From patchwork Fri Sep 3 11:20:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524240 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=MZf9jgL4; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1Fjw6rVqz9sSn for ; Fri, 3 Sep 2021 21:21:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348974AbhICLWh (ORCPT ); Fri, 3 Sep 2021 07:22:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348992AbhICLWd (ORCPT ); Fri, 3 Sep 2021 07:22:33 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 073EBC061757 for ; Fri, 3 Sep 2021 04:21:34 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id t15so7735285wrg.7 for ; Fri, 03 Sep 2021 04:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OdrRqNefaVNOxdAxmMezDhPAaaw5EYxGuh+OQAKyC64=; b=MZf9jgL44KooCVu8mMN7VD6E1sqJrRR4Un6fBlmbXSgAkooyoNJIxfm2rLMbfZ45Bx 1X4asN6/0tFW9Ii3P0KYRXheEEfgljB1ObgQAp5RGuxJpjIxKHH1IqDC/jkdZXJSsA4g pV5bsYYARP9T18adRSZn4l03mwsVLe2JENWTwRWjvaI7puKxGAUY7iazmae4oHfvyVo8 KX5agr5iZSnoIt7bbvPfjPJ7TRLYudyvGViOu5ptcFWjun2iwi7RLtOaLJ4lrn+NP0GB 0HHk+OQrJGo1IVsjlg6aUZPJLLZF1F33r4WPse5BzXn4JcS/ip0eY/p1QqeyWNXip/e+ AOsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OdrRqNefaVNOxdAxmMezDhPAaaw5EYxGuh+OQAKyC64=; b=hr4gXxCL1FsV8+2apTGUp1v8+Zdc8wA8AzblCjcxRJNXPEfjr/VwHesFjDEMBZMDOX E6XuCN79Tm1/hC4KsvAL7uvxJ0nqjZfgTI2ufmJpP7/9KOJyU3soRmTQ+1+vuvO3sZxv 8hJdZauwo1I3totwZKdWwR8CMx2qwsPIHImMXe+cJ+LCR8t+8qfWQRnwlx8inE+vgkpn qO4YdfHFUv6zmOr8nrucrE0Y9IO+EfsNtpwKovFHuoWf4A1ubwbw6BgnK1mKNao+dQFi c0wkla5wbYIITcI5C0yAc1OHTFdr1CE1d1GnG/+8Yy8qE9bxnb2Y7kE6GcgXpZUX1Ivl 6sLw== X-Gm-Message-State: AOAM531F7oSLYy2XrrrPdVqpi4zndzWBBv/ztsvnQG7nzbJ/As3QzhaQ zJ/4r4g0BkZgfEmIETeMpPr+up0dTj0CwQ== X-Google-Smtp-Source: ABdhPJyNXBTIOh0VizrOkpSTcSct2b2yUWXNmbx1TYEcCwIRb7Q5BMRHDbMa0FlLDwW17oRVHo6VXw== X-Received: by 2002:adf:eb8d:: with SMTP id t13mr3530333wrn.4.1630668092515; Fri, 03 Sep 2021 04:21:32 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:31 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 01/21] soc: dt-bindings: qcom: apr: convert to yaml Date: Fri, 3 Sep 2021 12:20:12 +0100 Message-Id: <20210903112032.25834-2-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert APR bindings to yaml format so that we could add new bindings support. All the dsp services bindings are now part of apr bindings instead of adding them to audio bindings. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/qcom/qcom,apr.txt | 134 ------------------ .../bindings/soc/qcom/qcom,apr.yaml | 128 +++++++++++++++++ 2 files changed, 128 insertions(+), 134 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt deleted file mode 100644 index 2e2f6dc351c0..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.txt +++ /dev/null @@ -1,134 +0,0 @@ -Qualcomm APR (Asynchronous Packet Router) binding - -This binding describes the Qualcomm APR. APR is a IPC protocol for -communication between Application processor and QDSP. APR is mainly -used for audio/voice services on the QDSP. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,apr-v", example "qcom,apr-v2" - -- qcom,apr-domain - Usage: required - Value type: - Definition: Destination processor ID. - Possible values are : - 1 - APR simulator - 2 - PC - 3 - MODEM - 4 - ADSP - 5 - APPS - 6 - MODEM2 - 7 - APPS2 - -= APR SERVICES -Each subnode of the APR node represents service tied to this apr. The name -of the nodes are not important. The properties of these nodes are defined -by the individual bindings for the specific service -- All APR services MUST contain the following property: - -- reg - Usage: required - Value type: - Definition: APR Service ID - Possible values are : - 3 - DSP Core Service - 4 - Audio Front End Service. - 5 - Voice Stream Manager Service. - 6 - Voice processing manager. - 7 - Audio Stream Manager Service. - 8 - Audio Device Manager Service. - 9 - Multimode voice manager. - 10 - Core voice stream. - 11 - Core voice processor. - 12 - Ultrasound stream manager. - 13 - Listen stream manager. - -- qcom,protection-domain - Usage: optional - Value type: - Definition: Must list the protection domain service name and path - that the particular apr service has a dependency on. - Possible values are : - "avs/audio", "msm/adsp/audio_pd". - "kernel/elf_loader", "msm/modem/wlan_pd". - "tms/servreg", "msm/adsp/audio_pd". - "tms/servreg", "msm/modem/wlan_pd". - "tms/servreg", "msm/slpi/sensor_pd". - -= EXAMPLE -The following example represents a QDSP based sound card on a MSM8996 device -which uses apr as communication between Apps and QDSP. - - apr { - compatible = "qcom,apr-v2"; - qcom,apr-domain = ; - - apr-service@3 { - compatible = "qcom,q6core"; - reg = ; - }; - - apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - - dais { - #sound-dai-cells = <1>; - dai@1 { - reg = ; - }; - }; - }; - - apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - ... - }; - - apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - ... - }; - }; - -= EXAMPLE 2 -The following example represents a QDSP based sound card with protection domain -dependencies specified. Here some of the apr services are dependent on services -running on protection domain hosted on ADSP/SLPI remote processors while others -have no such dependency. - - apr { - compatible = "qcom,apr-v2"; - qcom,glink-channels = "apr_audio_svc"; - qcom,apr-domain = ; - - apr-service@3 { - compatible = "qcom,q6core"; - reg = ; - }; - - q6afe: apr-service@4 { - compatible = "qcom,q6afe"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - ... - }; - - q6asm: apr-service@7 { - compatible = "qcom,q6asm"; - reg = ; - qcom,protection-domain = "tms/servreg", "msm/slpi/sensor_pd"; - ... - }; - - q6adm: apr-service@8 { - compatible = "qcom,q6adm"; - reg = ; - qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; - ... - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml new file mode 100644 index 000000000000..133e9c6cd961 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm APR (Asynchronous Packet Router) binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm APR, APR is a IPC protocol for + communication between Application processor and QDSP. APR is mainly + used for audio/voice services on the QDSP. + +properties: + compatible: + enum: + - qcom,apr-v2 + + qcom,apr-domain: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4, 5, 6, 7] + description: + Selects the processor domain for apr + 1 = APR simulator + 2 = PC Domain + 3 = Modem Domain + 4 = ADSP Domain + 5 = Application processor Domain + 6 = Modem2 Domain + 7 = Application Processor2 Domain + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +#APR Services +patternProperties: + "^service@[3-9a-d]$": + type: object + description: + APR node's client devices use subnodes for desired static port services. + + properties: + compatible: + enum: + - qcom,q6core + - qcom,q6asm + - qcom,q6afe + - qcom,q6adm + + reg: + enum: [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] + description: + APR Service ID + 3 = DSP Core Service + 4 = Audio Front End Service. + 5 = Voice Stream Manager Service. + 6 = Voice processing manager. + 7 = Audio Stream Manager Service. + 8 = Audio Device Manager Service. + 9 = Multimode voice manager. + 10 = Core voice stream. + 11 = Core voice processor. + 12 = Ultrasound stream manager. + 13 = Listen stream manager. + + qcom,protection-domain: + $ref: /schemas/types.yaml#/definitions/string-array + description: protection domain service name and path for apr service + possible values are + "avs/audio", "msm/adsp/audio_pd". + "kernel/elf_loader", "msm/modem/wlan_pd". + "tms/servreg", "msm/adsp/audio_pd". + "tms/servreg", "msm/modem/wlan_pd". + "tms/servreg", "msm/slpi/sensor_pd". + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + additionalProperties: false + +required: + - compatible + - qcom,apr-domain + +additionalProperties: false + +examples: + - | + #include + apr { + compatible = "qcom,apr-v2"; + qcom,apr-domain = ; + #address-cells = <1>; + #size-cells = <0>; + + q6core: service@3 { + compatible = "qcom,q6core"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + }; From patchwork Fri Sep 3 11:20:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524241 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=wmZS/Jpd; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1Fjx2MCqz9sW4 for ; Fri, 3 Sep 2021 21:21:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348992AbhICLWi (ORCPT ); Fri, 3 Sep 2021 07:22:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349241AbhICLWf (ORCPT ); Fri, 3 Sep 2021 07:22:35 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C402C061575 for ; Fri, 3 Sep 2021 04:21:35 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id g18so7723180wrc.11 for ; Fri, 03 Sep 2021 04:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=//dKqQtyVNezpAIRnDOA9TcRJZDgQ0d9R3BICS21tDc=; b=wmZS/JpdpDhKKOiUAcrscdLMLOUHMjFl5m+4MoOLjHpeYa7goPbKbBaCfQuPHBFdtR r6/+jssbulj32HuMqSQ48oFlcquv9/pzggC9xW/wPRY8wksFy7+r05H5ZdF+rNxS7kWS SA3Ktpm98Sm4ECMrwItZQ48B+E1BCGeVgyDNn4ylccO7YU7odqh8JwiHYtsh6ZzscUc4 kEaTgkZtUQjB9CenCE238k0C91+c/G+3EoeNeU1ecGHxo4MTbaYqUvMMcYPurlWAo0re e6My8mEfexB7InlMhXzSxuJiCK/skJuvyhmDkrOlAWT3Gb3LQnjSAzocKs/b0DC8nTYj i3/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=//dKqQtyVNezpAIRnDOA9TcRJZDgQ0d9R3BICS21tDc=; b=fe6538X18l5vuL5dmV9wk/ulI1Q71Xf/6l+xfQHk/DurTAO5XLSaVyCOcP3A8qG/p2 pfPYWns5xvjqyJe2id+aIFd4M9ttU6mULBXf7FR31TEJ2iw1HWJAEaL/cAo5RQ7Cbeas kYqUMfufNrm5UYeixrU/RFpzvvSuXN3IOsMhnVWYC2Tt01/9uLS6GGJbpr7t39pl99NS 7gVkQjqI2UxXDbBFwZoJVdYtfVvlvMQaGKiIZFGWhUH0O87zI9eIv8/ukeq2qs+JRhjM tA4ruCaDeFdBGmk4CO4NqsEdXozGS8fTRXXnWxj3icrfaF8A9tPXWpL3rINmCjDE0z1A /iLA== X-Gm-Message-State: AOAM531o+2v+rq4tahwuDGj1TxpW5lxVv6JeEmf+qVwP7IZa+wojfuMw P1z3h17wmljwj3k7F+7puHKOcw== X-Google-Smtp-Source: ABdhPJzdx00/bR6Zmsjxe4MaeAATmKIDg/ma7PcG8N0v6jOVuazg79rcvbgd8Gbxkzg43gNAaNMmug== X-Received: by 2002:adf:c550:: with SMTP id s16mr3529756wrf.25.1630668094060; Fri, 03 Sep 2021 04:21:34 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:33 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 02/21] soc: dt-bindings: qcom: apr: deprecate qcom,apr-domain property Date: Fri, 3 Sep 2021 12:20:13 +0100 Message-Id: <20210903112032.25834-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org replace usage of qcom,apr-domain property with qcom,domain property so that bindings and driver can be reused. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/qcom/qcom,apr.yaml | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index 133e9c6cd961..922c8567c134 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -31,6 +31,20 @@ properties: 5 = Application processor Domain 6 = Modem2 Domain 7 = Application Processor2 Domain + deprecated: true + + qcom,domain: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4, 5, 6, 7] + description: + Selects the processor domain for apr + 1 = APR simulator + 2 = PC Domain + 3 = Modem Domain + 4 = ADSP Domain + 5 = Application processor Domain + 6 = Modem2 Domain + 7 = Application Processor2 Domain '#address-cells': const: 1 @@ -89,7 +103,7 @@ patternProperties: required: - compatible - - qcom,apr-domain + - qcom,domain additionalProperties: false @@ -98,7 +112,7 @@ examples: #include apr { compatible = "qcom,apr-v2"; - qcom,apr-domain = ; + qcom,domain = ; #address-cells = <1>; #size-cells = <0>; From patchwork Fri Sep 3 11:20:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524242 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=CVAXc/zX; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1Fjx4mnsz9sRf for ; Fri, 3 Sep 2021 21:21:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349239AbhICLWj (ORCPT ); Fri, 3 Sep 2021 07:22:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349203AbhICLWi (ORCPT ); Fri, 3 Sep 2021 07:22:38 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 683E0C061575 for ; Fri, 3 Sep 2021 04:21:38 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id m9so7755487wrb.1 for ; Fri, 03 Sep 2021 04:21:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oIR90abl/sfH0/3DyNtRoQ8W4nkCYWxgXrfABfULtXI=; b=CVAXc/zX9vEav2VQvgoDC8dPYDc3W748VQ0PehfC9sjMqCVhP0F4LASBJnqWL511Tb CgEmYFJlgiU3X+sz9+iZGixzp0M2zKOjzvv7mZD3962fZ8bb7OGecY8h24p8/cF5JxD5 NKdLkHQflrXBCttI5eM134nItRcs3G3Ylt/4VNnFYpLwEbLqtSL2F+brYKxyu1M4uIYa kQkwkPebrICT64XpEAAOFvlxdCYJpcCLtjl2JQaef+tytBnyDaGo8clDtag7gkstALAK jbRneawn5xyIUD7dMax2bwG5PJIA0UdeO0wHGEGuCxj35on66f7lNP6fBhYxUU7fwLEz i4Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oIR90abl/sfH0/3DyNtRoQ8W4nkCYWxgXrfABfULtXI=; b=aP4sdsIQgNT1yrofZFG7WVjCe+qPmoZOGfRI/fjtJ+gv+LwsN+AnyIFwgFiu3g4oL4 85/ABZzFc0eFrFzE4l1L5lEKa2oelWC3tG/biUB2yYIjtFMeWiiZphyaGOiZW9TMfljG NlbwWngt90rB7Cq+AQZ4LZ6lY7SpsK9n2PfltgrtnA/RgjPBVFpd/kSYjiG3QqFt249O 7Li4uwIjspmr6yuipwCx9OorWXOrcKFcFcU5lK5zMm2uW/UD/zPj76CXgiXSxmpuZRMM U/fvX4OW1Ut4mJM8rDD0RP+/YvJPZ+3vtI4JeqWGevhZ1qqNqXDEnUxEHsdyOQZxnSoP 3SGA== X-Gm-Message-State: AOAM533BZcxGi7j2HylGcCgvX3YYzZAUYFz6uGMb9CpoL0tVdwsTWWCd b3nfDOUi2GXyD37bI/OGYtwOCQ== X-Google-Smtp-Source: ABdhPJytDaDGeJG/cmR9NCL+XRcdKTrmZNjIxwCqvaSPY/9YonjkIby0wBE5LE4gqijdQ1U4W5qxpQ== X-Received: by 2002:a5d:67c3:: with SMTP id n3mr3454870wrw.201.1630668096971; Fri, 03 Sep 2021 04:21:36 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:36 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 04/21] soc: dt-bindings: qcom: add gpr bindings Date: Fri, 3 Sep 2021 12:20:15 +0100 Message-Id: <20210903112032.25834-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm Generic Packet router aka GPR is the IPC mechanism found in AudioReach next generation signal processing framework to perform command and response messages between various processors. GPR has concepts of static and dynamic port, all static services like APM (Audio Processing Manager), PRM (Proxy resource manager) have fixed port numbers where as dynamic services like graphs have dynamic port numbers which are allocated at runtime. All GPR packet messages will have source and destination domain and port along with opcode and payload. This support is added using existing APR driver to reuse most of the code. Signed-off-by: Srinivas Kandagatla --- .../bindings/soc/qcom/qcom,apr.yaml | 41 +++++++++++++++---- include/dt-bindings/soc/qcom,gpr.h | 18 ++++++++ 2 files changed, 52 insertions(+), 7 deletions(-) create mode 100644 include/dt-bindings/soc/qcom,gpr.h diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index 922c8567c134..14d75f6a556e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -4,20 +4,21 @@ $id: "http://devicetree.org/schemas/soc/qcom/qcom,apr.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Qualcomm APR (Asynchronous Packet Router) binding +title: Qualcomm APR/GPR (Asynchronous/Generic Packet Router) binding maintainers: - Srinivas Kandagatla description: | - This binding describes the Qualcomm APR, APR is a IPC protocol for - communication between Application processor and QDSP. APR is mainly + This binding describes the Qualcomm APR/GPR, APR/GPR is a IPC protocol for + communication between Application processor and QDSP. APR/GPR is mainly used for audio/voice services on the QDSP. properties: compatible: enum: - qcom,apr-v2 + - qcom,gpr qcom,apr-domain: $ref: /schemas/types.yaml#/definitions/uint32 @@ -45,6 +46,10 @@ properties: 5 = Application processor Domain 6 = Modem2 Domain 7 = Application Processor2 Domain + Selects the processor domain for gpr + 1 = Modem Domain + 2 = Audio DSP Domain + 3 = Application Processor Domain '#address-cells': const: 1 @@ -52,12 +57,12 @@ properties: '#size-cells': const: 0 -#APR Services +#APR/GPR Services patternProperties: - "^service@[3-9a-d]$": + "^service@[1-9a-d]$": type: object description: - APR node's client devices use subnodes for desired static port services. + APR/GPR node's client devices use subnodes for desired static port services. properties: compatible: @@ -66,9 +71,11 @@ patternProperties: - qcom,q6asm - qcom,q6afe - qcom,q6adm + - qcom,q6apm + - qcom,q6prm reg: - enum: [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] + enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] description: APR Service ID 3 = DSP Core Service @@ -82,6 +89,11 @@ patternProperties: 11 = Core voice processor. 12 = Ultrasound stream manager. 13 = Listen stream manager. + GPR Service ID + 1 = Audio Process Manager Service + 2 = Proxy Resource Manager Service. + 3 = AMDB Service. + 4 = Voice processing manager. qcom,protection-domain: $ref: /schemas/types.yaml#/definitions/string-array @@ -140,3 +152,18 @@ examples: qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; }; }; + + - | + #include + gpr { + compatible = "qcom,gpr"; + qcom,domain = ; + #address-cells = <1>; + #size-cells = <0>; + + service@1 { + compatible = "qcom,q6apm"; + reg = ; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + }; diff --git a/include/dt-bindings/soc/qcom,gpr.h b/include/dt-bindings/soc/qcom,gpr.h new file mode 100644 index 000000000000..1c68906e079c --- /dev/null +++ b/include/dt-bindings/soc/qcom,gpr.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_QCOM_GPR_H +#define __DT_BINDINGS_QCOM_GPR_H + +/* DOMAINS */ + +#define GPR_DOMAIN_ID_MODEM 1 +#define GPR_DOMAIN_ID_ADSP 2 +#define GPR_DOMAIN_ID_APPS 3 + +/* Static Services */ + +#define GPR_APM_MODULE_IID 1 +#define GPR_PRM_MODULE_IID 2 +#define GPR_AMDB_MODULE_IID 3 +#define GPR_VCPM_MODULE_IID 4 + +#endif /* __DT_BINDINGS_QCOM_GPR_H */ From patchwork Fri Sep 3 11:20:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524243 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=XGrE8BHH; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1Fjy4zqSz9sRf for ; Fri, 3 Sep 2021 21:21:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348486AbhICLWl (ORCPT ); Fri, 3 Sep 2021 07:22:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348457AbhICLWl (ORCPT ); Fri, 3 Sep 2021 07:22:41 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E91BC061575 for ; Fri, 3 Sep 2021 04:21:41 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id k20-20020a05600c0b5400b002e87ad6956eso3334860wmr.1 for ; Fri, 03 Sep 2021 04:21:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=47v/fQQP0+XqFFjvLWMPsTUHxde1y35xEPXbN5jqyCE=; b=XGrE8BHHWd9wa/oiyUW2f2KXA7RCWl+E4RMCcsfW5N3msGog4sW15fqT+BMks/ohhl fsdjzP+rBXkavvwp144S6XE1Mu6a1jTuXQ2uVaCd+sYXCl951yglHTB2u95mmYKBYpXt H4XCa1LHjfTwQJnAp32RxvNKQR+286uJir/XNcv3548VAT8zTqNoCmGjz/fZESYzqWRE 1zsx7YR2h3rE/0Q/G9FwCdtee2OeD5uAE/H+QZOGdgMXAssQiWdsttMQhfgk0oud+FiL /Y+jty4s1ZyH5YiKoASwv8jHzEsT2WsftGu6H5iAx/gqcSW9vjuDebXQZGAzMWSHRkw+ vZ3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=47v/fQQP0+XqFFjvLWMPsTUHxde1y35xEPXbN5jqyCE=; b=MdyQ+0JAyQj6BJD7E1u7QNm1iLywO9/oKu4pKPhLgGSTd66Z3g5Gd6tehSNo+vwOdl S1cPEl4ip95LNmOEHnPcnUb5p2lUhHY+W+nd0dHuJQ6nl45vhGlYiSugHZ/IkEwpzFhO 00eeIjZerTP6/c/4i5231kROtMvuVrKArcP+Ha7Vz+b3itPI+QfslVdapadGIm0sE70R A5og6o00msjf4dweUCfcfCkCmIe8LbVLvthWrzdIrZDjzl3j6vPleCtdph3xX3SuZKyL LlBXgSqaJ4pKKghT/pNEeEexKI+yXoZGBMTQV3HrQdMKBrNaCX+1b/z53WiQq5AXduDW WGbg== X-Gm-Message-State: AOAM530CKXZmLKnoVepUOD6i45DZqblseSqYpFUpzfvrEL4+tM1NTyRZ o+VNPQqP6Cxff6sFyMJlBvD5cg== X-Google-Smtp-Source: ABdhPJxYGh0C+gBCntK6c4LX9Mjg8t8QaePxlE1zQseLE96+GH1YEXHIrbfothz4IQv/OlT72WLH1A== X-Received: by 2002:a05:600c:221a:: with SMTP id z26mr2797769wml.142.1630668099542; Fri, 03 Sep 2021 04:21:39 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:39 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 06/21] ASoC: dt-bindings: move LPASS dai related bindings out of q6afe Date: Fri, 3 Sep 2021 12:20:17 +0100 Message-Id: <20210903112032.25834-7-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org q6afe (Audio Front End) is one of the DSP service that handles both LPASS (Low Power Audio SubSystem) Audio ports and LPASS clocks. As LPASS is a hardwware IP and commonly used by Qualcomm Audio DSP. In order to allow multiple DSP frameworks to use these bindings its best to move it out from the dsp specific bindings. For compatibility reasons and not breaking which is already working we still maintain same compatible string "qcom,q6afe-dais" Also as part of this change convert these LPASS dai related bindings into yaml format. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../devicetree/bindings/sound/qcom,q6afe.txt | 158 ---------------- .../sound/qcom,q6dsp-lpass-ports.yaml | 178 ++++++++++++++++++ 2 files changed, 178 insertions(+), 158 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt index 2d6fb2ea75a0..fcf81058504c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt +++ b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt @@ -12,92 +12,6 @@ used by all apr services. Must contain the following properties. from DSP. example "qcom,q6afe" -= AFE DAIs (Digial Audio Interface) -"dais" subnode of the AFE node. It represents afe dais, each afe dai is a -subnode of "dais" representing board specific dai setup. -"dais" node should have following properties followed by dai children. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-dais" - -- #sound-dai-cells - Usage: required - Value type: - Definition: Must be 1 - -- #address-cells - Usage: required - Value type: - Definition: Must be 1 - -- #size-cells - Usage: required - Value type: - Definition: Must be 0 - -== AFE DAI is subnode of "dais" and represent a dai, it includes board specific -configuration of each dai. Must contain the following properties. - -- reg - Usage: required - Value type: - Definition: Must be dai id - -- qcom,sd-lines - Usage: required for mi2s interface - Value type: - Definition: Must be list of serial data lines used by this dai. - should be one or more of the 0-3 sd lines. - - - qcom,tdm-sync-mode: - Usage: required for tdm interface - Value type: - Definition: Synchronization mode. - 0 - Short sync bit mode - 1 - Long sync mode - 2 - Short sync slot mode - - - qcom,tdm-sync-src: - Usage: required for tdm interface - Value type: - Definition: Synchronization source. - 0 - External source - 1 - Internal source - - - qcom,tdm-data-out: - Usage: required for tdm interface - Value type: - Definition: Data out signal to drive with other masters. - 0 - Disable - 1 - Enable - - - qcom,tdm-invert-sync: - Usage: required for tdm interface - Value type: - Definition: Invert the sync. - 0 - Normal - 1 - Invert - - - qcom,tdm-data-delay: - Usage: required for tdm interface - Value type: - Definition: Number of bit clock to delay data - with respect to sync edge. - 0 - 0 bit clock cycle - 1 - 1 bit clock cycle - 2 - 2 bit clock cycle - - - qcom,tdm-data-align: - Usage: required for tdm interface - Value type: - Definition: Indicate how data is packed - within the slot. For example, 32 slot width in case of - sample bit width is 24. - 0 - MSB - 1 - LSB - = AFE CLOCKSS "clocks" subnode of the AFE node. It represents q6afe clocks "clocks" node should have following properties. @@ -122,78 +36,6 @@ apr-service@4 { compatible = "qcom,q6afe"; reg = ; - dais { - compatible = "qcom,q6afe-dais"; - #sound-dai-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - dai@1 { - reg = ; - }; - - dai@24 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay = <1>; - qcom,tdm-data-align = <0>; - - }; - - dai@25 { - reg = ; - qcom,tdm-sync-mode = <1>: - qcom,tdm-sync-src = <1>; - qcom,tdm-data-out = <0>; - qcom,tdm-invert-sync = <1>; - qcom,tdm-data-delay <1>: - qcom,tdm-data-align = <0>; - }; - - dai@16 { - reg = ; - qcom,sd-lines = <0 2>; - }; - - dai@17 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@18 { - reg = ; - qcom,sd-lines = <0 3>; - }; - - dai@19 { - reg = ; - qcom,sd-lines = <1>; - }; - - dai@20 { - reg = ; - qcom,sd-lines = <1 3>; - }; - - dai@21 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@22 { - reg = ; - qcom,sd-lines = <0>; - }; - - dai@23 { - reg = ; - qcom,sd-lines = <1>; - }; - }; - clocks { compatible = "qcom,q6afe-clocks"; #clock-cells = <2>; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml new file mode 100644 index 000000000000..e6148c17419b --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-ports.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS(Low Power Audio SubSystem) Audio Ports binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP LPASS Audio ports + +properties: + compatible: + enum: + - qcom,q6afe-dais + + reg: + maxItems: 1 + + '#sound-dai-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +#Digital Audio Interfaces +patternProperties: + '^dai@[0-9]+$': + type: object + description: + Q6DSP Digital Audio Interfaces. + + properties: + reg: + description: + Digital Audio Interface ID + + qcom,sd-lines: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of serial data lines used by this dai.should be one or more of the 0-3 sd lines. + minItems: 1 + maxItems: 4 + uniqueItems: true + items: + minimum: 0 + maximum: 3 + + qcom,tdm-sync-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Synchronization mode + 0 = Short sync bit mode + 1 = Long sync mode + 2 = Short sync slot mode + + qcom,tdm-sync-src: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Synchronization source + 0 = External source + 1 = Internal source + + qcom,tdm-data-out: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Data out signal to drive with other masters + 0 = Disable + 1 = Enable + + qcom,tdm-invert-sync: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + TDM Invert the sync + 0 = Normal + 1 = Invert + + qcom,tdm-data-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + TDM Number of bit clock to delay data + 0 = 0 bit clock cycle + 1 = 1 bit clock cycle + 2 = 2 bit clock cycle + + qcom,tdm-data-align: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Indicate how data is packed within the slot. For example, 32 slot + width in case of sample bit width is 24TDM Invert the sync. + 0 = MSB + 1 = LSB + + required: + - reg + + allOf: + - if: + properties: + reg: + contains: + # TDM DAI ID range from PRIMARY_TDM_RX_0 - QUINARY_TDM_TX_7 + items: + minimum: 24 + maximum: 103 + then: + required: + - qcom,tdm-sync-mode + - qcom,tdm-sync-src + - qcom,tdm-data-out + - qcom,tdm-invert-sync + - qcom,tdm-data-delay + - qcom,tdm-data-align + + - if: + properties: + reg: + contains: + # MI2S DAI ID range PRIMARY_MI2S_RX - QUATERNARY_MI2S_TX and + # QUINARY_MI2S_RX - QUINARY_MI2S_TX + items: + oneOf: + - minimum: 16 + maximum: 23 + - minimum: 127 + maximum: 128 + then: + required: + - qcom,sd-lines + + additionalProperties: false + +required: + - compatible + - reg + - "#sound-dai-cells" + - "#address-cells" + - "#size-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6afedai@1 { + compatible = "qcom,q6afe-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; From patchwork Fri Sep 3 11:20:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524244 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=Ltqb+2DW; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1Fjz4Tbzz9sRf for ; Fri, 3 Sep 2021 21:21:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348629AbhICLWm (ORCPT ); Fri, 3 Sep 2021 07:22:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348457AbhICLWm (ORCPT ); Fri, 3 Sep 2021 07:22:42 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E885C061575 for ; Fri, 3 Sep 2021 04:21:42 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id m2so3300053wmm.0 for ; Fri, 03 Sep 2021 04:21:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d5Vm8czTL3+cyI2rjmlcRETsvgdq2hCBoaTdt0tcxRk=; b=Ltqb+2DW00gH5hFRPHIiqQanWa6ocu1K9klT2CfkuvbUEuikwLK4Fn+oyiBkF9Jf+W J6phSBiX/crjJn5g+kkLhQBulesHkz/+OXWp14Xp9uWsMBJSMibOZZ/9cESfHSnN30B8 X8CghO5CfQle9eMwgK695zphiyZ5yzfa+NsQEJtvnvo/ZGE7R9GUH1DSFGbY1F+hP7OH LWUuIuTcHifulaPWqF9u15CTC39IgiT+iSppf1zN9gzVqzppv4SVcdmtiUtBgbv7wMxt CJ6CYJrPA/u55tBBdNVXE0hOP/Vhg5TYK8CW3n0MgQm5Kc3l7T5ZnyJnyhNar8U98cit NXjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d5Vm8czTL3+cyI2rjmlcRETsvgdq2hCBoaTdt0tcxRk=; b=PTyFLIWKkjXPOKUq86RVu704ZM4cp4+aOsMcrl0NmwDb8YKgFFYXj8xmUsaqtTpm7A J/EG5n4FC4cHtN6lfSz0+zT/iZEGHbDYlVjcw7BvCnomkix+JdVdcVdEKARj3XSqsl/5 1VxZqW7y8NaGH+BXG1x4uw958xkdiei/UWh3g41gHTuMiOaRLlKCHT1KpCacchM5GTXD 93iU23x6VHcl8LDqMDSiz186g+tJrd4ZoGU+XdvWW94pMVS0XC6EWf1yDmuqVFPpPSe/ AtTwpDrCTeNlt1m9iSyAAlg+9cQ6pmST7DbWHN7WvHttiv8UPhFUM/po3E0xS3jhWnBC VpSQ== X-Gm-Message-State: AOAM531sZNMG+do44R60XWBZFwrReQow+b8DaHngMGwJmLguxxlExM1o PJXdXhRsLmTZTx0fe3clMmaGhw== X-Google-Smtp-Source: ABdhPJwD6vgMakshKTex1cn0m+Z670al13ANnqwiTM9bLMjwHtOYTC2n8odz9s/AQHWE+BrDAQdlYA== X-Received: by 2002:a1c:1d84:: with SMTP id d126mr2836057wmd.160.1630668100851; Fri, 03 Sep 2021 04:21:40 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:40 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 07/21] ASoC: dt-bindings: move LPASS clocks related bindings out of q6afe Date: Fri, 3 Sep 2021 12:20:18 +0100 Message-Id: <20210903112032.25834-8-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org q6afe (Audio Front End) is one of the DSP service that handles both LPASS (Low Power Audio SubSystem) Audio ports and LPASS clocks. As LPASS is a hardwware IP and commonly used by Qualcomm Audio DSP. In order to allow multiple DSP frameworks to use these bindings its best to move it out from the dsp specific bindings. For compatibility reasons and not breaking which is already working we still maintain same compatible string "qcom,q6afe-clocks" Also as part of this change convert these LPASS clocks related bindings into yaml format. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../devicetree/bindings/sound/qcom,q6afe.txt | 23 -------- .../sound/qcom,q6dsp-lpass-clocks.yaml | 56 +++++++++++++++++++ 2 files changed, 56 insertions(+), 23 deletions(-) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml diff --git a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt index fcf81058504c..bc6b5f1fe4f1 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6afe.txt +++ b/Documentation/devicetree/bindings/sound/qcom,q6afe.txt @@ -12,32 +12,9 @@ used by all apr services. Must contain the following properties. from DSP. example "qcom,q6afe" -= AFE CLOCKSS -"clocks" subnode of the AFE node. It represents q6afe clocks -"clocks" node should have following properties. -- compatible: - Usage: required - Value type: - Definition: must be "qcom,q6afe-clocks" - -- #clock-cells: - Usage: required - Value type: - Definition: Must be 2. Clock Id followed by - below valid clock coupling attributes. - 1 - for no coupled clock - 2 - for dividend of the coupled clock - 3 - for divisor of the coupled clock - 4 - for inverted and no couple clock - = EXAMPLE apr-service@4 { compatible = "qcom,q6afe"; reg = ; - - clocks { - compatible = "qcom,q6afe-clocks"; - #clock-cells = <2>; - }; }; diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml new file mode 100644 index 000000000000..589c3f1e2008 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6dsp-lpass-clocks.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm DSP LPASS Clock Controller binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm DSP Clock Controller + +properties: + compatible: + enum: + - qcom,q6afe-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 2 + description: + Clock Id is followed by clock coupling attributes. + 1 = for no coupled clock + 2 = for dividend of the coupled clock + 3 = for divisor of the coupled clock + 4 = for inverted and no couple clock + +required: + - compatible + - reg + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + #include + apr { + #address-cells = <1>; + #size-cells = <0>; + apr-service@4 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6afecc@2 { + compatible = "qcom,q6afe-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; From patchwork Fri Sep 3 11:20:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524245 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=e6+fImB2; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1Fk06vP6z9sSn for ; Fri, 3 Sep 2021 21:21:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348681AbhICLWn (ORCPT ); Fri, 3 Sep 2021 07:22:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348457AbhICLWn (ORCPT ); Fri, 3 Sep 2021 07:22:43 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 78270C061575 for ; Fri, 3 Sep 2021 04:21:43 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id x6so7704182wrv.13 for ; Fri, 03 Sep 2021 04:21:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jONUN0C6XA6UJsv3RxwoGrHmtYxRlaTGrHYolrxpDUg=; b=e6+fImB2E0yZrDQkgzhG9uaikbDcLMEoD94s4WdFl22Fy0pYVavjy60j3YwP4Yd3L+ xigJx/HXmRwmkqpWBLILtl8VV1G9hJyrNXVCyr4Cqq9c1UXhhDuquiIo6XQjpn/jLCX+ KSKZS2dSgUkP20h/PLhEvUweUpSMYueJUMIsrE7/sJobG4WOAiEO7C1XIiNgqKVx0Mb9 NyPYMljiOHOzwF7+WMi/BmFj6U0PKAm9cPWNoc3g9jWyDwqG0qW9VAR5BR3XRmUBckER QYAf912xjksmucIB2pIyq775QS5tbPEXBnl4UYCu30GD9kUegcO+HBsZpuBRyJbTOO// ZWqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jONUN0C6XA6UJsv3RxwoGrHmtYxRlaTGrHYolrxpDUg=; b=B290z8KWxnG2qmkiEgXtvNjN7rqj185j3tp0Dyyp2JWQMb7pdSGetzQeUfNKx/I+Fc m24jyfnqPpchD11bH/NzZMzNvzQ7n4aE6RfO2ik+o9LGMDQ4PT2LSRiy+Fif/IPXWW6s yCNUu7uT64e7YkD42F0EYeS3ohmlVvyK1tNLwfbXCWmtKRdWXYSSWu2w56amq/XKSbat m+YJmPYzTvS/TP5/zqZRa4IDsr+I7yFRJrCACKSuUZqJcmeUlqNzGs1HqjPbycI63XfO O4N3I+ZPddrIJ7vlQ+mhGaw0FCVDAP1YD2T8IN05oP2T7IJk+jHBNJKzebG92/mkZjMO YtmA== X-Gm-Message-State: AOAM532I30kSSH8eOX80cqYw5fYNNVyGwooESwgcjR6VEQju1jMWnKE9 799wdZp56mMhqph2QoyQ0ODzCA== X-Google-Smtp-Source: ABdhPJw84qayxX7EGr8q2Pjz/FH/8xAFo185S00fXDg35mgcmRC/eiep5pkqHzJDQ2PiLg37AflZQQ== X-Received: by 2002:a5d:6a08:: with SMTP id m8mr3491050wru.269.1630668101995; Fri, 03 Sep 2021 04:21:41 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:41 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 08/21] ASoC: dt-bindings: rename q6afe.h to q6dsp-lpass-ports.h Date: Fri, 3 Sep 2021 12:20:19 +0100 Message-Id: <20210903112032.25834-9-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org move all LPASS audio ports defines from q6afe.h to q6dsp-lpass-ports.h as these belong to LPASS IP. Also this move helps in reusing this header across multiple audio frameworks on Qualcomm Audio DSP. This patch is split out of the dt-bindings patch to enable easy review. Signed-off-by: Srinivas Kandagatla Acked-by: Rob Herring --- include/dt-bindings/sound/qcom,q6afe.h | 203 +---------------- .../sound/qcom,q6dsp-lpass-ports.h | 208 ++++++++++++++++++ 2 files changed, 210 insertions(+), 201 deletions(-) create mode 100644 include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h index 66c21ab03eef..9d5d89cfabcf 100644 --- a/include/dt-bindings/sound/qcom,q6afe.h +++ b/include/dt-bindings/sound/qcom,q6afe.h @@ -2,207 +2,8 @@ #ifndef __DT_BINDINGS_Q6_AFE_H__ #define __DT_BINDINGS_Q6_AFE_H__ -/* Audio Front End (AFE) virtual ports IDs */ -#define HDMI_RX 1 -#define SLIMBUS_0_RX 2 -#define SLIMBUS_0_TX 3 -#define SLIMBUS_1_RX 4 -#define SLIMBUS_1_TX 5 -#define SLIMBUS_2_RX 6 -#define SLIMBUS_2_TX 7 -#define SLIMBUS_3_RX 8 -#define SLIMBUS_3_TX 9 -#define SLIMBUS_4_RX 10 -#define SLIMBUS_4_TX 11 -#define SLIMBUS_5_RX 12 -#define SLIMBUS_5_TX 13 -#define SLIMBUS_6_RX 14 -#define SLIMBUS_6_TX 15 -#define PRIMARY_MI2S_RX 16 -#define PRIMARY_MI2S_TX 17 -#define SECONDARY_MI2S_RX 18 -#define SECONDARY_MI2S_TX 19 -#define TERTIARY_MI2S_RX 20 -#define TERTIARY_MI2S_TX 21 -#define QUATERNARY_MI2S_RX 22 -#define QUATERNARY_MI2S_TX 23 -#define PRIMARY_TDM_RX_0 24 -#define PRIMARY_TDM_TX_0 25 -#define PRIMARY_TDM_RX_1 26 -#define PRIMARY_TDM_TX_1 27 -#define PRIMARY_TDM_RX_2 28 -#define PRIMARY_TDM_TX_2 29 -#define PRIMARY_TDM_RX_3 30 -#define PRIMARY_TDM_TX_3 31 -#define PRIMARY_TDM_RX_4 32 -#define PRIMARY_TDM_TX_4 33 -#define PRIMARY_TDM_RX_5 34 -#define PRIMARY_TDM_TX_5 35 -#define PRIMARY_TDM_RX_6 36 -#define PRIMARY_TDM_TX_6 37 -#define PRIMARY_TDM_RX_7 38 -#define PRIMARY_TDM_TX_7 39 -#define SECONDARY_TDM_RX_0 40 -#define SECONDARY_TDM_TX_0 41 -#define SECONDARY_TDM_RX_1 42 -#define SECONDARY_TDM_TX_1 43 -#define SECONDARY_TDM_RX_2 44 -#define SECONDARY_TDM_TX_2 45 -#define SECONDARY_TDM_RX_3 46 -#define SECONDARY_TDM_TX_3 47 -#define SECONDARY_TDM_RX_4 48 -#define SECONDARY_TDM_TX_4 49 -#define SECONDARY_TDM_RX_5 50 -#define SECONDARY_TDM_TX_5 51 -#define SECONDARY_TDM_RX_6 52 -#define SECONDARY_TDM_TX_6 53 -#define SECONDARY_TDM_RX_7 54 -#define SECONDARY_TDM_TX_7 55 -#define TERTIARY_TDM_RX_0 56 -#define TERTIARY_TDM_TX_0 57 -#define TERTIARY_TDM_RX_1 58 -#define TERTIARY_TDM_TX_1 59 -#define TERTIARY_TDM_RX_2 60 -#define TERTIARY_TDM_TX_2 61 -#define TERTIARY_TDM_RX_3 62 -#define TERTIARY_TDM_TX_3 63 -#define TERTIARY_TDM_RX_4 64 -#define TERTIARY_TDM_TX_4 65 -#define TERTIARY_TDM_RX_5 66 -#define TERTIARY_TDM_TX_5 67 -#define TERTIARY_TDM_RX_6 68 -#define TERTIARY_TDM_TX_6 69 -#define TERTIARY_TDM_RX_7 70 -#define TERTIARY_TDM_TX_7 71 -#define QUATERNARY_TDM_RX_0 72 -#define QUATERNARY_TDM_TX_0 73 -#define QUATERNARY_TDM_RX_1 74 -#define QUATERNARY_TDM_TX_1 75 -#define QUATERNARY_TDM_RX_2 76 -#define QUATERNARY_TDM_TX_2 77 -#define QUATERNARY_TDM_RX_3 78 -#define QUATERNARY_TDM_TX_3 79 -#define QUATERNARY_TDM_RX_4 80 -#define QUATERNARY_TDM_TX_4 81 -#define QUATERNARY_TDM_RX_5 82 -#define QUATERNARY_TDM_TX_5 83 -#define QUATERNARY_TDM_RX_6 84 -#define QUATERNARY_TDM_TX_6 85 -#define QUATERNARY_TDM_RX_7 86 -#define QUATERNARY_TDM_TX_7 87 -#define QUINARY_TDM_RX_0 88 -#define QUINARY_TDM_TX_0 89 -#define QUINARY_TDM_RX_1 90 -#define QUINARY_TDM_TX_1 91 -#define QUINARY_TDM_RX_2 92 -#define QUINARY_TDM_TX_2 93 -#define QUINARY_TDM_RX_3 94 -#define QUINARY_TDM_TX_3 95 -#define QUINARY_TDM_RX_4 96 -#define QUINARY_TDM_TX_4 97 -#define QUINARY_TDM_RX_5 98 -#define QUINARY_TDM_TX_5 99 -#define QUINARY_TDM_RX_6 100 -#define QUINARY_TDM_TX_6 101 -#define QUINARY_TDM_RX_7 102 -#define QUINARY_TDM_TX_7 103 -#define DISPLAY_PORT_RX 104 -#define WSA_CODEC_DMA_RX_0 105 -#define WSA_CODEC_DMA_TX_0 106 -#define WSA_CODEC_DMA_RX_1 107 -#define WSA_CODEC_DMA_TX_1 108 -#define WSA_CODEC_DMA_TX_2 109 -#define VA_CODEC_DMA_TX_0 110 -#define VA_CODEC_DMA_TX_1 111 -#define VA_CODEC_DMA_TX_2 112 -#define RX_CODEC_DMA_RX_0 113 -#define TX_CODEC_DMA_TX_0 114 -#define RX_CODEC_DMA_RX_1 115 -#define TX_CODEC_DMA_TX_1 116 -#define RX_CODEC_DMA_RX_2 117 -#define TX_CODEC_DMA_TX_2 118 -#define RX_CODEC_DMA_RX_3 119 -#define TX_CODEC_DMA_TX_3 120 -#define RX_CODEC_DMA_RX_4 121 -#define TX_CODEC_DMA_TX_4 122 -#define RX_CODEC_DMA_RX_5 123 -#define TX_CODEC_DMA_TX_5 124 -#define RX_CODEC_DMA_RX_6 125 -#define RX_CODEC_DMA_RX_7 126 -#define QUINARY_MI2S_RX 127 -#define QUINARY_MI2S_TX 128 +/* This file exists due to backward compatibility reasons, Please do not DELETE! */ -#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 -#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 -#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 -#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 -#define LPASS_CLK_ID_TER_MI2S_IBIT 5 -#define LPASS_CLK_ID_TER_MI2S_EBIT 6 -#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 -#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 -#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 -#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 -#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 -#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 -#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 -#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 -#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 -#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 -#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 -#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 -#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 -#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 -#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 -#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 -#define LPASS_CLK_ID_QUI_MI2S_OSR 23 -#define LPASS_CLK_ID_PRI_PCM_IBIT 24 -#define LPASS_CLK_ID_PRI_PCM_EBIT 25 -#define LPASS_CLK_ID_SEC_PCM_IBIT 26 -#define LPASS_CLK_ID_SEC_PCM_EBIT 27 -#define LPASS_CLK_ID_TER_PCM_IBIT 28 -#define LPASS_CLK_ID_TER_PCM_EBIT 29 -#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 -#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 -#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 -#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 -#define LPASS_CLK_ID_QUI_PCM_OSR 34 -#define LPASS_CLK_ID_PRI_TDM_IBIT 35 -#define LPASS_CLK_ID_PRI_TDM_EBIT 36 -#define LPASS_CLK_ID_SEC_TDM_IBIT 37 -#define LPASS_CLK_ID_SEC_TDM_EBIT 38 -#define LPASS_CLK_ID_TER_TDM_IBIT 39 -#define LPASS_CLK_ID_TER_TDM_EBIT 40 -#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 -#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 -#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 -#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 -#define LPASS_CLK_ID_QUIN_TDM_OSR 45 -#define LPASS_CLK_ID_MCLK_1 46 -#define LPASS_CLK_ID_MCLK_2 47 -#define LPASS_CLK_ID_MCLK_3 48 -#define LPASS_CLK_ID_MCLK_4 49 -#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 -#define LPASS_CLK_ID_INT_MCLK_0 51 -#define LPASS_CLK_ID_INT_MCLK_1 52 -#define LPASS_CLK_ID_MCLK_5 53 -#define LPASS_CLK_ID_WSA_CORE_MCLK 54 -#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 -#define LPASS_CLK_ID_VA_CORE_MCLK 56 -#define LPASS_CLK_ID_TX_CORE_MCLK 57 -#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 -#define LPASS_CLK_ID_RX_CORE_MCLK 59 -#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 -#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 - -#define LPASS_HW_AVTIMER_VOTE 101 -#define LPASS_HW_MACRO_VOTE 102 -#define LPASS_HW_DCODEC_VOTE 103 - -#define Q6AFE_MAX_CLK_ID 104 - -#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 -#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 -#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 +#include #endif /* __DT_BINDINGS_Q6_AFE_H__ */ diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h new file mode 100644 index 000000000000..0d3276c8fc11 --- /dev/null +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_Q6_AUDIO_PORTS_H__ +#define __DT_BINDINGS_Q6_AUDIO_PORTS_H__ + +/* LPASS Audio virtual ports IDs */ +#define HDMI_RX 1 +#define SLIMBUS_0_RX 2 +#define SLIMBUS_0_TX 3 +#define SLIMBUS_1_RX 4 +#define SLIMBUS_1_TX 5 +#define SLIMBUS_2_RX 6 +#define SLIMBUS_2_TX 7 +#define SLIMBUS_3_RX 8 +#define SLIMBUS_3_TX 9 +#define SLIMBUS_4_RX 10 +#define SLIMBUS_4_TX 11 +#define SLIMBUS_5_RX 12 +#define SLIMBUS_5_TX 13 +#define SLIMBUS_6_RX 14 +#define SLIMBUS_6_TX 15 +#define PRIMARY_MI2S_RX 16 +#define PRIMARY_MI2S_TX 17 +#define SECONDARY_MI2S_RX 18 +#define SECONDARY_MI2S_TX 19 +#define TERTIARY_MI2S_RX 20 +#define TERTIARY_MI2S_TX 21 +#define QUATERNARY_MI2S_RX 22 +#define QUATERNARY_MI2S_TX 23 +#define PRIMARY_TDM_RX_0 24 +#define PRIMARY_TDM_TX_0 25 +#define PRIMARY_TDM_RX_1 26 +#define PRIMARY_TDM_TX_1 27 +#define PRIMARY_TDM_RX_2 28 +#define PRIMARY_TDM_TX_2 29 +#define PRIMARY_TDM_RX_3 30 +#define PRIMARY_TDM_TX_3 31 +#define PRIMARY_TDM_RX_4 32 +#define PRIMARY_TDM_TX_4 33 +#define PRIMARY_TDM_RX_5 34 +#define PRIMARY_TDM_TX_5 35 +#define PRIMARY_TDM_RX_6 36 +#define PRIMARY_TDM_TX_6 37 +#define PRIMARY_TDM_RX_7 38 +#define PRIMARY_TDM_TX_7 39 +#define SECONDARY_TDM_RX_0 40 +#define SECONDARY_TDM_TX_0 41 +#define SECONDARY_TDM_RX_1 42 +#define SECONDARY_TDM_TX_1 43 +#define SECONDARY_TDM_RX_2 44 +#define SECONDARY_TDM_TX_2 45 +#define SECONDARY_TDM_RX_3 46 +#define SECONDARY_TDM_TX_3 47 +#define SECONDARY_TDM_RX_4 48 +#define SECONDARY_TDM_TX_4 49 +#define SECONDARY_TDM_RX_5 50 +#define SECONDARY_TDM_TX_5 51 +#define SECONDARY_TDM_RX_6 52 +#define SECONDARY_TDM_TX_6 53 +#define SECONDARY_TDM_RX_7 54 +#define SECONDARY_TDM_TX_7 55 +#define TERTIARY_TDM_RX_0 56 +#define TERTIARY_TDM_TX_0 57 +#define TERTIARY_TDM_RX_1 58 +#define TERTIARY_TDM_TX_1 59 +#define TERTIARY_TDM_RX_2 60 +#define TERTIARY_TDM_TX_2 61 +#define TERTIARY_TDM_RX_3 62 +#define TERTIARY_TDM_TX_3 63 +#define TERTIARY_TDM_RX_4 64 +#define TERTIARY_TDM_TX_4 65 +#define TERTIARY_TDM_RX_5 66 +#define TERTIARY_TDM_TX_5 67 +#define TERTIARY_TDM_RX_6 68 +#define TERTIARY_TDM_TX_6 69 +#define TERTIARY_TDM_RX_7 70 +#define TERTIARY_TDM_TX_7 71 +#define QUATERNARY_TDM_RX_0 72 +#define QUATERNARY_TDM_TX_0 73 +#define QUATERNARY_TDM_RX_1 74 +#define QUATERNARY_TDM_TX_1 75 +#define QUATERNARY_TDM_RX_2 76 +#define QUATERNARY_TDM_TX_2 77 +#define QUATERNARY_TDM_RX_3 78 +#define QUATERNARY_TDM_TX_3 79 +#define QUATERNARY_TDM_RX_4 80 +#define QUATERNARY_TDM_TX_4 81 +#define QUATERNARY_TDM_RX_5 82 +#define QUATERNARY_TDM_TX_5 83 +#define QUATERNARY_TDM_RX_6 84 +#define QUATERNARY_TDM_TX_6 85 +#define QUATERNARY_TDM_RX_7 86 +#define QUATERNARY_TDM_TX_7 87 +#define QUINARY_TDM_RX_0 88 +#define QUINARY_TDM_TX_0 89 +#define QUINARY_TDM_RX_1 90 +#define QUINARY_TDM_TX_1 91 +#define QUINARY_TDM_RX_2 92 +#define QUINARY_TDM_TX_2 93 +#define QUINARY_TDM_RX_3 94 +#define QUINARY_TDM_TX_3 95 +#define QUINARY_TDM_RX_4 96 +#define QUINARY_TDM_TX_4 97 +#define QUINARY_TDM_RX_5 98 +#define QUINARY_TDM_TX_5 99 +#define QUINARY_TDM_RX_6 100 +#define QUINARY_TDM_TX_6 101 +#define QUINARY_TDM_RX_7 102 +#define QUINARY_TDM_TX_7 103 +#define DISPLAY_PORT_RX 104 +#define WSA_CODEC_DMA_RX_0 105 +#define WSA_CODEC_DMA_TX_0 106 +#define WSA_CODEC_DMA_RX_1 107 +#define WSA_CODEC_DMA_TX_1 108 +#define WSA_CODEC_DMA_TX_2 109 +#define VA_CODEC_DMA_TX_0 110 +#define VA_CODEC_DMA_TX_1 111 +#define VA_CODEC_DMA_TX_2 112 +#define RX_CODEC_DMA_RX_0 113 +#define TX_CODEC_DMA_TX_0 114 +#define RX_CODEC_DMA_RX_1 115 +#define TX_CODEC_DMA_TX_1 116 +#define RX_CODEC_DMA_RX_2 117 +#define TX_CODEC_DMA_TX_2 118 +#define RX_CODEC_DMA_RX_3 119 +#define TX_CODEC_DMA_TX_3 120 +#define RX_CODEC_DMA_RX_4 121 +#define TX_CODEC_DMA_TX_4 122 +#define RX_CODEC_DMA_RX_5 123 +#define TX_CODEC_DMA_TX_5 124 +#define RX_CODEC_DMA_RX_6 125 +#define RX_CODEC_DMA_RX_7 126 +#define QUINARY_MI2S_RX 127 +#define QUINARY_MI2S_TX 128 + +#define LPASS_CLK_ID_PRI_MI2S_IBIT 1 +#define LPASS_CLK_ID_PRI_MI2S_EBIT 2 +#define LPASS_CLK_ID_SEC_MI2S_IBIT 3 +#define LPASS_CLK_ID_SEC_MI2S_EBIT 4 +#define LPASS_CLK_ID_TER_MI2S_IBIT 5 +#define LPASS_CLK_ID_TER_MI2S_EBIT 6 +#define LPASS_CLK_ID_QUAD_MI2S_IBIT 7 +#define LPASS_CLK_ID_QUAD_MI2S_EBIT 8 +#define LPASS_CLK_ID_SPEAKER_I2S_IBIT 9 +#define LPASS_CLK_ID_SPEAKER_I2S_EBIT 10 +#define LPASS_CLK_ID_SPEAKER_I2S_OSR 11 +#define LPASS_CLK_ID_QUI_MI2S_IBIT 12 +#define LPASS_CLK_ID_QUI_MI2S_EBIT 13 +#define LPASS_CLK_ID_SEN_MI2S_IBIT 14 +#define LPASS_CLK_ID_SEN_MI2S_EBIT 15 +#define LPASS_CLK_ID_INT0_MI2S_IBIT 16 +#define LPASS_CLK_ID_INT1_MI2S_IBIT 17 +#define LPASS_CLK_ID_INT2_MI2S_IBIT 18 +#define LPASS_CLK_ID_INT3_MI2S_IBIT 19 +#define LPASS_CLK_ID_INT4_MI2S_IBIT 20 +#define LPASS_CLK_ID_INT5_MI2S_IBIT 21 +#define LPASS_CLK_ID_INT6_MI2S_IBIT 22 +#define LPASS_CLK_ID_QUI_MI2S_OSR 23 +#define LPASS_CLK_ID_PRI_PCM_IBIT 24 +#define LPASS_CLK_ID_PRI_PCM_EBIT 25 +#define LPASS_CLK_ID_SEC_PCM_IBIT 26 +#define LPASS_CLK_ID_SEC_PCM_EBIT 27 +#define LPASS_CLK_ID_TER_PCM_IBIT 28 +#define LPASS_CLK_ID_TER_PCM_EBIT 29 +#define LPASS_CLK_ID_QUAD_PCM_IBIT 30 +#define LPASS_CLK_ID_QUAD_PCM_EBIT 31 +#define LPASS_CLK_ID_QUIN_PCM_IBIT 32 +#define LPASS_CLK_ID_QUIN_PCM_EBIT 33 +#define LPASS_CLK_ID_QUI_PCM_OSR 34 +#define LPASS_CLK_ID_PRI_TDM_IBIT 35 +#define LPASS_CLK_ID_PRI_TDM_EBIT 36 +#define LPASS_CLK_ID_SEC_TDM_IBIT 37 +#define LPASS_CLK_ID_SEC_TDM_EBIT 38 +#define LPASS_CLK_ID_TER_TDM_IBIT 39 +#define LPASS_CLK_ID_TER_TDM_EBIT 40 +#define LPASS_CLK_ID_QUAD_TDM_IBIT 41 +#define LPASS_CLK_ID_QUAD_TDM_EBIT 42 +#define LPASS_CLK_ID_QUIN_TDM_IBIT 43 +#define LPASS_CLK_ID_QUIN_TDM_EBIT 44 +#define LPASS_CLK_ID_QUIN_TDM_OSR 45 +#define LPASS_CLK_ID_MCLK_1 46 +#define LPASS_CLK_ID_MCLK_2 47 +#define LPASS_CLK_ID_MCLK_3 48 +#define LPASS_CLK_ID_MCLK_4 49 +#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE 50 +#define LPASS_CLK_ID_INT_MCLK_0 51 +#define LPASS_CLK_ID_INT_MCLK_1 52 +#define LPASS_CLK_ID_MCLK_5 53 +#define LPASS_CLK_ID_WSA_CORE_MCLK 54 +#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK 55 +#define LPASS_CLK_ID_VA_CORE_MCLK 56 +#define LPASS_CLK_ID_TX_CORE_MCLK 57 +#define LPASS_CLK_ID_TX_CORE_NPL_MCLK 58 +#define LPASS_CLK_ID_RX_CORE_MCLK 59 +#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60 +#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61 + +#define LPASS_HW_AVTIMER_VOTE 101 +#define LPASS_HW_MACRO_VOTE 102 +#define LPASS_HW_DCODEC_VOTE 103 + +#define Q6AFE_MAX_CLK_ID 104 + +#define LPASS_CLK_ATTRIBUTE_INVALID 0x0 +#define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND 0x2 +#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR 0x3 + +#endif /* __DT_BINDINGS_Q6_AUDIO_PORTS_H__ */ From patchwork Fri Sep 3 11:20:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524248 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=NthLu70j; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1FkC1j7pz9ssD for ; Fri, 3 Sep 2021 21:21:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349288AbhICLWx (ORCPT ); Fri, 3 Sep 2021 07:22:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349219AbhICLWr (ORCPT ); Fri, 3 Sep 2021 07:22:47 -0400 Received: from mail-wr1-x434.google.com (mail-wr1-x434.google.com [IPv6:2a00:1450:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 932E5C061575 for ; Fri, 3 Sep 2021 04:21:47 -0700 (PDT) Received: by mail-wr1-x434.google.com with SMTP id q11so7719754wrr.9 for ; Fri, 03 Sep 2021 04:21:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZwS0pTLfaYvtmnmGSPY2CWYSjvjRmgOXbJ+a8m+7l0Q=; b=NthLu70jVSNa9pEkEcYM0mSh3MxkSlrJqC6QtjhFW7W7pEJdifqWfKPqN/QcZfGydO T1IaFTjhOMACUbcQtTUA0WJ6VbDEZCOELmyogwljE6C5NAaj0fKytVnKr9iDU2dMqkx9 9r4GrNIp8w+XFYPcibSkw99GMh+/RhMVAh8JIRVqRfZknUUN1QifColyynJlKqPbMl4a VsFo7uRITU0lDZldkCEQYgMMcKEMMbtb3MO8WcrLDmElwAr2o7Es9b86C500fHH27g9h pI73nF1+F6alXZvQJqzHdyjlHh3go3bpGpQT4sg3lgqF/0RZHH32Os96kNpMqDIRg/j3 wxzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZwS0pTLfaYvtmnmGSPY2CWYSjvjRmgOXbJ+a8m+7l0Q=; b=PGPWjlcWr7anII51cwfo0B00ZGbItz9FqxUaVjJEiVP9mAhsKIY7cx8pkHk14Q55EG iSAiLSq92YLKZV+Nw2tQNjQa0M7QmKap4UXtGwP2rMiaFzT1YQ2rSpTDKmMNPQq+RYvu 7pnmhkubWbexZbBpPXbS4shzniDw+EPrWJDuImPIJxdqo76AsJ8vvSN0kE3cRq11kvBS ptgesXubMgtqXN4P+cmHKRm6xMaBEveHFretAjRC2EDN5umWaMWuBpVZ77I+WPzXY71Q /hrBFRWSOI/afEL2wnZBolJA6+pWqobGHreA/4H6htRFVlGWfWgs4I3JaT6V1xcQxUGB nv5w== X-Gm-Message-State: AOAM532T2zp8eLOI++SoPF6jgsNUGSN76dlxXAWKydcBHn4BK6ECiJ0y ImmF85QkmMyKKVnGHZqqWl6UMQ== X-Google-Smtp-Source: ABdhPJyRIG1jDC1HovGExZgKxlc97C10bjOuLrdMrf/bDLQQrwOzv5el44PzsJqyiEzbAknPQa4fDQ== X-Received: by 2002:adf:fb8d:: with SMTP id a13mr3569765wrr.164.1630668106206; Fri, 03 Sep 2021 04:21:46 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:45 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 11/21] ASoC: dt-bindings: q6dsp: add q6apm-lpass-dai compatible Date: Fri, 3 Sep 2021 12:20:22 +0100 Message-Id: <20210903112032.25834-12-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org on AudioReach audio Framework access to LPASS ports is via Q6APM(Audio Process Manager) service, so add a dedicated compatible string for this. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../sound/qcom,q6dsp-lpass-ports.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml index e6148c17419b..92a641dfe04f 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-ports.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,q6afe-dais + - qcom,q6apm-lpass-dais reg: maxItems: 1 @@ -169,6 +170,29 @@ examples: #size-cells = <0>; #sound-dai-cells = <1>; + dai@22 { + reg = ; + qcom,sd-lines = <0 1 2 3>; + }; + }; + }; + }; + - | + #include + gpr { + #address-cells = <1>; + #size-cells = <0>; + gpr-service@1 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6apmdai@1 { + compatible = "qcom,q6apm-lpass-dais"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + dai@22 { reg = ; qcom,sd-lines = <0 1 2 3>; From patchwork Fri Sep 3 11:20:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524246 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=m3dU1nsk; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1FkB2SRgz9sW4 for ; Fri, 3 Sep 2021 21:21:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349276AbhICLWx (ORCPT ); Fri, 3 Sep 2021 07:22:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349241AbhICLWs (ORCPT ); Fri, 3 Sep 2021 07:22:48 -0400 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1F7AC061757 for ; Fri, 3 Sep 2021 04:21:48 -0700 (PDT) Received: by mail-wr1-x42a.google.com with SMTP id m9so7756094wrb.1 for ; Fri, 03 Sep 2021 04:21:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XrcdWigOrJBOqNH3/v+b+R+GIipVI1XmPMk0yejMbMo=; b=m3dU1nskU148xorso3M3e8tJyMoaA5cHdIzy7AL+czkLGPv7oLPA5e7oVDBKgfySp6 NzaK41cabEW4S3hpjdQHiOyuVtyfaP4+2EM+JFWxbRAn8VFJEiKI4bDMgFkH6Q3i9rCX 0de9CDTHSVkVTXIVZnpdIibdLfUKSjFPnCPCc4LoWaQvs0hDXnBTUF0xA5tSprctigvW Sj1iRKkQRrutNlSRfRgic/lZR379VY9Eka8nmn2z1EQzlDKQZFErCpHOgOw5+4txL4yR aUw1vzmFa8QB0WAjRrKFD2fAqPO5jqIrMLUsl0tPuf0GxybFXu4exEErL0OXa8QKEM3b T7lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XrcdWigOrJBOqNH3/v+b+R+GIipVI1XmPMk0yejMbMo=; b=UTULpEXa23axNVrixEKhMpp+EV3Ktsu0Aw9jFyaQCR80k6aQC7OKyQSx4WIMp4xWSA NDbSn3VsfISi4zyfCRShzZ/sBIjl1Cr5ne5sj6KIjOOrgoOzRRIg2SazTe/C782xU+LW Plrbq3EgrLjZpNiY2J0XMo+wfBUQgiFM+U36KuJtHpKZdT6tvB5E5UT3+UE57brcfhFK Fa1NsJpbnNxq+A/WOZRPDWq6msPP+aVmnS7Yo2j2qqrNnCiPlcy8RujbFOQTTn1c44ZY ibJHBsVWiBSpmFfx1Gy9FJyAUb87l8W4Di2uCJQQcFPy485JVGDoFVpl6/LXqQ56YIpv F2UQ== X-Gm-Message-State: AOAM533waBTbft9ehlTblMBzC9C1BZrqWzQR33IG9nobE3VMLQfDsaoQ Ku8wGi4B4oy6tehHMphUpFCVRw== X-Google-Smtp-Source: ABdhPJx/laJ0dPo3VhAp35pton8lIaiXEa8k4R19JM9JV80XiAkhPelcOx2o0e0ANCWxX77k4D+xsA== X-Received: by 2002:a5d:56c9:: with SMTP id m9mr2888686wrw.134.1630668107423; Fri, 03 Sep 2021 04:21:47 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:46 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 12/21] ASoC: dt-bindings: lpass-clocks: add q6prm clocks compatible Date: Fri, 3 Sep 2021 12:20:23 +0100 Message-Id: <20210903112032.25834-13-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On AudioReach audio Framework access to LPASS ports is via Q6PRM (Proxy Resource Manager) service, so add a dedicated lpass-clock compatible string for this. Signed-off-by: Srinivas Kandagatla Reviewed-by: Rob Herring --- .../sound/qcom,q6dsp-lpass-clocks.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml index 589c3f1e2008..9f3de2307d1c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,q6dsp-lpass-clocks.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,q6afe-clocks + - qcom,q6prm-lpass-clocks reg: maxItems: 1 @@ -54,3 +55,20 @@ examples: }; }; }; + + - | + #include + gpr { + #address-cells = <1>; + #size-cells = <0>; + gpr-service@2 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + q6prmcc@2 { + compatible = "qcom,q6prm-lpass-clocks"; + reg = <2>; + #clock-cells = <2>; + }; + }; + }; From patchwork Fri Sep 3 11:20:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 1524247 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=nnDuaGdz; dkim-atps=neutral Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4H1FkB4nZvz9sjJ for ; Fri, 3 Sep 2021 21:21:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349241AbhICLWx (ORCPT ); Fri, 3 Sep 2021 07:22:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349253AbhICLWt (ORCPT ); Fri, 3 Sep 2021 07:22:49 -0400 Received: from mail-wr1-x435.google.com (mail-wr1-x435.google.com [IPv6:2a00:1450:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 067D8C061760 for ; Fri, 3 Sep 2021 04:21:50 -0700 (PDT) Received: by mail-wr1-x435.google.com with SMTP id z4so7727322wrr.6 for ; Fri, 03 Sep 2021 04:21:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RwkBekoVHbR6mINfcBzFLlTHGm7nkcct6qC3KOCM4UE=; b=nnDuaGdzIo6q/ktDdSQ5oNq6FAVQxDKNm3vpvhidfJ+W0+arnzzt8T0i4adPPle3Na /X2embjE5Zrfp2eYUGZKthxtgIFJfdh6JECxWbeyOLoyF1HCdyggBvrKPL9qM+gF8Ks+ bGKG/dV4gKwN8ghzywLXFa2v6ZtgdDKstEDQj06MyO2/L0Dg0rwNGSWRo7B40PIBTlmH 25fyCDiQ4/0UwMPTwH5WSDIZVo4UrY69fHfEXkcqe6+D9N4Kj4zO9UQti/sgvpm437BN 2n6mExwvWjbXzLLG1kKfp82UmGZpfvSATTOjL6TKLWpVyRg40QKuu5wSq9j1zJX6ybi7 G6/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RwkBekoVHbR6mINfcBzFLlTHGm7nkcct6qC3KOCM4UE=; b=LjTg++EsYuxb9DlNfKbY2OTPnl7QQ2mwxRhSn5fmB7Gr3S+qGuAMOSZQPKo8OsIvRp U3+FxssNPSfHR5XjU+jG85l4BDPUs0lJaDsEXkx+0c7RYPA77w/SvndOSugIouoehIF+ NypRfNheeiOlrvJwzh1Jr0IN6JOPgbP1+iMx6tWU0XM/elr53Xqv/gjmxqAxWHHr4Oos u4DXMbwLPmz54aoeR9kr9laIXnTOfe17yq9+Yx3mUmb/wxFfTsCeXLMVEWg/qRhW0we6 lDH5OVungzA/3hjfTseUk0oXnSBw7N96Jbg00Ex55Onq91T3tLiS7DDe+AlGCw3YdiFm hygQ== X-Gm-Message-State: AOAM530ey6Jei6UBokUHzWBSW3gzmFOItvSZYR4FMu1fcPf7jmu+gYzB L89oPvOqE+ObGexLZMzB1SsPXg== X-Google-Smtp-Source: ABdhPJzwBsuoA054xPFPRaAoZeV82ZrjBVhXF2UfSP+zszzIu2WwjBzQ1sQL90BX/skDPztfsvcUKw== X-Received: by 2002:adf:80e5:: with SMTP id 92mr3506130wrl.300.1630668108623; Fri, 03 Sep 2021 04:21:48 -0700 (PDT) Received: from srini-hackbox.lan (cpc86377-aztw32-2-0-cust226.18-1.cable.virginm.net. [92.233.226.227]) by smtp.gmail.com with ESMTPSA id f20sm3881877wmb.32.2021.09.03.04.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Sep 2021 04:21:48 -0700 (PDT) From: Srinivas Kandagatla To: bjorn.andersson@linaro.org, broonie@kernel.org, robh@kernel.org Cc: plai@codeaurora.org, tiwai@suse.de, devicetree@vger.kernel.org, perex@perex.cz, alsa-devel@alsa-project.org, lgirdwood@gmail.com, bgoswami@codeaurora.org, Srinivas Kandagatla Subject: [PATCH v5 13/21] ASoC: dt-bindings: add q6apm digital audio stream bindings Date: Fri, 3 Sep 2021 12:20:24 +0100 Message-Id: <20210903112032.25834-14-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> References: <20210903112032.25834-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On AudioReach audio Framework, Audio Streams (PCM/Compressed) are managed by Q6APM(Audio Process Manager) service. This patch adds bindings for this DAIs exposed by the DSP. Signed-off-by: Srinivas Kandagatla --- .../bindings/sound/qcom,q6apm-dai.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml diff --git a/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml new file mode 100644 index 000000000000..75431d1c0b2a --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,q6apm-dai.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/sound/qcom,q6apm-dai.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Audio Process Manager Digital Audio Interfaces binding + +maintainers: + - Srinivas Kandagatla + +description: | + This binding describes the Qualcomm APM DAIs in DSP + +properties: + compatible: + const: qcom,q6apm-dais + + reg: + maxItems: 1 + + iommus: + maxItems: 1 + +required: + - compatible + - iommus + - reg + +additionalProperties: false + +examples: + - | + gpr { + #address-cells = <1>; + #size-cells = <0>; + gprservice@1 { + compatible = "qcom,q6apm"; + reg = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + apm@1 { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + reg = <1>; + }; + }; + };