From patchwork Fri Aug 20 17:07:58 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 1519118 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=fsR9G4fw; dkim-atps=neutral Received: from sourceware.org (ip-8-43-85-97.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Grp4g3NMDz9sWq for ; Sat, 21 Aug 2021 03:08:34 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B1E9F39C0029 for ; Fri, 20 Aug 2021 17:08:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B1E9F39C0029 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1629479311; bh=5AQWotUKf5OlJEVHG0VPuLkMvITqN8NtNxJ4Fyteg+A=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=fsR9G4fwsH8yznZDeZPE9KdXPHEl9Prbpynv4adhCQf/NdLTM7Fzt9sx+ufZLlJCa 7v0EpOaileFJQzS4yw5QQ/1gFSFj1qAEWcxTZ94Bk77fFgAiWYPssFHLfoSbdeBXyv B2qDZxswkC2gkPWUQwrZd1qwB5D0oeH8MeOsWOEM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mengyan1223.wang (mengyan1223.wang [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id F245A3857C67 for ; Fri, 20 Aug 2021 17:08:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F245A3857C67 Received: from localhost.localdomain (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@mengyan1223.wang) by mengyan1223.wang (Postfix) with ESMTPSA id 802DD65ACF for ; Fri, 20 Aug 2021 13:08:00 -0400 (EDT) Message-ID: <82b0b91d0bb769748b0ee4f830c294fad33ded7f.camel@mengyan1223.wang> Subject: [PATCH] mips: msa: truncate immediate shift amount [PR101922] To: gcc-patches@gcc.gnu.org Date: Sat, 21 Aug 2021 01:07:58 +0800 User-Agent: Evolution 3.40.4 MIME-Version: 1.0 X-Spam-Status: No, score=-3037.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" When -mloongson-mmi is enabled, SHIFT_COUNT_TRUNCATED is turned off. This causes untruncated immediate shift amount outputed into the asm, and the GNU assembler refuses to assemble it. Truncate immediate shift amount when outputing the asm instruction to make GAS happy again. gcc/ PR target/101922 * config/mips/mips-protos.h (mips_msa_output_shift_immediate): Declare. * config/mips/mips.c (mips_msa_output_shift_immediate): New function. * config/mips/mips-msa.md (vashl3, vashr3, vlshr3): Call it. gcc/testsuite/ PR target/101922 * gcc.target/mips/pr101922.c: New test. --- gcc/config/mips/mips-msa.md | 27 ++++++++++++++++-------- gcc/config/mips/mips-protos.h | 1 + gcc/config/mips/mips.c | 21 ++++++++++++++++++ gcc/testsuite/gcc.target/mips/pr101922.c | 19 +++++++++++++++++ 4 files changed, 59 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/pr101922.c diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 3a67f25be56..d3b27d132ad 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -870,9 +870,12 @@ (define_insn "vlshr3" (match_operand:IMSA 1 "register_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] "ISA_HAS_MSA" - "@ - srl.\t%w0,%w1,%w2 - srli.\t%w0,%w1,%E2" +{ + if (which_alternative == 0) + return "srl.\t%w0,%w1,%w2"; + + return mips_msa_output_shift_immediate("srli.\t%w0,%w1,%E2", operands); +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) @@ -882,9 +885,12 @@ (define_insn "vashr3" (match_operand:IMSA 1 "register_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] "ISA_HAS_MSA" - "@ - sra.\t%w0,%w1,%w2 - srai.\t%w0,%w1,%E2" +{ + if (which_alternative == 0) + return "sra.\t%w0,%w1,%w2"; + + return mips_msa_output_shift_immediate("srai.\t%w0,%w1,%E2", operands); +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) @@ -894,9 +900,12 @@ (define_insn "vashl3" (match_operand:IMSA 1 "register_operand" "f,f") (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))] "ISA_HAS_MSA" - "@ - sll.\t%w0,%w1,%w2 - slli.\t%w0,%w1,%E2" +{ + if (which_alternative == 0) + return "sll.\t%w0,%w1,%w2"; + + return mips_msa_output_shift_immediate("slli.\t%w0,%w1,%E2", operands); +} [(set_attr "type" "simd_shift") (set_attr "mode" "")]) diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h index a5e4151b9e6..8d97eb36125 100644 --- a/gcc/config/mips/mips-protos.h +++ b/gcc/config/mips/mips-protos.h @@ -317,6 +317,7 @@ extern const char *mips_output_sync_loop (rtx_insn *, rtx *); extern unsigned int mips_sync_loop_insns (rtx_insn *, rtx *); extern const char *mips_output_division (const char *, rtx *); extern const char *mips_msa_output_division (const char *, rtx *); +extern const char *mips_msa_output_shift_immediate (const char *, rtx *); extern const char *mips_output_probe_stack_range (rtx, rtx); extern bool mips_hard_regno_rename_ok (unsigned int, unsigned int); extern bool mips_linked_madd_p (rtx_insn *, rtx_insn *); diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 89d1be6cea6..3d5be369b1c 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -14495,6 +14495,27 @@ mips_msa_output_division (const char *division, rtx *operands) } return s; } + +/* Return the assembly code for MSA immediate shift instructions, + which has the operands given by OPERANDS. Truncate the shift amount + to make GAS happy. */ + +const char * +mips_msa_output_shift_immediate (const char *shift, rtx *operands) +{ + rtx amount = operands[2]; + machine_mode mode = amount->mode; + + unsigned val = UINTVAL (CONST_VECTOR_ELT (amount, 0)); + val &= GET_MODE_UNIT_BITSIZE (mode) - 1; + if (!val) + return ""; + + rtx c = gen_int_mode (val, GET_MODE_INNER (mode)); + operands[2] = gen_const_vec_duplicate (mode, c); + + return shift; +} /* Return true if destination of IN_INSN is used as add source in OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example: diff --git a/gcc/testsuite/gcc.target/mips/pr101922.c b/gcc/testsuite/gcc.target/mips/pr101922.c new file mode 100644 index 00000000000..00a6e495ba2 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr101922.c @@ -0,0 +1,19 @@ +/* PR target/101922 + This was triggering an assembler error with -O3 -mmsa -mloongson-mmi. */ + +/* { dg-do assemble } */ +/* { dg-options "-mmsa -mloongson-mmi" } */ + +typedef __INT8_TYPE__ i8; +typedef __INT32_TYPE__ i32; + +i8 d[16]; + +i32 f(i32 x) { + int i; + for (i = 0; i < 16; i++) { + i32 t = (i32) d[i] >> 31; + x &= t; + } + return x; +}