From patchwork Sat Jul 17 12:11:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1506453 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=YREaVJek; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GRn6g6rm6z9t4b for ; Sat, 17 Jul 2021 22:12:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234056AbhGQMOc (ORCPT ); Sat, 17 Jul 2021 08:14:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47274 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233700AbhGQMOZ (ORCPT ); Sat, 17 Jul 2021 08:14:25 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10055C061762; Sat, 17 Jul 2021 05:11:28 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id y42so20626876lfa.3; Sat, 17 Jul 2021 05:11:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3PQPHGOW6QQhg7v1jHH53jvk1y+aGZu+fHQa7m9Qum4=; b=YREaVJekFAPhdCMaSbys01Jn/bOl54nB2yn83WExr1QnB6Db0r1G/jVSH11B4XmT/c cSZhDtmJnTWJfWhzqovZi/waxZVM2n5ndnThfeybqngDwqncOz8NjJkXq9wvOSXA13XE 1kvlCdx1QX6cXxhRDAmeirvsY86gkYEhX9RKuG8wdvzJLZf0PuJno925mVt21fJ42Hl+ b3Ynht5Tu2oj+PqFSJYhqUP43mZ1dAUAfw0PM9DnTyN4DUk7tdLX3kUzv78GYsMJh2BX g1UZNAGFMUWahi5MCkpUZWJyJlQVhf0oCmTGE1U+LxC4iw5wnXZG7hFOCJ1HW5tG16Hk bkWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3PQPHGOW6QQhg7v1jHH53jvk1y+aGZu+fHQa7m9Qum4=; b=ZfcuhV388J10Bkn4E2IXwhC0pFODMVA1zvc0tqVm6edJa30+GpAB6E/07i8b7+xPYG /VO8tHjwbu9dMa9g3pwiAvDGXkG7E2UUHRsKkZDg5X/eYxpeFm4Mz/QruKhHCWdifJdv CkUbhvIz0PwFxbjJdpMHbzSFozqXp3978DCh+laitXLfSZM8vszuANT0u59wN3dfbHNu 1kSR2xiA/beAIQogMn3DTworVxrG/ctjgUNyKtRmnshdmdD+s8WXuEF1yxyzzcdiQ+OI IALEUMROMuoApxsMlROS/1z3chylSbs5j3r/3LJ0EZvNOdtNoYdyiEUC4AUgxD5VD9a1 J6CA== X-Gm-Message-State: AOAM530aDNFzOh4dcshOXBMRzVscb4lZXUP9wcPC1pd6AgIRY/FT6/Yd Vvefxeb8ned2ulO3M9UHMyc= X-Google-Smtp-Source: ABdhPJy2XvtfSCjE4dYkYBQ8fjaD9acy15eBZc5X3VDjRHZ/nHD7Yqrt9xSpAbaPtpkfM+szP7ruEA== X-Received: by 2002:a19:7617:: with SMTP id c23mr11699557lff.149.1626523886254; Sat, 17 Jul 2021 05:11:26 -0700 (PDT) Received: from localhost.localdomain (46-138-17-250.dynamic.spd-mgts.ru. [46.138.17.250]) by smtp.gmail.com with ESMTPSA id m16sm852597lfq.23.2021.07.17.05.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 05:11:25 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Rob Herring , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 01/12] dt-bindings: phy: tegra20-usb-phy: Convert to schema Date: Sat, 17 Jul 2021 15:11:01 +0300 Message-Id: <20210717121112.3248-2-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717121112.3248-1-digetx@gmail.com> References: <20210717121112.3248-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert NVIDIA Tegra20 USB PHY binding to schema. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ---- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 357 ++++++++++++++++++ 2 files changed, 357 insertions(+), 74 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt deleted file mode 100644 index 1aa6f2674af5..000000000000 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt +++ /dev/null @@ -1,74 +0,0 @@ -Tegra SOC USB PHY - -The device node for Tegra SOC USB PHY: - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". - For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain - "nvidia,-usb-phy" plus at least one of the above, where is - tegra114, tegra124, tegra132, or tegra210. - - reg : Defines the following set of registers, in the order listed: - - The PHY's own register set. - Always present. - - The register set of the PHY containing the UTMI pad control registers. - Present if-and-only-if phy_type == utmi. - - phy_type : Should be one of "utmi", "ulpi" or "hsic". - - clocks : Defines the clocks listed in the clock-names property. - - clock-names : The following clock names must be present: - - reg: The clock needed to access the PHY's own registers. This is the - associated EHCI controller's clock. Always present. - - pll_u: PLL_U. Always present. - - timer: The timeout clock (clk_m). Present if phy_type == utmi. - - utmi-pads: The clock needed to access the UTMI pad control registers. - Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 - with pad group aka "nvidia,pins" cdev2 and pin mux option config aka - "nvidia,function" pllp_out4). - Present if phy_type == ulpi, and ULPI link mode is in use. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb: The PHY's own reset signal. - - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control - registers. Required even if phy_type == ulpi. - -Required properties for phy_type == ulpi: - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. - -Required PHY timing params for utmi phy, for all chips: - - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before - start of sync launches RxActive - - nvidia,elastic-limit : Variable FIFO Depth of elastic input store - - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait - before declare IDLE. - - nvidia,term-range-adj : Range adjusment on terminations - - Either one of the following for HS driver output control: - - nvidia,xcvr-setup : integer, uses the provided value. - - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read - from the on-chip fuses - If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. - - nvidia,xcvr-lsfslew : LS falling slew rate control. - - nvidia,xcvr-lsrslew : LS rising slew rate control. - -Required PHY timing params for utmi phy, only on Tegra30 and above: - - nvidia,xcvr-hsslew : HS slew rate control. - - nvidia,hssquelch-level : HS squelch detector level. - - nvidia,hsdiscon-level : HS disconnect detector level. - -Optional properties: - - nvidia,has-legacy-mode : boolean indicates whether this controller can - operate in legacy mode (as APX 2500 / 2600). In legacy mode some - registers are accessed through the APB_MISC base address instead of - the USB controller. - - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power - optimizations for the devices that are always connected. e.g. modem. - - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be - "host", "peripheral", or "otg". Defaults to "host" if not defined. - host means this is a host controller - peripheral means it is device controller - otg means it can operate as either ("on the go") - - nvidia,has-utmi-pad-registers : boolean indicates whether this controller - contains the UTMI pad control registers common to all USB controllers. - -VBUS control (required for dr_mode == otg, optional for dr_mode == host): - - vbus-supply: regulator for VBUS diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml new file mode 100644 index 000000000000..593187234e6a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml @@ -0,0 +1,357 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra USB PHY + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra124-usb-phy + - nvidia,tegra114-usb-phy + - enum: + - nvidia,tegra30-usb-phy + - items: + - enum: + - nvidia,tegra30-usb-phy + - nvidia,tegra20-usb-phy + + reg: + minItems: 1 + maxItems: 2 + description: | + PHY0 and PHY2 share power and ground, PHY0 contains shared registers. + PHY0 and PHY2 must specify two register sets, where the first set is + PHY own registers and the second set is the PHY0 registers. + + clocks: + anyOf: + - items: + - description: Registers clock + - description: Main PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: ULPI PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI pads control registers clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI timeout clock + - description: UTMI pads control registers clock + + clock-names: + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + - items: + - const: reg + - const: pll_u + - const: utmi-pads + + - items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + resets: + oneOf: + - maxItems: 1 + description: PHY reset + + - items: + - description: PHY reset + - description: UTMI pads reset + + reset-names: + oneOf: + - const: usb + + - items: + - const: usb + - const: utmi-pads + + "#phy-cells": + const: 0 + + phy_type: + $ref: /schemas/types.yaml#/definitions/string + enum: [utmi, ulpi, hsic] + + dr_mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, peripheral, otg] + default: host + + vbus-supply: + description: Regulator controlling USB VBUS. + + nvidia,has-legacy-mode: + description: | + Indicates whether this controller can operate in legacy mode + (as APX 2500 / 2600). In legacy mode some registers are accessed + through the APB_MISC base address instead of the USB controller. + type: boolean + + nvidia,is-wired: + description: | + Indicates whether we can do certain kind of power optimizations for + the devices that are always connected. e.g. modem. + type: boolean + + nvidia,has-utmi-pad-registers: + description: | + Indicates whether this controller contains the UTMI pad control + registers common to all USB controllers. + type: boolean + + nvidia,hssync-start-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles to wait before start of sync launches + RxActive. + + nvidia,elastic-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Variable FIFO Depth of elastic input store. + + nvidia,idle-wait-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles of idle to wait before declare IDLE. + + nvidia,term-range-adj: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Range adjustment on terminations. + + nvidia,xcvr-setup: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 127 + description: Input of XCVR cell, HS driver output control. + + nvidia,xcvr-setup-use-fuses: + description: Indicates that the value is read from the on-chip fuses. + type: boolean + + nvidia,xcvr-lsfslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS falling slew rate control. + + nvidia,xcvr-lsrslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS rising slew rate control. + + nvidia,xcvr-hsslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 511 + description: HS slew rate control. + + nvidia,hssquelch-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: HS squelch detector level. + + nvidia,hsdiscon-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: HS disconnect detector level. + + nvidia,phy-reset-gpio: + maxItems: 1 + description: GPIO used to reset the PHY. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + - phy_type + +additionalProperties: false + +allOf: + - if: + properties: + phy_type: + const: utmi + + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + + required: + - nvidia,hssync-start-delay + - nvidia,elastic-limit + - nvidia,idle-wait-delay + - nvidia,term-range-adj + - nvidia,xcvr-lsfslew + - nvidia,xcvr-lsrslew + + anyOf: + - required: ["nvidia,xcvr-setup"] + - required: ["nvidia,xcvr-setup-use-fuses"] + + if: + properties: + compatible: + contains: + const: nvidia,tegra30-usb-phy + + then: + properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: reg + - const: pll_u + - const: utmi-pads + + required: + - nvidia,xcvr-hsslew + - nvidia,hssquelch-level + - nvidia,hsdiscon-level + + else: + properties: + clocks: + maxItems: 4 + + clock-names: + items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + - if: + properties: + phy_type: + const: ulpi + + then: + properties: + reg: + minItems: 1 + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + +examples: + - | + #include + + usb-phy@7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + }; + + - | + #include + + usb-phy@c5004000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004000 0x4000>; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA20_CLK_USB2>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + }; From patchwork Sat Jul 17 12:11:02 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1506440 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=rxl/vB5M; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GRn5k0Yrlz9sW8 for ; Sat, 17 Jul 2021 22:11:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233893AbhGQMOb (ORCPT ); Sat, 17 Jul 2021 08:14:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233715AbhGQMO0 (ORCPT ); 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[46.138.17.250]) by smtp.gmail.com with ESMTPSA id m16sm852597lfq.23.2021.07.17.05.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 05:11:26 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Rob Herring , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 02/12] dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG mode Date: Sat, 17 Jul 2021 15:11:02 +0300 Message-Id: <20210717121112.3248-3-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717121112.3248-1-digetx@gmail.com> References: <20210717121112.3248-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to support OTG mode we need these new properties: - interrupt - nvidia,pmc Add the new properties to the binding. Signed-off-by: Dmitry Osipenko --- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml index 593187234e6a..dfde0eaf66e1 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml @@ -77,6 +77,9 @@ properties: - const: timer - const: utmi-pads + interrupts: + maxItems: 1 + resets: oneOf: - maxItems: 1 @@ -199,6 +202,15 @@ properties: maxItems: 1 description: GPIO used to reset the PHY. + nvidia,pmc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to Power Management controller. + - description: USB controller ID. + description: + Phandle to Power Management controller. + required: - compatible - reg @@ -320,6 +332,7 @@ examples: compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = <0 97 4>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -338,6 +351,7 @@ examples: nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc 2>; }; - | @@ -346,6 +360,7 @@ examples: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5004000 0x4000>; + interrupts = <0 21 4>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -354,4 +369,5 @@ examples: resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc 1>; }; From patchwork Sat Jul 17 12:11:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1506446 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=UHvrWhhw; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GRn610FTHz9sWl for ; Sat, 17 Jul 2021 22:11:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234466AbhGQMOj (ORCPT ); Sat, 17 Jul 2021 08:14:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233850AbhGQMOb (ORCPT ); Sat, 17 Jul 2021 08:14:31 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F401C061767; Sat, 17 Jul 2021 05:11:32 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id i5so20629662lfe.2; Sat, 17 Jul 2021 05:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5Vgfkn6aojezGyNshrp4rdUuCsXyIjMI3yAFc0juggw=; b=UHvrWhhwpcUuQOIPpK22jHEi7JX3plC7DsT9NNkpvpszcO4q4AYRGk77Y943U+ra2u nXyG0zzmOLYkxYMSYcuQhMJQ5ZtjNuc2b1DACwbJyZHqIf5532jCD2N2UMNDmgPCndgO xPXN0bC8uqJ31A7Kvbh8YyESVQ7aH2IBOZLtD/FHWMmHrg7EtSno864xiU1eSukh5BJk EmUAHhTQn6DTW+kynY7nXz0YXDCrmUf7xDazYfDeOFzqHKKvfz83e8obyRWNmwQxzh9n pvd5Oo1pksbXBOGGq3eDeZgVaMYdz5bNd2E5HGqlmDLTFxQRed9F+EWG0mhoUWLTruxb ZlOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Vgfkn6aojezGyNshrp4rdUuCsXyIjMI3yAFc0juggw=; b=bF2yEVFe6oGAPJMO0jHsKqYXEVjzf5XDR3P6rO5mOLr6ccV1I3x5GXyX3V0yEGIZQ2 Teucu3edhR/7OJljjEAL+3XIUfgagiYh3avc2Aqn2AhsFdtAdMWV81PwrIWbaUMkL8lq jvyrizqXWsn0RWdhuPzimwjReVGvV9CoYKth4mtzr9gM7LHee5BqnV5zs0JY+TXkrPUV DPWRkQCUvgvycxc5U5lukJRLpHP5y5DSAN02teCYW4PPYMuyjSozutcEZvbHnM0i62WQ S314sIxGnJ1QbnfxFHsiPbzbagVLKu5vFFn9TIAGY+iqNLtLVPNWUs9j0SsvBAaijM9m 793Q== X-Gm-Message-State: AOAM532N/NEzQZeGfRFvsY41/lRw4U0VWkKnbK7y3vBCS/pk6JYMYgA8 /y/1X0obuxNeSz9uz8PgBpE= X-Google-Smtp-Source: ABdhPJyO8g0219TmdUe8/OktK+NJx29ZTQWj7jvkILuLCrT8d3J2SKnl+79bNkLx+V8PXGMZhphuvg== X-Received: by 2002:a19:8588:: with SMTP id h130mr11315847lfd.501.1626523890842; Sat, 17 Jul 2021 05:11:30 -0700 (PDT) Received: from localhost.localdomain (46-138-17-250.dynamic.spd-mgts.ru. [46.138.17.250]) by smtp.gmail.com with ESMTPSA id m16sm852597lfq.23.2021.07.17.05.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Jul 2021 05:11:30 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Rob Herring , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v4 06/12] dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator Date: Sat, 17 Jul 2021 15:11:06 +0300 Message-Id: <20210717121112.3248-7-digetx@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210717121112.3248-1-digetx@gmail.com> References: <20210717121112.3248-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SMB347 can supply power to USB VBUS, which is required by OTG-cable devices that want to switch USB port into the host mode. Add USB VBUS regulator properties. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko --- .../power/supply/summit,smb347-charger.yaml | 30 +++++++++++++++++++ .../dt-bindings/power/summit,smb347-charger.h | 4 +++ 2 files changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml index 983fc215c1e5..20862cdfc116 100644 --- a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml @@ -73,6 +73,26 @@ properties: - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation + summit,inok-polarity: + description: | + Polarity of INOK signal indicating presence of external power supply. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_SYSOK_INOK_ACTIVE_LOW + - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH + + usb-vbus: + $ref: "../../regulator/regulator.yaml#" + type: object + + properties: + summit,needs-inok-toggle: + type: boolean + description: INOK signal is fixed and polarity needs to be toggled + in order to enable/disable output mode. + + unevaluatedProperties: false + allOf: - if: properties: @@ -134,6 +154,7 @@ examples: reg = <0x7f>; summit,enable-charge-control = ; + summit,inok-polarity = ; summit,chip-temperature-threshold-celsius = <110>; summit,mains-current-limit-microamp = <2000000>; summit,usb-current-limit-microamp = <500000>; @@ -141,6 +162,15 @@ examples: summit,enable-mains-charging; monitored-battery = <&battery>; + + usb-vbus { + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-min-microamp = <750000>; + regulator-max-microamp = <750000>; + summit,needs-inok-toggle; + }; }; }; diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h index d918bf321a71..3205699b5e41 100644 --- a/include/dt-bindings/power/summit,smb347-charger.h +++ b/include/dt-bindings/power/summit,smb347-charger.h @@ -16,4 +16,8 @@ #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1 #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 +/* Polarity of INOK signal */ +#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0 +#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1 + #endif