From patchwork Tue Jul 6 16:02:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Liang X-Patchwork-Id: 1501386 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GK6lD4kyFz9sX1 for ; Wed, 7 Jul 2021 02:02:32 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C0E6D82D58; Tue, 6 Jul 2021 18:02:29 +0200 (CEST) Authentication-Results: phobos.denx.de; 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Wed, 7 Jul 2021 00:02:09 +0800 (GMT-8) (envelope-from ycliang@andestech.com) Received: from andestech.com (10.0.15.65) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 7 Jul 2021 00:02:12 +0800 Date: Wed, 7 Jul 2021 00:02:05 +0800 From: Leo Liang To: CC: , Subject: [PULL] u-boot-riscv/master Message-ID: <20210706160205.GA11927@andestech.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.24 (2015-08-30) X-Originating-IP: [10.0.15.65] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 166G29fa060440 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Tom, The following changes since commit 1311dd37ecf476be041d0452d4ee38619aadd5de: Merge branch '2021-07-01-update-CI-containers' (2021-07-05 15:29:44 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to 4b4159d0f31ca3e0174ccfdce9a24a1fe3671829: board: sifive: support spl multi-dtb on unmatched board (2021-07-06 20:24:26 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/8081 ---------------------------------------------------------------- Dimitri John Ledkov (1): riscv: sifive: Set default fdtfile names Green Wan (1): drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux' Tianrui Wei (2): board: riscv: add openpiton-riscv64 SoC support mmc: openpiton: add piton_mmc driver Zong Li (6): board: sifive: unmatched: add initial support for a platform ID EEPROM riscv: sifive: fu740: kconfig: Enable support for Opencores I2C controller riscv: sifive: fu740: Support i2c in spl board: sifive: Add an interface to get PCB revision riscv: dts: add dts for unmatched rev1 board: sifive: support spl multi-dtb on unmatched board arch/riscv/Kconfig | 4 + arch/riscv/cpu/fu740/Kconfig | 3 + arch/riscv/dts/Makefile | 3 +- arch/riscv/dts/fu740-c000-u-boot.dtsi | 4 + .../dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi | 1489 ++++++++++++++++++++ .../dts/hifive-unmatched-a00-rev1-u-boot.dtsi | 7 + arch/riscv/dts/hifive-unmatched-a00-rev1.dts | 4 + arch/riscv/dts/openpiton-riscv64.dts | 153 ++ arch/riscv/include/asm/arch-fu740/eeprom.h | 15 + board/openpiton/riscv64/Kconfig | 40 + board/openpiton/riscv64/MAINTAINERS | 8 + board/openpiton/riscv64/Makefile | 5 + board/openpiton/riscv64/openpiton-riscv64.c | 33 + board/sifive/unmatched/Kconfig | 1 + board/sifive/unmatched/Makefile | 1 + .../sifive/unmatched/hifive-platform-i2c-eeprom.c | 574 ++++++++ board/sifive/unmatched/spl.c | 28 +- configs/openpiton_riscv64_defconfig | 76 + configs/openpiton_riscv64_spl_defconfig | 87 ++ configs/sifive_unleashed_defconfig | 1 + configs/sifive_unmatched_defconfig | 5 + doc/board/index.rst | 1 + doc/board/openpiton/index.rst | 9 + doc/board/openpiton/riscv64.rst | 376 +++++ drivers/clk/sifive/fu740-prci.c | 6 +- drivers/mmc/Kconfig | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/piton_mmc.c | 161 +++ include/configs/openpiton-riscv64.h | 61 + include/configs/sifive-unleashed.h | 1 + include/configs/sifive-unmatched.h | 7 + 31 files changed, 3167 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr-rev1.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1-u-boot.dtsi create mode 100644 arch/riscv/dts/hifive-unmatched-a00-rev1.dts create mode 100644 arch/riscv/dts/openpiton-riscv64.dts create mode 100644 arch/riscv/include/asm/arch-fu740/eeprom.h create mode 100644 board/openpiton/riscv64/Kconfig create mode 100644 board/openpiton/riscv64/MAINTAINERS create mode 100644 board/openpiton/riscv64/Makefile create mode 100644 board/openpiton/riscv64/openpiton-riscv64.c create mode 100644 board/sifive/unmatched/hifive-platform-i2c-eeprom.c create mode 100644 configs/openpiton_riscv64_defconfig create mode 100644 configs/openpiton_riscv64_spl_defconfig create mode 100644 doc/board/openpiton/index.rst create mode 100644 doc/board/openpiton/riscv64.rst create mode 100644 drivers/mmc/piton_mmc.c create mode 100644 include/configs/openpiton-riscv64.h Best regards, Leo