From patchwork Thu Jul 1 23:43:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1499815 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=H0NwiYxr; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GGFCy6Tq0z9sT6 for ; Fri, 2 Jul 2021 09:43:58 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234400AbhGAXq0 (ORCPT ); Thu, 1 Jul 2021 19:46:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234063AbhGAXqZ (ORCPT ); Thu, 1 Jul 2021 19:46:25 -0400 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC9F2C061762; Thu, 1 Jul 2021 16:43:52 -0700 (PDT) Received: by mail-lj1-x22a.google.com with SMTP id r16so10817954ljk.9; Thu, 01 Jul 2021 16:43:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/GPfDEmQQJhXgHdxr1BFSN2ruNpULfNm16Js3A20DV4=; b=H0NwiYxrpC/IPsMqOLBtWoyM2ObE+wt15XSLmM2lYjLAYx5Up6ZUnSrwvmCcNptLti 57/yTXuiCzoU6t/alk/AL6AEe+819DmBaYs7SANK1LgN9cTYbxDgjZBFyFDWkSuah3gR 9xFir7rucR986XVnB+3Bogt6GoDD5t8gHBrkEyyssLLmeSBZ7Kg4aFuVYIjBIpA9niao IJCTulUeAjorCxrHdMQC6Su5fVkjRx8Xk2gV7UzxSnBVfouy90FQ38V2wIwotTTGDCem lHMeSfhwARqtW4qfz6bp/hrKvOkckvF1eMQ/lJh0i8T9j5JJ5zsgQge6FT6RtAAH2IH2 TzLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/GPfDEmQQJhXgHdxr1BFSN2ruNpULfNm16Js3A20DV4=; b=CaT2SbRxR5rXTauYdIhOqeH3F8kRt5nJkGHQOLy34l+I6t5captcgnd5mdVG8PfdJk LZDQc34MLHam/g/rHmC2XneWMYMkPVgfHdaN81mEovwy/HXwHsIKTSEleE6/V5cv6wxW /kpCEpuyZTCylKK+bbyrWggo8NAJYcmzr82YFyy/7On5AoDIOHhCh0+TZ4I4M8xLyV9d ARq4JiOb0lZAs69kaDNdpLrelGQyoZwC2ILW/MsBP2ra/D5vx2KsRHVEr/x0PLloVhlZ R702XYQZvxuGmDkTCRg3ZHcDdURym0CnLbNoTT58gA3VTEIPZrazLuEE8SFFU14TzYc+ 9e2A== X-Gm-Message-State: AOAM533HLWNOrkgIS6ga12RxHzR/At13vetYUdCfzVL41IniMrC0iXqK xG0/DVcCzNyCefbddznoDHE= X-Google-Smtp-Source: ABdhPJy9+JS94Te3RYhlizxvb/3uD9uANXA8P80xYZBTQ+EUgh6/j2j040wImxT1a+2/MMqrgG6zwQ== X-Received: by 2002:a2e:7306:: with SMTP id o6mr1522013ljc.125.1625183031093; Thu, 01 Jul 2021 16:43:51 -0700 (PDT) Received: from localhost.localdomain (94-29-37-113.dynamic.spd-mgts.ru. [94.29.37.113]) by smtp.gmail.com with ESMTPSA id e23sm60743lfq.221.2021.07.01.16.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jul 2021 16:43:50 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Rob Herring , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 01/12] dt-bindings: phy: tegra20-usb-phy: Convert to schema Date: Fri, 2 Jul 2021 02:43:06 +0300 Message-Id: <20210701234317.26393-2-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210701234317.26393-1-digetx@gmail.com> References: <20210701234317.26393-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert NVIDIA Tegra20 USB PHY binding to schema. Signed-off-by: Dmitry Osipenko --- .../bindings/phy/nvidia,tegra20-usb-phy.txt | 74 ---- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 357 ++++++++++++++++++ 2 files changed, 357 insertions(+), 74 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt deleted file mode 100644 index 1aa6f2674af5..000000000000 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.txt +++ /dev/null @@ -1,74 +0,0 @@ -Tegra SOC USB PHY - -The device node for Tegra SOC USB PHY: - -Required properties : - - compatible : For Tegra20, must contain "nvidia,tegra20-usb-phy". - For Tegra30, must contain "nvidia,tegra30-usb-phy". Otherwise, must contain - "nvidia,-usb-phy" plus at least one of the above, where is - tegra114, tegra124, tegra132, or tegra210. - - reg : Defines the following set of registers, in the order listed: - - The PHY's own register set. - Always present. - - The register set of the PHY containing the UTMI pad control registers. - Present if-and-only-if phy_type == utmi. - - phy_type : Should be one of "utmi", "ulpi" or "hsic". - - clocks : Defines the clocks listed in the clock-names property. - - clock-names : The following clock names must be present: - - reg: The clock needed to access the PHY's own registers. This is the - associated EHCI controller's clock. Always present. - - pll_u: PLL_U. Always present. - - timer: The timeout clock (clk_m). Present if phy_type == utmi. - - utmi-pads: The clock needed to access the UTMI pad control registers. - Present if phy_type == utmi. - - ulpi-link: The clock Tegra provides to the ULPI PHY (usually pad DAP_MCLK2 - with pad group aka "nvidia,pins" cdev2 and pin mux option config aka - "nvidia,function" pllp_out4). - Present if phy_type == ulpi, and ULPI link mode is in use. - - resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. - - reset-names : Must include the following entries: - - usb: The PHY's own reset signal. - - utmi-pads: The reset of the PHY containing the chip-wide UTMI pad control - registers. Required even if phy_type == ulpi. - -Required properties for phy_type == ulpi: - - nvidia,phy-reset-gpio : The GPIO used to reset the PHY. - -Required PHY timing params for utmi phy, for all chips: - - nvidia,hssync-start-delay : Number of 480 Mhz clock cycles to wait before - start of sync launches RxActive - - nvidia,elastic-limit : Variable FIFO Depth of elastic input store - - nvidia,idle-wait-delay : Number of 480 Mhz clock cycles of idle to wait - before declare IDLE. - - nvidia,term-range-adj : Range adjusment on terminations - - Either one of the following for HS driver output control: - - nvidia,xcvr-setup : integer, uses the provided value. - - nvidia,xcvr-setup-use-fuses : boolean, indicates that the value is read - from the on-chip fuses - If both are provided, nvidia,xcvr-setup-use-fuses takes precedence. - - nvidia,xcvr-lsfslew : LS falling slew rate control. - - nvidia,xcvr-lsrslew : LS rising slew rate control. - -Required PHY timing params for utmi phy, only on Tegra30 and above: - - nvidia,xcvr-hsslew : HS slew rate control. - - nvidia,hssquelch-level : HS squelch detector level. - - nvidia,hsdiscon-level : HS disconnect detector level. - -Optional properties: - - nvidia,has-legacy-mode : boolean indicates whether this controller can - operate in legacy mode (as APX 2500 / 2600). In legacy mode some - registers are accessed through the APB_MISC base address instead of - the USB controller. - - nvidia,is-wired : boolean. Indicates whether we can do certain kind of power - optimizations for the devices that are always connected. e.g. modem. - - dr_mode : dual role mode. Indicates the working mode for the PHY. Can be - "host", "peripheral", or "otg". Defaults to "host" if not defined. - host means this is a host controller - peripheral means it is device controller - otg means it can operate as either ("on the go") - - nvidia,has-utmi-pad-registers : boolean indicates whether this controller - contains the UTMI pad control registers common to all USB controllers. - -VBUS control (required for dr_mode == otg, optional for dr_mode == host): - - vbus-supply: regulator for VBUS diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml new file mode 100644 index 000000000000..593187234e6a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml @@ -0,0 +1,357 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra USB PHY + +maintainers: + - Dmitry Osipenko + - Jon Hunter + - Thierry Reding + +properties: + compatible: + oneOf: + - items: + - enum: + - nvidia,tegra124-usb-phy + - nvidia,tegra114-usb-phy + - enum: + - nvidia,tegra30-usb-phy + - items: + - enum: + - nvidia,tegra30-usb-phy + - nvidia,tegra20-usb-phy + + reg: + minItems: 1 + maxItems: 2 + description: | + PHY0 and PHY2 share power and ground, PHY0 contains shared registers. + PHY0 and PHY2 must specify two register sets, where the first set is + PHY own registers and the second set is the PHY0 registers. + + clocks: + anyOf: + - items: + - description: Registers clock + - description: Main PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: ULPI PHY clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI pads control registers clock + + - items: + - description: Registers clock + - description: Main PHY clock + - description: UTMI timeout clock + - description: UTMI pads control registers clock + + clock-names: + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + - items: + - const: reg + - const: pll_u + - const: utmi-pads + + - items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + resets: + oneOf: + - maxItems: 1 + description: PHY reset + + - items: + - description: PHY reset + - description: UTMI pads reset + + reset-names: + oneOf: + - const: usb + + - items: + - const: usb + - const: utmi-pads + + "#phy-cells": + const: 0 + + phy_type: + $ref: /schemas/types.yaml#/definitions/string + enum: [utmi, ulpi, hsic] + + dr_mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [host, peripheral, otg] + default: host + + vbus-supply: + description: Regulator controlling USB VBUS. + + nvidia,has-legacy-mode: + description: | + Indicates whether this controller can operate in legacy mode + (as APX 2500 / 2600). In legacy mode some registers are accessed + through the APB_MISC base address instead of the USB controller. + type: boolean + + nvidia,is-wired: + description: | + Indicates whether we can do certain kind of power optimizations for + the devices that are always connected. e.g. modem. + type: boolean + + nvidia,has-utmi-pad-registers: + description: | + Indicates whether this controller contains the UTMI pad control + registers common to all USB controllers. + type: boolean + + nvidia,hssync-start-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles to wait before start of sync launches + RxActive. + + nvidia,elastic-limit: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: Variable FIFO Depth of elastic input store. + + nvidia,idle-wait-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: | + Number of 480 MHz clock cycles of idle to wait before declare IDLE. + + nvidia,term-range-adj: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Range adjustment on terminations. + + nvidia,xcvr-setup: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 127 + description: Input of XCVR cell, HS driver output control. + + nvidia,xcvr-setup-use-fuses: + description: Indicates that the value is read from the on-chip fuses. + type: boolean + + nvidia,xcvr-lsfslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS falling slew rate control. + + nvidia,xcvr-lsrslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: LS rising slew rate control. + + nvidia,xcvr-hsslew: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 511 + description: HS slew rate control. + + nvidia,hssquelch-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 3 + description: HS squelch detector level. + + nvidia,hsdiscon-level: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: HS disconnect detector level. + + nvidia,phy-reset-gpio: + maxItems: 1 + description: GPIO used to reset the PHY. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + - phy_type + +additionalProperties: false + +allOf: + - if: + properties: + phy_type: + const: utmi + + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + + required: + - nvidia,hssync-start-delay + - nvidia,elastic-limit + - nvidia,idle-wait-delay + - nvidia,term-range-adj + - nvidia,xcvr-lsfslew + - nvidia,xcvr-lsrslew + + anyOf: + - required: ["nvidia,xcvr-setup"] + - required: ["nvidia,xcvr-setup-use-fuses"] + + if: + properties: + compatible: + contains: + const: nvidia,tegra30-usb-phy + + then: + properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: reg + - const: pll_u + - const: utmi-pads + + required: + - nvidia,xcvr-hsslew + - nvidia,hssquelch-level + - nvidia,hsdiscon-level + + else: + properties: + clocks: + maxItems: 4 + + clock-names: + items: + - const: reg + - const: pll_u + - const: timer + - const: utmi-pads + + - if: + properties: + phy_type: + const: ulpi + + then: + properties: + reg: + minItems: 1 + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + maxItems: 3 + + oneOf: + - items: + - const: reg + - const: pll_u + + - items: + - const: reg + - const: pll_u + - const: ulpi-link + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 + +examples: + - | + #include + + usb-phy@7d008000 { + compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; + reg = <0x7d008000 0x4000>, + <0x7d000000 0x4000>; + phy_type = "utmi"; + clocks = <&tegra_car TEGRA124_CLK_USB3>, + <&tegra_car TEGRA124_CLK_PLL_U>, + <&tegra_car TEGRA124_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + resets = <&tegra_car 59>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + nvidia,hssync-start-delay = <0>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <9>; + nvidia,xcvr-lsfslew = <0>; + nvidia,xcvr-lsrslew = <3>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; + nvidia,xcvr-hsslew = <12>; + }; + + - | + #include + + usb-phy@c5004000 { + compatible = "nvidia,tegra20-usb-phy"; + reg = <0xc5004000 0x4000>; + phy_type = "ulpi"; + clocks = <&tegra_car TEGRA20_CLK_USB2>, + <&tegra_car TEGRA20_CLK_PLL_U>, + <&tegra_car TEGRA20_CLK_CDEV2>; + clock-names = "reg", "pll_u", "ulpi-link"; + resets = <&tegra_car 58>, <&tegra_car 22>; + reset-names = "usb", "utmi-pads"; + #phy-cells = <0>; + }; From patchwork Thu Jul 1 23:43:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1499813 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=t4Wwozpd; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GGFCw2kffz9sjD for ; Fri, 2 Jul 2021 09:43:56 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234370AbhGAXqZ (ORCPT ); Thu, 1 Jul 2021 19:46:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234352AbhGAXqY (ORCPT ); Thu, 1 Jul 2021 19:46:24 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 720D8C061764; Thu, 1 Jul 2021 16:43:53 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id u20so10780956ljo.12; Thu, 01 Jul 2021 16:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=adJQUfPeiRUepTm54Dxm95RAQuwCijRoZlMsrd5sNGE=; b=t4WwozpdNtQFm35n9vvIaC+3/5uF/mj+RGDBfVbac6Q8gdx0e68DgGpBd/ZWYnYRy5 rRJVfBUY8GSWhsez485W9CfUou+UtylEFooQ9N3acejkPXqFqj6D7wUWCaxK4K8hSAjZ dCAw1d+zqsdcJFhE30UelMsJHRf7D1gAoqXbOzaCZy3sa/lflKUGE4cAZBtiDKLf7JFA mghrjxXa9UlzKnmP+NQy9DTYZ121pCOYqwRynadzRZdXQUeKFOj+ZF0JA8TYiNq1Netg 8Nzqo48/GVlB9pTLFVmoS/r3lU/RnW7yxxjQhKka5IvrIFW+eR4RTtwN1DzQSSNz9QEH Wu/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=adJQUfPeiRUepTm54Dxm95RAQuwCijRoZlMsrd5sNGE=; b=pYKEvQkTkcc4esOndwOOuJley7kD2ks8BBaNUqNfOoNqeARAQBKPwkimPnO5JnLdxn 2aisci2qif0/W8wmQ9AbAc4sDXZ5jpMYJiT7+DjtO0Za3qseadnEzhfcSTWBA+5Pc2UQ CJbxBRy/6JFgmCKyWYFT94SSlWQXrSYLuWNGv5tTrftmzuDn1UU9iXSlqjdgdJc4VF8P OU3TAwZ8PbCRCL3hN/3D54lB4k61+G5/wzntIDc4+IFtbduXB0qj8x8I/Z9bj5RMICBw 8jH/R9E2U8L2TllMOQ+Rj2/lw5BuAhL8ko2+B8k42uAI7npjgnTAlQ/rA3Qr0lYrp/Kz EA8w== X-Gm-Message-State: AOAM532jiK7rsxH47IgPYRFREA7iVlKMkhhy+WaLaA3w6a/g6atgQBny L4mugxkRc3/qMOv2GZdHBwY= X-Google-Smtp-Source: ABdhPJwVf6Y/f55g2R6MJe4/lIwGUkfZNzgt5agcmDHckVkkenxJG89Yu0PLVAPgVPtTYj4gZ9gtHw== X-Received: by 2002:a2e:9152:: with SMTP id q18mr1510345ljg.493.1625183031834; Thu, 01 Jul 2021 16:43:51 -0700 (PDT) Received: from localhost.localdomain (94-29-37-113.dynamic.spd-mgts.ru. [94.29.37.113]) by smtp.gmail.com with ESMTPSA id e23sm60743lfq.221.2021.07.01.16.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jul 2021 16:43:51 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Rob Herring , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 02/12] dt-bindings: phy: tegra20-usb-phy: Document properties needed for OTG mode Date: Fri, 2 Jul 2021 02:43:07 +0300 Message-Id: <20210701234317.26393-3-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210701234317.26393-1-digetx@gmail.com> References: <20210701234317.26393-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to support OTG mode we need these new properties: - interrupt - nvidia,pmc - nvidia,phy-instance The nvidia,phy-instance isn't strictly needed for the OTG mode since we know that only first controller supports it in practice, but it will be needed in general for supporting more complex hardware features that require knowledge of the PHY offset within common registers of the Power Management controller (PMC). Add the new properties to the bindings. Signed-off-by: Dmitry Osipenko --- .../bindings/phy/nvidia,tegra20-usb-phy.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml index 593187234e6a..a108f1552042 100644 --- a/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra20-usb-phy.yaml @@ -77,6 +77,9 @@ properties: - const: timer - const: utmi-pads + interrupts: + maxItems: 1 + resets: oneOf: - maxItems: 1 @@ -199,6 +202,17 @@ properties: maxItems: 1 description: GPIO used to reset the PHY. + nvidia,pmc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to Power Management controller. + + nvidia,phy-instance: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 2 + description: Unique hardware ID. + required: - compatible - reg @@ -320,6 +334,7 @@ examples: compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000>, <0x7d000000 0x4000>; + interrupts = <0 97 4>; phy_type = "utmi"; clocks = <&tegra_car TEGRA124_CLK_USB3>, <&tegra_car TEGRA124_CLK_PLL_U>, @@ -338,6 +353,8 @@ examples: nvidia,hssquelch-level = <2>; nvidia,hsdiscon-level = <5>; nvidia,xcvr-hsslew = <12>; + nvidia,pmc = <&tegra_pmc>; + nvidia,phy-instance= <2>; }; - | @@ -346,6 +363,7 @@ examples: usb-phy@c5004000 { compatible = "nvidia,tegra20-usb-phy"; reg = <0xc5004000 0x4000>; + interrupts = <0 21 4>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>, <&tegra_car TEGRA20_CLK_PLL_U>, @@ -354,4 +372,6 @@ examples: resets = <&tegra_car 58>, <&tegra_car 22>; reset-names = "usb", "utmi-pads"; #phy-cells = <0>; + nvidia,pmc = <&tegra_pmc>; + nvidia,phy-instance= <1>; }; From patchwork Thu Jul 1 23:43:11 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 1499818 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=BKUihBPI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GGFD50CfMz9srZ for ; Fri, 2 Jul 2021 09:44:05 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234564AbhGAXqd (ORCPT ); Thu, 1 Jul 2021 19:46:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234463AbhGAXq3 (ORCPT ); Thu, 1 Jul 2021 19:46:29 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FA8FC061764; Thu, 1 Jul 2021 16:43:56 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id f13so10812825ljp.10; Thu, 01 Jul 2021 16:43:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IwL3qryTNfgwkU5i7nwmV+nzWjMAB8DcHs6NfVFo2aw=; b=BKUihBPIMJywpAfV/nid00lybHpBf24+14TosiwolYNHAWVQ1+ZCPdvTtNtHpWb5cG b6BfqWKWW6mzuvAa6BBo3ybzmtC+dpgWeT8Cwduiphwhqrc//uAwQLYwbibnBHbJV3Vj DxhYXow8WAWwt2b/84OvpnchgOODlf7csu70bMNI8wypYk5qKaZQBEFQUNkqBkycOO/Y mvG6n9gEFDrcaTIrJ/RBVsWopnDYRP919T1wn69hWNZA6PC1f7yJzAlkNzYJhg+HaUrX zZ0LmhjMOg2N8qC2EoqFrwF0c27d+4MS3ETUXR9jeqb7CC+YWfTjYd9ZN1PDjCTorD+9 mhfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IwL3qryTNfgwkU5i7nwmV+nzWjMAB8DcHs6NfVFo2aw=; b=O7FH8nUXWDhTxlLbz0erWLtfEM0RLRQdJmmJkedEk0x9o0eEyhIP+RBi4ZSM4NZ5eR WuDI5ZU664gZaWYfvp7qJF9OjO0oqEJ4USeY3PE5408fRB11VF2xVmoojzzn8FIpi0yD rF4RwifihNNgZkcR3BpmDQ/1w81HiXa6mW4UwE6hXAYSACGLGRUQyxcVCPf+/SHKYJEq vKdeIF01yOFZBYi1//lE3MSqnaUzr4XbNGMRpiOn7Mv52H2mJQHxle+H1Hnz3eocQID8 zibpoFytf62FHtTnw+lWdVhrD5PnG0DZ7XnirRbb6PstyyjwdjK8fH1UIvyFD4vIbQwJ 8aPg== X-Gm-Message-State: AOAM5325j6xTWW8UgvEJLd/KVd/pE8X+vRRd9OgmTBRo512AlTXOkFxd 1fgEX95KKS6UmY/sAspm8PM= X-Google-Smtp-Source: ABdhPJxsCwE3BLANWd00uATwXAW/o0frKYGXJeT8IRA1iLbVbOX28mWmGwQOWtwob0GtIxj7x/SqUQ== X-Received: by 2002:a2e:b8c9:: with SMTP id s9mr1591294ljp.426.1625183034746; Thu, 01 Jul 2021 16:43:54 -0700 (PDT) Received: from localhost.localdomain (94-29-37-113.dynamic.spd-mgts.ru. [94.29.37.113]) by smtp.gmail.com with ESMTPSA id e23sm60743lfq.221.2021.07.01.16.43.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Jul 2021 16:43:54 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Mark Brown , Rob Herring , Sebastian Reichel , Peter Chen , Greg Kroah-Hartman , Felipe Balbi , David Heidelberg Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v2 06/12] dt-bindings: power: supply: smb347-charger: Document USB VBUS regulator Date: Fri, 2 Jul 2021 02:43:11 +0300 Message-Id: <20210701234317.26393-7-digetx@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210701234317.26393-1-digetx@gmail.com> References: <20210701234317.26393-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SMB347 can supply power to USB VBUS, which is required by OTG-cable devices that want to switch USB port into the host mode. Add USB VBUS regulator properties. Signed-off-by: Dmitry Osipenko --- .../power/supply/summit,smb347-charger.yaml | 28 +++++++++++++++++++ .../dt-bindings/power/summit,smb347-charger.h | 4 +++ 2 files changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml index 983fc215c1e5..cd3d834f734d 100644 --- a/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml +++ b/Documentation/devicetree/bindings/power/supply/summit,smb347-charger.yaml @@ -73,6 +73,24 @@ properties: - 1 # SMB3XX_SOFT_TEMP_COMPENSATE_CURRENT Current compensation - 2 # SMB3XX_SOFT_TEMP_COMPENSATE_VOLTAGE Voltage compensation + summit,inok-polarity: + description: | + Polarity of INOK signal indicating presence of external power supply. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # SMB3XX_SYSOK_INOK_ACTIVE_LOW + - 1 # SMB3XX_SYSOK_INOK_ACTIVE_HIGH + + usb-vbus: + $ref: "../../regulator/regulator.yaml#" + type: object + + properties: + summit,needs-inok-toggle: + type: boolean + description: INOK signal is fixed and polarity needs to be toggled + in order to enable/disable output mode. + allOf: - if: properties: @@ -134,6 +152,7 @@ examples: reg = <0x7f>; summit,enable-charge-control = ; + summit,inok-polarity = ; summit,chip-temperature-threshold-celsius = <110>; summit,mains-current-limit-microamp = <2000000>; summit,usb-current-limit-microamp = <500000>; @@ -141,6 +160,15 @@ examples: summit,enable-mains-charging; monitored-battery = <&battery>; + + usb-vbus { + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-min-microamp = <750000>; + regulator-max-microamp = <750000>; + summit,needs-inok-toggle; + }; }; }; diff --git a/include/dt-bindings/power/summit,smb347-charger.h b/include/dt-bindings/power/summit,smb347-charger.h index d918bf321a71..3205699b5e41 100644 --- a/include/dt-bindings/power/summit,smb347-charger.h +++ b/include/dt-bindings/power/summit,smb347-charger.h @@ -16,4 +16,8 @@ #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW 1 #define SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH 2 +/* Polarity of INOK signal */ +#define SMB3XX_SYSOK_INOK_ACTIVE_LOW 0 +#define SMB3XX_SYSOK_INOK_ACTIVE_HIGH 1 + #endif