From patchwork Tue Jun 29 15:38:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1498434 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GDpXs2v1Vz9sW8 for ; Wed, 30 Jun 2021 01:38:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234959AbhF2PlD (ORCPT ); Tue, 29 Jun 2021 11:41:03 -0400 Received: from out28-171.mail.aliyun.com ([115.124.28.171]:60433 "EHLO out28-171.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234885AbhF2PlC (ORCPT ); Tue, 29 Jun 2021 11:41:02 -0400 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.1129384|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.00557325-0.000430199-0.993997;FP=4538976329095284722|3|2|8|0|-1|-1|-1;HT=ay29a033018047190;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=14;RT=14;SR=0;TI=SMTPD_---.KZtCVfJ_1624981102; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZtCVfJ_1624981102) by smtp.aliyun-inc.com(10.147.44.118); Tue, 29 Jun 2021 23:38:31 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v6 03/11] dt-bindings: clock: Add missing clocks for Ingenic SoCs. Date: Tue, 29 Jun 2021 23:38:14 +0800 Message-Id: <1624981102-26248-4-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add MACPHY, CIM, AIC, DMIC, I2S clocks bindings for the X1000 SoC and the X1830 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil Acked-by: Rob Herring --- Notes: v1->v2: 1.Add MACPHY and I2S for X1000, and add MACPHY for X1830. 2.Add Paul Cercueil's Reviewed-by and Rob Herring's Acked-by. v2->v3: No change. v3->v4: No change. v4->v5: Add CIM, AIC, DMIC for X1000, and add CIM, AIC, DMIC, I2S for X1830. v5->v6: No change. include/dt-bindings/clock/x1000-cgu.h | 5 +++++ include/dt-bindings/clock/x1830-cgu.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h index f187e07..3e79f36 100644 --- a/include/dt-bindings/clock/x1000-cgu.h +++ b/include/dt-bindings/clock/x1000-cgu.h @@ -50,5 +50,10 @@ #define X1000_CLK_PDMA 35 #define X1000_CLK_EXCLK_DIV512 36 #define X1000_CLK_RTC 37 +#define X1000_CLK_MACPHY 38 +#define X1000_CLK_CIM 39 +#define X1000_CLK_AIC 40 +#define X1000_CLK_DMIC 41 +#define X1000_CLK_I2S 42 #endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */ diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h index 8845537..8da2997 100644 --- a/include/dt-bindings/clock/x1830-cgu.h +++ b/include/dt-bindings/clock/x1830-cgu.h @@ -53,5 +53,10 @@ #define X1830_CLK_OST 38 #define X1830_CLK_EXCLK_DIV512 39 #define X1830_CLK_RTC 40 +#define X1830_CLK_MACPHY 41 +#define X1830_CLK_CIM 42 +#define X1830_CLK_AIC 43 +#define X1830_CLK_DMIC 44 +#define X1830_CLK_I2S 45 #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */ From patchwork Tue Jun 29 15:38:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1498435 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GDpXz2JLtz9sWM for ; Wed, 30 Jun 2021 01:38:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235010AbhF2PlI (ORCPT ); Tue, 29 Jun 2021 11:41:08 -0400 Received: from out28-194.mail.aliyun.com ([115.124.28.194]:39539 "EHLO out28-194.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234936AbhF2PlG (ORCPT ); Tue, 29 Jun 2021 11:41:06 -0400 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.507149|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.0604461-0.00470573-0.934848;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047188;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=14;RT=14;SR=0;TI=SMTPD_---.KZtCVfJ_1624981102; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZtCVfJ_1624981102) by smtp.aliyun-inc.com(10.147.44.118); Tue, 29 Jun 2021 23:38:35 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v6 07/11] dt-bindings: clock: Add documentation for JZ4775 and X2000 bindings. Date: Tue, 29 Jun 2021 23:38:18 +0800 Message-Id: <1624981102-26248-8-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation for the clock bindings of the JZ4775 SoC and the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Acked-by: Rob Herring --- Notes: v5: New patch. v5->v6: No change. Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index 6d6236e..5d699b3 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -25,9 +25,11 @@ select: - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu + - ingenic,jz4775-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu - ingenic,x1830-cgu + - ingenic,x2000-cgu required: - compatible @@ -54,9 +56,11 @@ properties: - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu + - ingenic,jz4775-cgu - ingenic,jz4780-cgu - ingenic,x1000-cgu - ingenic,x1830-cgu + - ingenic,x2000-cgu - const: simple-mfd minItems: 1 From patchwork Tue Jun 29 15:38:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1498436 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GDpY053nfz9sWM for ; Wed, 30 Jun 2021 01:38:44 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235004AbhF2PlK (ORCPT ); Tue, 29 Jun 2021 11:41:10 -0400 Received: from out28-75.mail.aliyun.com ([115.124.28.75]:49626 "EHLO out28-75.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235000AbhF2PlH (ORCPT ); Tue, 29 Jun 2021 11:41:07 -0400 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.2638936|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.00620392-0.000189541-0.993607;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047203;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=14;RT=14;SR=0;TI=SMTPD_---.KZtCVfJ_1624981102; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZtCVfJ_1624981102) by smtp.aliyun-inc.com(10.147.44.118); Tue, 29 Jun 2021 23:38:36 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v6 08/11] dt-bindings: clock: Add JZ4775 clock bindings. Date: Tue, 29 Jun 2021 23:38:19 +0800 Message-Id: <1624981102-26248-9-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the clock bindings for the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. v5->v6: No change. include/dt-bindings/clock/jz4775-cgu.h | 59 ++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 include/dt-bindings/clock/jz4775-cgu.h diff --git a/include/dt-bindings/clock/jz4775-cgu.h b/include/dt-bindings/clock/jz4775-cgu.h new file mode 100644 index 00000000..8c2af69 --- /dev/null +++ b/include/dt-bindings/clock/jz4775-cgu.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4775-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the jz4775 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4775_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4775_CGU_H__ + +#define JZ4775_CLK_EXCLK 0 +#define JZ4775_CLK_RTCLK 1 +#define JZ4775_CLK_APLL 2 +#define JZ4775_CLK_MPLL 3 +#define JZ4775_CLK_OTGPHY 4 +#define JZ4775_CLK_SCLKA 5 +#define JZ4775_CLK_UHC 6 +#define JZ4775_CLK_UHCPHY 7 +#define JZ4775_CLK_CPUMUX 8 +#define JZ4775_CLK_CPU 9 +#define JZ4775_CLK_L2CACHE 10 +#define JZ4775_CLK_AHB0 11 +#define JZ4775_CLK_AHB2PMUX 12 +#define JZ4775_CLK_AHB2 13 +#define JZ4775_CLK_PCLK 14 +#define JZ4775_CLK_DDR 15 +#define JZ4775_CLK_VPU 16 +#define JZ4775_CLK_OTG 17 +#define JZ4775_CLK_EXCLK_DIV2 18 +#define JZ4775_CLK_I2S 19 +#define JZ4775_CLK_LCD 20 +#define JZ4775_CLK_MSCMUX 21 +#define JZ4775_CLK_MSC0 22 +#define JZ4775_CLK_MSC1 23 +#define JZ4775_CLK_MSC2 24 +#define JZ4775_CLK_SSI 25 +#define JZ4775_CLK_CIM0 26 +#define JZ4775_CLK_CIM1 27 +#define JZ4775_CLK_PCM 28 +#define JZ4775_CLK_BCH 29 +#define JZ4775_CLK_EXCLK_DIV512 30 +#define JZ4775_CLK_RTC 31 +#define JZ4775_CLK_NEMC 32 +#define JZ4775_CLK_I2C0 33 +#define JZ4775_CLK_I2C1 34 +#define JZ4775_CLK_I2C2 35 +#define JZ4775_CLK_SADC 36 +#define JZ4775_CLK_UART0 37 +#define JZ4775_CLK_UART1 38 +#define JZ4775_CLK_UART2 39 +#define JZ4775_CLK_UART3 40 +#define JZ4775_CLK_PDMA 41 +#define JZ4775_CLK_MAC 42 + +#endif /* __DT_BINDINGS_CLOCK_JZ4775_CGU_H__ */ From patchwork Tue Jun 29 15:38:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Zhou Yanjie X-Patchwork-Id: 1498437 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GDpY10XY8z9sWX for ; Wed, 30 Jun 2021 01:38:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235047AbhF2PlK (ORCPT ); Tue, 29 Jun 2021 11:41:10 -0400 Received: from out28-2.mail.aliyun.com ([115.124.28.2]:55281 "EHLO out28-2.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234984AbhF2PlI (ORCPT ); Tue, 29 Jun 2021 11:41:08 -0400 X-Alimail-AntiSpam: AC=CONTINUE;BC=0.2779463|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_regular_dialog|0.0239892-0.00116343-0.974847;FP=0|0|0|0|0|-1|-1|-1;HT=ay29a033018047202;MF=zhouyanjie@wanyeetech.com;NM=1;PH=DS;RN=14;RT=14;SR=0;TI=SMTPD_---.KZtCVfJ_1624981102; Received: from zhouyanjie-virtual-machine.localdomain(mailfrom:zhouyanjie@wanyeetech.com fp:SMTPD_---.KZtCVfJ_1624981102) by smtp.aliyun-inc.com(10.147.44.118); Tue, 29 Jun 2021 23:38:37 +0800 From: =?utf-8?b?5ZGo55Cw5p2wIChaaG91IFlhbmppZSk=?= To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org Cc: linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, paul@crapouillou.net, dongsheng.qiu@ingenic.com, aric.pzqi@ingenic.com, rick.tyliu@ingenic.com, sihui.liu@ingenic.com, jun.jiang@ingenic.com, sernia.zhou@foxmail.com Subject: [PATCH v6 09/11] dt-bindings: clock: Add X2000 clock bindings. Date: Tue, 29 Jun 2021 23:38:20 +0800 Message-Id: <1624981102-26248-10-git-send-email-zhouyanjie@wanyeetech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> References: <1624981102-26248-1-git-send-email-zhouyanjie@wanyeetech.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the clock bindings for the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) --- Notes: v5: New patch. v5->v6: No change. include/dt-bindings/clock/x2000-cgu.h | 88 +++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 include/dt-bindings/clock/x2000-cgu.h diff --git a/include/dt-bindings/clock/x2000-cgu.h b/include/dt-bindings/clock/x2000-cgu.h new file mode 100644 index 00000000..222468d --- /dev/null +++ b/include/dt-bindings/clock/x2000-cgu.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,x2000-cgu DT binding. + * + * They are roughly ordered as: + * - external clocks + * - PLLs + * - muxes/dividers in the order they appear in the x2000 programmers manual + * - gates in order of their bit in the CLKGR* registers + */ + +#ifndef __DT_BINDINGS_CLOCK_X2000_CGU_H__ +#define __DT_BINDINGS_CLOCK_X2000_CGU_H__ + +#define X2000_CLK_EXCLK 0 +#define X2000_CLK_RTCLK 1 +#define X2000_CLK_APLL 2 +#define X2000_CLK_MPLL 3 +#define X2000_CLK_EPLL 4 +#define X2000_CLK_OTGPHY 5 +#define X2000_CLK_SCLKA 6 +#define X2000_CLK_I2S0 7 +#define X2000_CLK_I2S1 8 +#define X2000_CLK_I2S2 9 +#define X2000_CLK_I2S3 10 +#define X2000_CLK_CPUMUX 11 +#define X2000_CLK_CPU 12 +#define X2000_CLK_L2CACHE 13 +#define X2000_CLK_AHB0 14 +#define X2000_CLK_AHB2PMUX 15 +#define X2000_CLK_AHB2 16 +#define X2000_CLK_PCLK 17 +#define X2000_CLK_DDR 18 +#define X2000_CLK_ISP 19 +#define X2000_CLK_MACPTP 20 +#define X2000_CLK_MACPHY 21 +#define X2000_CLK_MAC0TX 22 +#define X2000_CLK_MAC1TX 23 +#define X2000_CLK_RSA 24 +#define X2000_CLK_SSIPLL 25 +#define X2000_CLK_LCD 26 +#define X2000_CLK_MSC0 27 +#define X2000_CLK_MSC1 28 +#define X2000_CLK_MSC2 29 +#define X2000_CLK_PWM 30 +#define X2000_CLK_SFC 31 +#define X2000_CLK_CIM 32 +#define X2000_CLK_DMIC_EXCLK 33 +#define X2000_CLK_DMIC 34 +#define X2000_CLK_EXCLK_DIV512 35 +#define X2000_CLK_RTC 36 +#define X2000_CLK_EMC 37 +#define X2000_CLK_EFUSE 38 +#define X2000_CLK_OTG 39 +#define X2000_CLK_SCC 40 +#define X2000_CLK_I2C0 41 +#define X2000_CLK_I2C1 42 +#define X2000_CLK_I2C2 43 +#define X2000_CLK_I2C3 44 +#define X2000_CLK_SADC 45 +#define X2000_CLK_UART0 46 +#define X2000_CLK_UART1 47 +#define X2000_CLK_UART2 48 +#define X2000_CLK_DTRNG 49 +#define X2000_CLK_TCU 50 +#define X2000_CLK_SSI0 51 +#define X2000_CLK_OST 52 +#define X2000_CLK_PDMA 53 +#define X2000_CLK_SSI1 54 +#define X2000_CLK_I2C4 55 +#define X2000_CLK_I2C5 56 +#define X2000_CLK_ISP0 57 +#define X2000_CLK_ISP1 58 +#define X2000_CLK_HASH 59 +#define X2000_CLK_UART3 60 +#define X2000_CLK_UART4 61 +#define X2000_CLK_UART5 62 +#define X2000_CLK_UART6 63 +#define X2000_CLK_UART7 64 +#define X2000_CLK_UART8 65 +#define X2000_CLK_UART9 66 +#define X2000_CLK_MAC0 67 +#define X2000_CLK_MAC1 68 +#define X2000_CLK_INTC 69 +#define X2000_CLK_CSI 70 +#define X2000_CLK_DSI 71 + +#endif /* __DT_BINDINGS_CLOCK_X2000_CGU_H__ */