From patchwork Tue Jun 29 14:50:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julian Brown X-Patchwork-Id: 1498393 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GDnVv3Wqzz9sWG for ; Wed, 30 Jun 2021 00:51:51 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5E1AE389682B for ; Tue, 29 Jun 2021 14:51:49 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id 0ABB13864813 for ; Tue, 29 Jun 2021 14:50:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0ABB13864813 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: qRnOJavE4xbKz0zOw52wSvvrDwWGnqP5sdRxywh4+7bmzkS8zWI5MvtSUvqyhEc7k/qn5cUbXI gMiuC8NE1VklQT0MTgRccxykq6FXJzR8JAUPgI/5vVOJa5zErYOb+UycpNP7gIfsyAc0VlRY0Y xCdWaGDTTW/XgkQ9qTS4tkcHQJYpGKX3v+l/PJE+0DI1aKTHT49VsvJq+rXeDQKXaimpZWIgQn HHVjN93nFq6hPgGFzSQLLI9iY0fD0gZ6aJJRZdCCB4wbJ71igijGvdMuvZ8TrPaoNyv91cUCZ0 g54= X-IronPort-AV: E=Sophos;i="5.83,309,1616486400"; d="scan'208";a="65377577" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 29 Jun 2021 06:50:55 -0800 IronPort-SDR: Tp6lTSGDT6AbUG9mx+S8GKQYdv8UPdJSbhs5O/M5cAkVATEfVG9MCbj8Xw6KLvzjgU3P4s3uei UTlwe72Ha05+2oAxhgkmTKUEODy5JstYto3occzPRRrPo/ZOhehCdxWD9gswz2wAnmb92Gl9za DBhZtXl5+0PrsssyKsgqkKRAiJD2flQkbHE8KazlVqtG0XEn6DeEA2XPh73oGsEGzhnPRNxIWs DM33J7WT3+m9wrI0z12+pp6bTjf7wwCH6aj87BWpJ/UzI2EhT3GiW9e+qznirQQfMNKkGbSNvl ZWw= From: Julian Brown To: Subject: [PATCH 1/3] amdgcn: Mark s_mulk_i32 as clobbering SCC Date: Tue, 29 Jun 2021 07:50:38 -0700 Message-ID: <5d5678393d10b9954479062cd145766f3b508adb.1624977771.git.julian@codesourcery.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) To SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Stubbs Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" The s_mulk_i32 instruction sets the SCC status register according to whether the multiplication overflows, but that is not currently modelled in the GCN backend. AFAIK this is a latent bug and hasn't been noticed "in the wild", but it should be fixed. I will commit shortly. Julian 2021-06-29 Julian Brown gcc/ * config/gcn/gcn.md (mulsi3): Make s_mulk_i32 variant clobber SCC. --- gcc/config/gcn/gcn.md | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index b5f895a93e2..cca45522fba 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -1371,10 +1371,13 @@ ; Vector multiply has vop3a encoding, but no corresponding vop2a, so no long ; immediate. +; The "s_mulk_i32" variant sets SCC to indicate overflow (which we don't care +; about here, but we need to indicate the clobbering). (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "= Sg,Sg, Sg, v") (mult:SI (match_operand:SI 1 "gcn_alu_operand" "%SgA, 0,SgA, v") - (match_operand:SI 2 "gcn_alu_operand" " SgA, J, B,vASv")))] + (match_operand:SI 2 "gcn_alu_operand" " SgA, J, B,vASv"))) + (clobber (match_scratch:BI 3 "=X,cs, X, X"))] "" "@ s_mul_i32\t%0, %1, %2 From patchwork Tue Jun 29 14:50:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julian Brown X-Patchwork-Id: 1498394 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GDnWh2fj5z9sWK for ; Wed, 30 Jun 2021 00:52:31 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 95B643890029 for ; Tue, 29 Jun 2021 14:52:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id 1C57A383E80A for ; Tue, 29 Jun 2021 14:50:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1C57A383E80A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: qhNkpoeFzIFXrzdfCuuuDHuwsNG6rA3HDdtbOsIZqQVO5BxVtnsAKSayn2+dKCT3mp3rwnYNs1 HvItZDGdrYr8PfwM7lohdMq90ZsCvM5MZ/J+L3WZcTrKg4Qs7REYM+bLD2AV+FG/QDj9GOBmi1 HdgAOlvUwwuGEhaIYGxR+sAGVJMO6jmgUuO11qEDhUfUWtHatvclobCi+49joOq+eUSqTehqlV U4h74wZ0jyEwaM4G99YVc+/BRdS6LuovwbsyW1tmYqerMZf/xurFX2SY1ZM8vbVh6pySCOimXE AOE= X-IronPort-AV: E=Sophos;i="5.83,309,1616486400"; d="scan'208";a="65377579" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 29 Jun 2021 06:50:56 -0800 IronPort-SDR: VdUpGBidC8Qgef7JuPetVu09E5wiZRV5VxuTwJgSHQpkW+mZ7qx2HyK0GDHWbtvt4wRLvuDh6Y KFQVQerybiIEHuiiEpH8sLcn9n240zT4HrIaNSJMNdmQ5ivCbN1f3MFQp78/hf9DPa6Z+3EoNL L/4Pzb07EPQ9xSKhOe3vcWo2XsKvBBh3gZqlk4OTnbg/zgLPhSLko1mO8TZ0I3+2RTvwKOMQyc dEC6oqc/LrT3MMdW9D8slLMkzGtlV5dSspvIFf0kCgAz+okg/gFQ/RmZBI36UuJMLD8x4w4Fb6 p28= From: Julian Brown To: Subject: [PATCH 2/3] amdgcn: Add [us]mulsi3_highpart SGPR alternatives Date: Tue, 29 Jun 2021 07:50:39 -0700 Message-ID: <2a36b2801da06b9d041941d8fdbd5b54d1cbfeb7.1624977771.git.julian@codesourcery.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) To SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Stubbs Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch splits the mulsi3_highpart pattern into an expander and register/immediate alternatives (to avoid meaningless sign/zero_extends on constants), and adds alternatives for SGPR high-part multiply instructions on GCN5+. I will apply shortly. Julian 2021-06-29 Julian Brown gcc/ * config/gcn/gcn.md (mulsi3_highpart): Change to expander. (mulsi3_highpart_reg, mulsi3_highpart_imm): New patterns. --- gcc/config/gcn/gcn.md | 62 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 55 insertions(+), 7 deletions(-) diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index cca45522fba..d1d49981ebb 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -1394,20 +1394,68 @@ (define_code_attr iu [(sign_extend "i") (zero_extend "u")]) (define_code_attr e [(sign_extend "e") (zero_extend "")]) -(define_insn "mulsi3_highpart" - [(set (match_operand:SI 0 "register_operand" "= v") +(define_expand "mulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "") (truncate:SI (lshiftrt:DI (mult:DI (any_extend:DI - (match_operand:SI 1 "register_operand" "% v")) + (match_operand:SI 1 "register_operand" "")) (any_extend:DI - (match_operand:SI 2 "register_operand" "vSv"))) + (match_operand:SI 2 "gcn_alu_operand" ""))) (const_int 32))))] "" - "v_mul_hi0\t%0, %2, %1" - [(set_attr "type" "vop3a") - (set_attr "length" "8")]) +{ + if (can_create_pseudo_p () + && !TARGET_GCN5 + && !gcn_inline_immediate_operand (operands[2], SImode)) + operands[2] = force_reg (SImode, operands[2]); + + if (REG_P (operands[2])) + emit_insn (gen_mulsi3_highpart_reg (operands[0], operands[1], + operands[2])); + else + emit_insn (gen_mulsi3_highpart_imm (operands[0], operands[1], + operands[2])); + + DONE; +}) + +(define_insn "mulsi3_highpart_reg" + [(set (match_operand:SI 0 "register_operand" "=Sg, v") + (truncate:SI + (lshiftrt:DI + (mult:DI + (any_extend:DI + (match_operand:SI 1 "register_operand" "%Sg, v")) + (any_extend:DI + (match_operand:SI 2 "register_operand" "Sg,vSv"))) + (const_int 32))))] + "" + "@ + s_mul_hi0\t%0, %1, %2 + v_mul_hi0\t%0, %2, %1" + [(set_attr "type" "sop2,vop3a") + (set_attr "length" "4,8") + (set_attr "gcn_version" "gcn5,*")]) + +(define_insn "mulsi3_highpart_imm" + [(set (match_operand:SI 0 "register_operand" "=Sg,Sg,v") + (truncate:SI + (lshiftrt:DI + (mult:DI + (any_extend:DI + (match_operand:SI 1 "register_operand" "Sg,Sg,v")) + (match_operand:DI 2 "gcn_32bit_immediate_operand" "A, B,A")) + (const_int 32))))] + "TARGET_GCN5 || gcn_inline_immediate_operand (operands[2], SImode)" + "@ + s_mul_hi0\t%0, %1, %2 + s_mul_hi0\t%0, %1, %2 + v_mul_hi0\t%0, %2, %1" + [(set_attr "type" "sop2,sop2,vop3a") + (set_attr "length" "4,8,8") + (set_attr "gcn_version" "gcn5,gcn5,*")]) (define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=v") From patchwork Tue Jun 29 14:50:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julian Brown X-Patchwork-Id: 1498396 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GDnXH1DFFz9s5R for ; Wed, 30 Jun 2021 00:53:03 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B77D53891026 for ; Tue, 29 Jun 2021 14:53:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa1.mentor.iphmx.com (esa1.mentor.iphmx.com [68.232.129.153]) by sourceware.org (Postfix) with ESMTPS id AAF6F388A82B for ; Tue, 29 Jun 2021 14:51:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AAF6F388A82B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=mentor.com IronPort-SDR: i0aBjeW0qNROQscYxQ5vGtOjoZqqUAaFwG1qgJqX/kSbdeshh8kCjK9XG6+J/TYZMOTU5ZgbED 7erQJkmvB6Rb7FD72Ft9ZGu+Rnhloc044j70w+zGpRvXo4wZOBB+FsUWXwfO16CnBOCgiBxXc0 62s4+17t3kS3os04tPQ/p1YYKLvdSgBeTEfCkWvh0Q1hWIXe8A1JXXAYWuLS5tAJ6m/dESyDBe wXWAr4EBuu7qdUiVL6TiTvt+H14a/1kHz9KkQ+9Rq2FYzwq+oG+NdM658Qs/LZDg799MYbtbpr qyw= X-IronPort-AV: E=Sophos;i="5.83,309,1616486400"; d="scan'208";a="65377582" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa1.mentor.iphmx.com with ESMTP; 29 Jun 2021 06:51:00 -0800 IronPort-SDR: J0FeVDyZYlBzucXaU7RZeQu2A1YXNOu5fqlpLsh5Wc5GP6LfPAebJpveqVwO3AvbntFzBVv3xn /UQWLelUlu4TakKYTxJsld9gPyqFb9t8vK/cIK2aKV1h4YnLAqie5ZVyJzTHPWvKjE0q8h383w mND7tZXnmZiu2VnhgZL6W/ByrRxCXqT/LqQbkgHM7W4dGcv52yfT8G1gpqKVhPff89kXG1XNEv C83ZGtlNMx920hfA3rKS5W6qqbMu3jgKG2rg9I7zr2CsXQoUZLVTzu61NK52Gq5Je4qB59xLhN zvg= From: Julian Brown To: Subject: [PATCH 3/3] amdgcn: Add [us]mulsid3/muldi3 patterns Date: Tue, 29 Jun 2021 07:50:40 -0700 Message-ID: <33f23044bbd98b98156c5bc9c501b5bedea9be56.1624977771.git.julian@codesourcery.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) To SVR-IES-MBX-04.mgc.mentorg.com (139.181.222.4) X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Stubbs Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" This patch improves 64-bit multiplication for AMD GCN: patterns for unsigned and signed 32x32->64 bit multiplication have been added, and also 64x64->64 bit multiplication is now open-coded rather than calling a library function (which may be a win for code size as well as speed: the function calling sequence isn't particularly concise for GCN). This version of the patch uses define_insn_and_split in order to keep multiply operations together during RTL optimisations up to register allocation: this appears to produce more compact code via inspection on small test cases than the previous approach using an expander. I will apply shortly. Julian 2021-06-29 Julian Brown gcc/ * config/gcn/gcn.md (mulsidi3, mulsidi3_reg, mulsidi3_imm, muldi3): Add patterns. --- gcc/config/gcn/gcn.md | 94 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index d1d49981ebb..82f7a468bce 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -1457,6 +1457,100 @@ (set_attr "length" "4,8,8") (set_attr "gcn_version" "gcn5,gcn5,*")]) +(define_expand "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (any_extend:DI + (match_operand:SI 1 "register_operand" "")) + (any_extend:DI + (match_operand:SI 2 "nonmemory_operand" ""))))] + "" +{ + if (can_create_pseudo_p () + && !TARGET_GCN5 + && !gcn_inline_immediate_operand (operands[2], SImode)) + operands[2] = force_reg (SImode, operands[2]); + + if (REG_P (operands[2])) + emit_insn (gen_mulsidi3_reg (operands[0], operands[1], operands[2])); + else + emit_insn (gen_mulsidi3_imm (operands[0], operands[1], operands[2])); + + DONE; +}) + +(define_insn_and_split "mulsidi3_reg" + [(set (match_operand:DI 0 "register_operand" "=&Sg, &v") + (mult:DI (any_extend:DI + (match_operand:SI 1 "register_operand" "%Sg, v")) + (any_extend:DI + (match_operand:SI 2 "register_operand" "Sg,vSv"))))] + "" + "#" + "reload_completed" + [(const_int 0)] + { + rtx dstlo = gen_lowpart (SImode, operands[0]); + rtx dsthi = gen_highpart_mode (SImode, DImode, operands[0]); + emit_insn (gen_mulsi3 (dstlo, operands[1], operands[2])); + emit_insn (gen_mulsi3_highpart (dsthi, operands[1], operands[2])); + DONE; + } + [(set_attr "gcn_version" "gcn5,*")]) + +(define_insn_and_split "mulsidi3_imm" + [(set (match_operand:DI 0 "register_operand" "=&Sg,&Sg,&v") + (mult:DI (any_extend:DI + (match_operand:SI 1 "register_operand" "Sg, Sg, v")) + (match_operand:DI 2 "gcn_32bit_immediate_operand" + "A, B, A")))] + "TARGET_GCN5 || gcn_inline_immediate_operand (operands[2], SImode)" + "#" + "&& reload_completed" + [(const_int 0)] + { + rtx dstlo = gen_lowpart (SImode, operands[0]); + rtx dsthi = gen_highpart_mode (SImode, DImode, operands[0]); + emit_insn (gen_mulsi3 (dstlo, operands[1], operands[2])); + emit_insn (gen_mulsi3_highpart (dsthi, operands[1], operands[2])); + DONE; + } + [(set_attr "gcn_version" "gcn5,gcn5,*")]) + +(define_insn_and_split "muldi3" + [(set (match_operand:DI 0 "register_operand" "=&Sg,&Sg, &v,&v") + (mult:DI (match_operand:DI 1 "register_operand" "%Sg, Sg, v, v") + (match_operand:DI 2 "nonmemory_operand" "Sg, i,vSv, A"))) + (clobber (match_scratch:SI 3 "=&Sg,&Sg,&v,&v")) + (clobber (match_scratch:BI 4 "=cs, cs, X, X")) + (clobber (match_scratch:DI 5 "=X, X,cV,cV"))] + "" + "#" + "reload_completed" + [(const_int 0)] + { + rtx tmp = operands[3]; + rtx dsthi = gen_highpart_mode (SImode, DImode, operands[0]); + rtx op1lo = gcn_operand_part (DImode, operands[1], 0); + rtx op1hi = gcn_operand_part (DImode, operands[1], 1); + rtx op2lo = gcn_operand_part (DImode, operands[2], 0); + rtx op2hi = gcn_operand_part (DImode, operands[2], 1); + emit_insn (gen_umulsidi3 (operands[0], op1lo, op2lo)); + emit_insn (gen_mulsi3 (tmp, op1lo, op2hi)); + rtx add = gen_rtx_SET (dsthi, gen_rtx_PLUS (SImode, dsthi, tmp)); + rtx clob1 = gen_rtx_CLOBBER (VOIDmode, operands[4]); + rtx clob2 = gen_rtx_CLOBBER (VOIDmode, operands[5]); + add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, add, clob1, clob2)); + emit_insn (add); + emit_insn (gen_mulsi3 (tmp, op1hi, op2lo)); + add = gen_rtx_SET (dsthi, gen_rtx_PLUS (SImode, dsthi, tmp)); + clob1 = gen_rtx_CLOBBER (VOIDmode, operands[4]); + clob2 = gen_rtx_CLOBBER (VOIDmode, operands[5]); + add = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (3, add, clob1, clob2)); + emit_insn (add); + DONE; + } + [(set_attr "gcn_version" "gcn5,gcn5,*,*")]) + (define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=v") (mult:SI