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[111.241.119.86]) by smtp.gmail.com with ESMTPSA id md10sm1793783pjb.42.2021.06.28.04.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Jun 2021 04:13:52 -0700 (PDT) From: Green Wan To: Cc: bmeng.cn@gmail.com, schwab@linux-m68k.org, david.abdurachmanov@sifive.com, ycliang@andestech.com, rick@andestech.com, Green Wan , Lukasz Majewski , u-boot@lists.denx.de (open list) Subject: [PATCH] drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux' Date: Mon, 28 Jun 2021 19:13:08 +0800 Message-Id: <20210628111308.21325-1-green.wan@sifive.com> X-Mailer: git-send-email 2.17.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Replace 'pciaux' with 'pcieaux', including name string and function prefix. The old name string, 'pciaux', might cause an error if PCIe driver is changed to use clk_get_by_name() with 'pcieaux' to get clock. Signed-off-by: Green Wan Reviewed-by: Leo Yu-Chi Liang --- drivers/clk/sifive/fu740-prci.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c index 9a642c1c99..b025050e22 100644 --- a/drivers/clk/sifive/fu740-prci.c +++ b/drivers/clk/sifive/fu740-prci.c @@ -20,7 +20,7 @@ #include "sifive-prci.h" #include -int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable) +int sifive_prci_fu740_pcieauxclk_enable(struct __prci_clock *pc, bool enable) { struct __prci_wrpll_data *pwd = pc->pwd; struct __prci_data *pd = pc->pd; @@ -98,7 +98,7 @@ static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = { }; static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = { - .enable_clk = sifive_prci_fu740_pciauxclk_enable, + .enable_clk = sifive_prci_fu740_pcieauxclk_enable, }; /* List of clock controls provided by the PRCI */ @@ -150,7 +150,7 @@ struct __prci_clock __prci_init_clocks_fu740[] = { .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops, }, [PRCI_CLK_PCIEAUX] { - .name = "pciaux", + .name = "pcieaux", .parent_name = "", .ops = &sifive_fu740_prci_pcieaux_clk_ops, .pwd = &__prci_pcieaux_data,