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25 Jun 2021 17:57:34 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 01/15] docs: Add device tree bindings for SBI PMU extension Date: Fri, 25 Jun 2021 17:57:07 -0700 Message-Id: <20210626005721.3600114-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175738_721714_60FA932B X-CRM114-Status: GOOD ( 19.69 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: SBI PMU extension requires a firmware to be aware of the event to counter/mhpmevent mappings supported by the hardware. One approach is to encode that information in the device tree. Define a device tree binding that allows a hardware to describe all the PMU mappings required in concise format. Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org SBI PMU extension requires a firmware to be aware of the event to counter/mhpmevent mappings supported by the hardware. One approach is to encode that information in the device tree. Define a device tree binding that allows a hardware to describe all the PMU mappings required in concise format. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- docs/pmu_support.md | 83 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 docs/pmu_support.md diff --git a/docs/pmu_support.md b/docs/pmu_support.md new file mode 100644 index 000000000000..8535a1dccbeb --- /dev/null +++ b/docs/pmu_support.md @@ -0,0 +1,83 @@ +OpenSBI SBI PMU extension support +================================== +SBI PMU extension supports allow supervisor software to configure/start/stop +any performance counter at anytime. Thus, an user can leverage full +capability of performance analysis tools such as perf if SBI PMU extension is +enabled. The OpenSBI implementation makes the following assumptions about the +hardware platform. + + * MCOUNTINHIBIT CSR must be implemented in the hardware. Otherwise, SBI PMU +extension will not be enabled. + + * The platform must provide information about PMU event to counter mapping +via device tree or platform specific hooks. Otherwise, SBI PMU extension will +not be enabled. + + * The platforms should provide information about the PMU event selector values +that should be encoded in the expected value of MHPMEVENTx while configuring +MHPMCOUNTERx for that specific event. This can be done via a device tree or +platform specific hooks. The exact value to be written to he MHPMEVENTx is +completely platform specific. Generic platform writes a default value to +the MHPMEVENTx CSR where is formatted as described below. +``` + xyz[0:19] : event_idx + xyz[20:XLEN] : event_data[0:(XLEN-20)] + +``` + +SBI PMU Device Tree Bindings +---------------------------- + +Platforms may choose to describe PMU event selector and event to counter mapping +values via device tree. The following sections describes the PMU DT node +bindings in details. + +* **compatible** (Mandatory) - The compatible string of SBI PMU device tree node. +This DT property must have the value **riscv,pmu**. + +* **opensbi,event-to-mhpmevent**(Optional) - It represents an ONE-to-ONE mapping +between a PMU event and the event selector value that platform expects to be +written to the MHPMEVENTx CSR for that event. The mapping is encoded in a +table format where each row represents an event. The first column represent the +event idx where the 2nd & 3rd column represent the event selector value that +should be encoded in the expected value to be written in MHPMEVENTx. +This property shouldn't encode any raw hardware event. + +* **opensbi,event-to-counters**(Optional) - It represents a MANY-to-MANY +mapping between a range of events and all the MHPMCOUNTERx in a bitmap format +that can be used to monitor these range of events. The information is encoded in +a table format where each row represent a certain range of events and +corresponding counters. The first column represents starting of the pmu event id +and 2nd column represents the end of the pmu event id. The third column +represent a bitmap of all the MHPMCOUNTERx. This property is mandatory if +event-to-mhpmevent is present. Otherwise, it can be omitted. This property +shouldn't encode any raw event. + +* **opensbi,raw-event-to-counters**(Optional) - It represents an ONE-to-MANY +mapping between a raw event and all the MHPMCOUNTERx in a bitmap format that can +be used to monitor that raw event. The information is encoded in a table format +where each raw represent a specific raw event. The first column stores the +expected event selector value that should be encoded in the expected value to be +written in MHPMEVENTx. The second column stores a bitmap of all the MHPMCOUNTERx +that can be used for monitoring the specified event. + +*Note:* A platform may choose to provide the mapping between event & counters +via platform hooks rather than the device tree. + +### Example + +``` +pmu { + compatible = "riscv,pmu"; + interrupts = <0x100>; + interrupt-parent = <&plic> + opensbi,event-to-mhpmevent = <0x0000B 0x0000 0x0001>, + opensbi,event-to-counters = <0x00001 0x00001 0x00000001>, + <0x00002 0x00002 0x00000004>, + <0x00003 0x0000A 0x00000ff8>, + <0x10000 0x10033 0x000ff000>, + opensbi,raw-event-to-counters = <0x0000 0x0002 0x00000f8>, + <0x0000 0x0003 0x00000ff0>, +}; + +``` From patchwork Sat Jun 26 00:57:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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25 Jun 2021 17:57:36 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 02/15] lib: sbi: Detect mcountinihibit support at runtime Date: Fri, 25 Jun 2021 17:57:08 -0700 Message-Id: <20210626005721.3600114-3-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175739_320787_2F7D3CE2 X-CRM114-Status: GOOD ( 11.38 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: RISC-V ISA specification v1.11 defined mcountinhibit CSR that allows software to stop any counter from incrementing. The SBI PMU extension depends on this CSR support in hardware. Define mcountinhibit as a hart specific feature and detect it at runtime. Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org RISC-V ISA specification v1.11 defined mcountinhibit CSR that allows software to stop any counter from incrementing. The SBI PMU extension depends on this CSR support in hardware. Define mcountinhibit as a hart specific feature and detect it at runtime. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- include/sbi/sbi_hart.h | 4 +++- lib/sbi/sbi_hart.c | 11 +++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 031c7b08a815..9e317c52008c 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -18,8 +18,10 @@ enum sbi_hart_features { SBI_HART_HAS_SCOUNTEREN = (1 << 0), /** Hart has M-mode counter enable */ SBI_HART_HAS_MCOUNTEREN = (1 << 1), + /** Hart has counter inhibit CSR */ + SBI_HART_HAS_MCOUNTINHIBIT = (1 << 2), /** HART has timer csr implementation in hardware */ - SBI_HART_HAS_TIME = (1 << 2), + SBI_HART_HAS_TIME = (1 << 3), /** Last index of Hart features*/ SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME, diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 56878b47624e..0bd1db1ab85e 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -259,6 +259,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature) case SBI_HART_HAS_MCOUNTEREN: fstr = "mcounteren"; break; + case SBI_HART_HAS_MCOUNTINHIBIT: + fstr = "mcountinhibit"; + break; case SBI_HART_HAS_TIME: fstr = "time"; break; @@ -421,6 +424,14 @@ __mhpm_skip: hfeatures->features |= SBI_HART_HAS_MCOUNTEREN; } + /* Detect if hart supports MCOUNTINHIBIT feature */ + val = csr_read_allowed(CSR_MCOUNTINHIBIT, (unsigned long)&trap); + if (!trap.cause) { + csr_write_allowed(CSR_MCOUNTINHIBIT, (unsigned long)&trap, val); + if (!trap.cause) + hfeatures->features |= SBI_HART_HAS_MCOUNTINHIBIT; + } + /* Detect if hart supports time CSR */ csr_read_allowed(CSR_TIME, (unsigned long)&trap); if (!trap.cause) From patchwork Sat Jun 26 00:57:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497518 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; 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Content preview: Reviewed-by: Xiang W Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_hart.c | 2 +- 1 file changed, 1 insertion(+), 1 dele [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Reviewed-by: Xiang W Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_hart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 0bd1db1ab85e..9c01cf75c0bb 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -320,7 +320,7 @@ static unsigned long hart_pmp_get_allowed_addr(void) unsigned long val = 0; struct sbi_trap_info trap = {0}; - csr_write_allowed(CSR_PMPADDR0, (ulong)&trap, PMP_ADDR_MASK); \ + csr_write_allowed(CSR_PMPADDR0, (ulong)&trap, PMP_ADDR_MASK); if (!trap.cause) { val = csr_read_allowed(CSR_PMPADDR0, (ulong)&trap); if (trap.cause) From patchwork Sat Jun 26 00:57:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497519 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=iA0p9rXw; dkim=fail reason="signature verification failed" (2048-bit key; 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The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: RISC-V privilege specification allows the implementation to have less than 64 bits. Add a function to detect the number of implemented bits in mhpmcounter dynamically at runtime. Reviewed-by: Xiang W Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- include/sbi/sbi_hart.h | 1 + lib/sbi/sbi_hart.c | 48 +++++++++++ [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org RISC-V privilege specification allows the implementation to have less than 64 bits. Add a function to detect the number of implemented bits in mhpmcounter dynamically at runtime. Reviewed-by: Xiang W Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- include/sbi/sbi_hart.h | 1 + lib/sbi/sbi_hart.c | 48 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h index 9e317c52008c..0c18ef9325b2 100644 --- a/include/sbi/sbi_hart.h +++ b/include/sbi/sbi_hart.h @@ -44,6 +44,7 @@ void sbi_hart_delegation_dump(struct sbi_scratch *scratch, unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch); unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch); unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch); +unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch); int sbi_hart_pmp_configure(struct sbi_scratch *scratch); bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature); void sbi_hart_get_features_str(struct sbi_scratch *scratch, diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 9c01cf75c0bb..e8cd0421b5e6 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -33,6 +33,7 @@ struct hart_features { unsigned int pmp_addr_bits; unsigned long pmp_gran; unsigned int mhpm_count; + unsigned int mhpm_bits; }; static unsigned long hart_features_offset; @@ -177,6 +178,14 @@ unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch) return hfeatures->pmp_addr_bits; } +unsigned int sbi_hart_mhpm_bits(struct sbi_scratch *scratch) +{ + struct hart_features *hfeatures = + sbi_scratch_offset_ptr(scratch, hart_features_offset); + + return hfeatures->mhpm_bits; +} + int sbi_hart_pmp_configure(struct sbi_scratch *scratch) { struct sbi_domain_memregion *reg; @@ -330,6 +339,37 @@ static unsigned long hart_pmp_get_allowed_addr(void) return val; } +static int hart_pmu_get_allowed_bits(void) +{ + unsigned long val = ~(0UL); + struct sbi_trap_info trap = {0}; + int num_bits = 0; + + /** + * It is assumed that platforms will implement same number of bits for + * all the performance counters including mcycle/minstret. + */ + csr_write_allowed(CSR_MHPMCOUNTER3, (ulong)&trap, val); + if (!trap.cause) { + val = csr_read_allowed(CSR_MHPMCOUNTER3, (ulong)&trap); + if (trap.cause) + return 0; + } + num_bits = __fls(val) + 1; +#if __riscv_xlen == 32 + csr_write_allowed(CSR_MHPMCOUNTER3H, (ulong)&trap, val); + if (!trap.cause) { + val = csr_read_allowed(CSR_MHPMCOUNTER3H, (ulong)&trap); + if (trap.cause) + return num_bits; + } + num_bits += __fls(val) + 1; + +#endif + + return num_bits; +} + static void hart_detect_features(struct sbi_scratch *scratch) { struct sbi_trap_info trap = {0}; @@ -395,9 +435,17 @@ __pmp_skip: /* Detect number of MHPM counters */ __check_csr(CSR_MHPMCOUNTER3, 0, 1UL, mhpm_count, __mhpm_skip); + hfeatures->mhpm_bits = hart_pmu_get_allowed_bits(); + __check_csr_4(CSR_MHPMCOUNTER4, 0, 1UL, mhpm_count, __mhpm_skip); __check_csr_8(CSR_MHPMCOUNTER8, 0, 1UL, mhpm_count, __mhpm_skip); __check_csr_16(CSR_MHPMCOUNTER16, 0, 1UL, mhpm_count, __mhpm_skip); + + /** + * No need to check for MHPMCOUNTERH for RV32 as they are expected to be + * implemented if MHPMCOUNTER is implemented. + */ + __mhpm_skip: #undef __check_csr_64 From patchwork Sat Jun 26 00:57:11 2021 Content-Type: text/plain; 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25 Jun 2021 17:57:41 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 05/15] lib: sbi: Disable m/scounteren & enable mcountinhibit Date: Fri, 25 Jun 2021 17:57:11 -0700 Message-Id: <20210626005721.3600114-6-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175744_171425_BDA3A287 X-CRM114-Status: GOOD ( 12.70 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Currently, all bits in mcountern are enabled unconditionally at boot time. With SBI PMU extension, all the programmable counters should enabled only during performance monitoring for a particular even [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Currently, all bits in mcountern are enabled unconditionally at boot time. With SBI PMU extension, all the programmable counters should enabled only during performance monitoring for a particular event. However, this is done only if mcountinhibit is implemented because the supervisor mode can not start/stop any event without mcountinhibit. Similarly, supervisor should take care enabling scounteren which allows U-mode to access programmable pmu counters. All the non-programmable ones (CY, TM, IR) should be enabled in M-mode because some userspace may rely on builtins such as __builtin_readcyclecounter. Supervisor OS can still disable them during initial configuration. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_hart.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index e8cd0421b5e6..6254452e11bb 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -51,12 +51,29 @@ static void mstatus_init(struct sbi_scratch *scratch) csr_write(CSR_MSTATUS, mstatus_val); - /* Enable user/supervisor use of perf counters */ + /* Disable user mode usage of all perf counters except default ones (CY, TM, IR) */ if (misa_extension('S') && sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN)) - csr_write(CSR_SCOUNTEREN, -1); - if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTEREN)) - csr_write(CSR_MCOUNTEREN, -1); + csr_write(CSR_SCOUNTEREN, 7); + + if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTEREN)) { + if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT)) + /** + * Just enable the default counters (CY, TM, IR) because + * some OS (e.g FreeBSD) expect them to be enabled. + * + * All other counters will be enabled at runtime after + * S-mode request. + */ + csr_write(CSR_MCOUNTEREN, 7); + else + /* Supervisor mode usage are enabled by default */ + csr_write(CSR_MCOUNTEREN, -1); + } + + /* All programmable counters will start running at runtime after S-mode request */ + if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT)) + csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8); /* Disable all interrupts */ csr_write(CSR_MIE, 0); From patchwork Sat Jun 26 00:57:12 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=W1HrvGAb; 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Reviewed-by: Anup Patel Reviewed-by: Xiang W Signed-off-by: Atish Patra --- include/sbi/sbi_list.h | 11 +++++++++++ 1 file changed, 11 inser [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Implement a list helper function that checks for empty lists. Reviewed-by: Anup Patel Reviewed-by: Xiang W Signed-off-by: Atish Patra --- include/sbi/sbi_list.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/sbi/sbi_list.h b/include/sbi/sbi_list.h index 1174ad274c54..b1178dfc9b8e 100644 --- a/include/sbi/sbi_list.h +++ b/include/sbi/sbi_list.h @@ -43,6 +43,17 @@ static inline void __sbi_list_add(struct sbi_dlist *new, next->prev = new; } +/** + * Checks if the list is empty or not. + * @param head List head + * + * Retruns TRUE if list is empty, FALSE otherwise. + */ +static inline bool sbi_list_empty(struct sbi_dlist *head) +{ + return head->next == head; +} + /** * Adds the new node after the given head. * @param new New node that needs to be added to list. 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25 Jun 2021 17:57:45 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 07/15] lib: sbi: Remove redundant boot time print statement Date: Fri, 25 Jun 2021 17:57:13 -0700 Message-Id: <20210626005721.3600114-8-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175746_322945_F7EA4EB8 X-CRM114-Status: UNSURE ( 7.94 ) X-CRM114-Notice: Please train this message. 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Content preview: Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_init.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index e396d95d424c..30747776f3bf 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -137,8 +137,6 @@ static void sbi_boot_print_hart(struc [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_init.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index e396d95d424c..30747776f3bf 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -137,8 +137,6 @@ static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid) sbi_hart_pmp_addrbits(scratch)); sbi_printf("Boot HART MHPM Count : %d\n", sbi_hart_mhpm_count(scratch)); - sbi_printf("Boot HART MHPM Count : %d\n", - sbi_hart_mhpm_count(scratch)); sbi_hart_delegation_dump(scratch, "Boot HART ", " "); } From patchwork Sat Jun 26 00:57:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497524 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=tb+obvrU; dkim=fail reason="signature verification failed" (2048-bit key; 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25 Jun 2021 17:36:20 -0700 IronPort-SDR: feFhC7YZlfHFH4gwHG+xOc1eILPvNBE1JEwwtsFqjLuktNxxQTwGDIqAK8I9gR9qlC+Pm4glPo A1lueW/0U3IhNX4P0Tzjxj56z89dHY6oRgwQM6D1gJ2hMEppIm1xBMrhUehJpa3zeKkExnx1x8 fxoAuDrvNa24W6NOeF7C51dg/72pKi31Z9Bl6R2MzNLdFnGeX/1Zuu8E5odz8CWVX43YhSxB/T bwdBIPhjW15TKweA8tBDEqgREQRcFH3g+BXAgumHes/Kmb1h5SSofHBvSAwAp2sjQg5HrZqOz5 7Pw= WDCIronportException: Internal Received: from unknown (HELO jedi-01.wdc.com) ([10.225.163.19]) by uls-op-cesaip02.wdc.com with ESMTP; 25 Jun 2021 17:57:47 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel , Xiang W Subject: [PATCH v3 08/15] lib: sbi: Use csr_read/write_num to read/update PMU counters Date: Fri, 25 Jun 2021 17:57:14 -0700 Message-Id: <20210626005721.3600114-9-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175748_263401_6C51FBC1 X-CRM114-Status: UNSURE ( 8.08 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel Reviewed-by: Xiang W Signed-off-by: Atish Patra --- lib/sbi/riscv_asm.c | 35 +++++++++++++++++++++++++++++++++++ 1 f [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Currently, csr_read/write_num functions are used to read/write PMP related CSRs where CSR value is decided at runtime. Expand this function to include PMU related CSRs as well. Reviewed-by: Anup Patel Reviewed-by: Xiang W Signed-off-by: Atish Patra --- lib/sbi/riscv_asm.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/lib/sbi/riscv_asm.c b/lib/sbi/riscv_asm.c index 8c54c11147e7..4c24a5132195 100644 --- a/lib/sbi/riscv_asm.c +++ b/lib/sbi/riscv_asm.c @@ -118,6 +118,21 @@ unsigned long csr_read_num(int csr_num) switch (csr_num) { switchcase_csr_read_16(CSR_PMPCFG0, ret) switchcase_csr_read_64(CSR_PMPADDR0, ret) + switchcase_csr_read(CSR_MCYCLE, ret) + switchcase_csr_read(CSR_MINSTRET, ret) + switchcase_csr_read(CSR_MHPMCOUNTER3, ret) + switchcase_csr_read_4(CSR_MHPMCOUNTER4, ret) + switchcase_csr_read_8(CSR_MHPMCOUNTER8, ret) + switchcase_csr_read_16(CSR_MHPMCOUNTER16, ret) +#if __riscv_xlen == 32 + switchcase_csr_read(CSR_MCYCLEH, ret) + switchcase_csr_read(CSR_MINSTRETH, ret) + switchcase_csr_read(CSR_MHPMCOUNTER3H, ret) + switchcase_csr_read_4(CSR_MHPMCOUNTER4H, ret) + switchcase_csr_read_8(CSR_MHPMCOUNTER8H, ret) + switchcase_csr_read_16(CSR_MHPMCOUNTER16H, ret) +#endif + default: break; }; @@ -161,6 +176,26 @@ void csr_write_num(int csr_num, unsigned long val) switch (csr_num) { switchcase_csr_write_16(CSR_PMPCFG0, val) switchcase_csr_write_64(CSR_PMPADDR0, val) + switchcase_csr_write(CSR_MCYCLE, val) + switchcase_csr_write(CSR_MINSTRET, val) + switchcase_csr_write(CSR_MHPMCOUNTER3, val) + switchcase_csr_write_4(CSR_MHPMCOUNTER4, val) + switchcase_csr_write_8(CSR_MHPMCOUNTER8, val) + switchcase_csr_write_16(CSR_MHPMCOUNTER16, val) +#if __riscv_xlen == 32 + switchcase_csr_write(CSR_MCYCLEH, val) + switchcase_csr_write(CSR_MINSTRETH, val) + switchcase_csr_write(CSR_MHPMCOUNTER3H, val) + switchcase_csr_write_4(CSR_MHPMCOUNTER4H, val) + switchcase_csr_write_8(CSR_MHPMCOUNTER8H, val) + switchcase_csr_write_16(CSR_MHPMCOUNTER16H, val) +#endif + switchcase_csr_write(CSR_MCOUNTINHIBIT, val) + switchcase_csr_write(CSR_MHPMEVENT3, val) + switchcase_csr_write_4(CSR_MHPMEVENT4, val) + switchcase_csr_write_8(CSR_MHPMEVENT8, val) + switchcase_csr_write_16(CSR_MHPMEVENT16, val) + default: break; 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25 Jun 2021 17:57:49 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 09/15] lib: sbi: Add PMU specific platform hooks Date: Fri, 25 Jun 2021 17:57:15 -0700 Message-Id: <20210626005721.3600114-10-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175749_862462_39F84C0C X-CRM114-Status: GOOD ( 13.11 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: A platform hook to initialize PMU allows platform vendors to provide their own mechanism to define pmu event-counter mappings in addition to the DT based approach. Another platform hook that allows platform vendors customize the final mhpmevent value configuration. Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org A platform hook to initialize PMU allows platform vendors to provide their own mechanism to define pmu event-counter mappings in addition to the DT based approach. Another platform hook that allows platform vendors customize the final mhpmevent value configuration. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- include/sbi/sbi_platform.h | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h index f8074d28db65..4d192f2a0ec5 100644 --- a/include/sbi/sbi_platform.h +++ b/include/sbi/sbi_platform.h @@ -89,6 +89,12 @@ struct sbi_platform_operations { /** Initialize (or populate) domains for the platform */ int (*domains_init)(void); + /** Initialize hw performance counters */ + int (*pmu_init)(void); + + /** Get platform specific mhpmevent value */ + uint64_t (*pmu_xlate_to_mhpmevent)(uint32_t event_idx, uint64_t data); + /** Initialize the platform console */ int (*console_init)(void); @@ -391,6 +397,39 @@ static inline int sbi_platform_domains_init(const struct sbi_platform *plat) return 0; } +/** + * Setup hw PMU events for the platform + * + * @param plat pointer to struct sbi_platform + * + * @return 0 on success and negative error code on failure + */ +static inline int sbi_platform_pmu_init(const struct sbi_platform *plat) +{ + if (plat && sbi_platform_ops(plat)->pmu_init) + return sbi_platform_ops(plat)->pmu_init(); + return 0; +} + +/** + * Get the value to be written in mhpmeventx for event_idx + * + * @param plat pointer to struct sbi_platform + * @param event_idx ID of the PMU event + * @param data Additional configuration data passed from supervisor software + * + * @return expected value by the platform or 0 if platform doesn't know about + * the event + */ +static inline uint64_t sbi_platform_pmu_xlate_to_mhpmevent(const struct sbi_platform *plat, + uint32_t event_idx, uint64_t data) +{ + if (plat && sbi_platform_ops(plat)->pmu_xlate_to_mhpmevent) + return sbi_platform_ops(plat)->pmu_xlate_to_mhpmevent(event_idx, + data); + return 0; +} + /** * Initialize the platform console * From patchwork Sat Jun 26 00:57:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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25 Jun 2021 17:57:50 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , anup.patel@wdc.com Subject: [PATCH v3 10/15] lib: sbi: Add PMU support Date: Fri, 25 Jun 2021 17:57:16 -0700 Message-Id: <20210626005721.3600114-11-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175751_891827_5AA6CC8D X-CRM114-Status: GOOD ( 27.39 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: RISC-V SBI v0.3 specification defined a PMU extension to configure/start/stop the hardware/firmware pmu events. Implement PMU support in OpenSBI library. The implementation is agnostic of event to counter mapping & mhpmevent value configuration. That means, it expects platform hooks will be used to set up the m [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org RISC-V SBI v0.3 specification defined a PMU extension to configure/start/stop the hardware/firmware pmu events. Implement PMU support in OpenSBI library. The implementation is agnostic of event to counter mapping & mhpmevent value configuration. That means, it expects platform hooks will be used to set up the mapping and provide the mhpmevent value at runtime. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/sbi_ecall_interface.h | 138 ++++++- include/sbi/sbi_error.h | 2 + include/sbi/sbi_pmu.h | 73 ++++ lib/sbi/objects.mk | 1 + lib/sbi/sbi_init.c | 9 + lib/sbi/sbi_pmu.c | 620 ++++++++++++++++++++++++++++++ 6 files changed, 842 insertions(+), 1 deletion(-) create mode 100644 include/sbi/sbi_pmu.h create mode 100644 lib/sbi/sbi_pmu.c diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h index 559a33e7ced0..70a3bf7abfae 100644 --- a/include/sbi/sbi_ecall_interface.h +++ b/include/sbi/sbi_ecall_interface.h @@ -28,6 +28,7 @@ #define SBI_EXT_RFENCE 0x52464E43 #define SBI_EXT_HSM 0x48534D #define SBI_EXT_SRST 0x53525354 +#define SBI_EXT_PMU 0x504D55 /* SBI function IDs for BASE extension*/ #define SBI_EXT_BASE_GET_SPEC_VERSION 0x0 @@ -91,6 +92,139 @@ #define SBI_SRST_RESET_REASON_NONE 0x0 #define SBI_SRST_RESET_REASON_SYSFAIL 0x1 +/* SBI function IDs for PMU extension */ +#define SBI_EXT_PMU_NUM_COUNTERS 0x0 +#define SBI_EXT_PMU_COUNTER_GET_INFO 0x1 +#define SBI_EXT_PMU_COUNTER_CFG_MATCH 0x2 +#define SBI_EXT_PMU_COUNTER_START 0x3 +#define SBI_EXT_PMU_COUNTER_STOP 0x4 +#define SBI_EXT_PMU_COUNTER_FW_READ 0x5 + +/** General pmu event codes specified in SBI PMU extension */ +enum sbi_pmu_hw_generic_events_t { + SBI_PMU_HW_NO_EVENT = 0, + SBI_PMU_HW_CPU_CYCLES = 1, + SBI_PMU_HW_INSTRUCTIONS = 2, + SBI_PMU_HW_CACHE_REFERENCES = 3, + SBI_PMU_HW_CACHE_MISSES = 4, + SBI_PMU_HW_BRANCH_INSTRUCTIONS = 5, + SBI_PMU_HW_BRANCH_MISSES = 6, + SBI_PMU_HW_BUS_CYCLES = 7, + SBI_PMU_HW_STALLED_CYCLES_FRONTEND = 8, + SBI_PMU_HW_STALLED_CYCLES_BACKEND = 9, + SBI_PMU_HW_REF_CPU_CYCLES = 10, + + SBI_PMU_HW_GENERAL_MAX, +}; + +/** + * Generalized hardware cache events: + * + * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x + * { read, write, prefetch } x + * { accesses, misses } + */ +enum sbi_pmu_hw_cache_id { + SBI_PMU_HW_CACHE_L1D = 0, + SBI_PMU_HW_CACHE_L1I = 1, + SBI_PMU_HW_CACHE_LL = 2, + SBI_PMU_HW_CACHE_DTLB = 3, + SBI_PMU_HW_CACHE_ITLB = 4, + SBI_PMU_HW_CACHE_BPU = 5, + SBI_PMU_HW_CACHE_NODE = 6, + + SBI_PMU_HW_CACHE_MAX, +}; + +enum sbi_pmu_hw_cache_op_id { + SBI_PMU_HW_CACHE_OP_READ = 0, + SBI_PMU_HW_CACHE_OP_WRITE = 1, + SBI_PMU_HW_CACHE_OP_PREFETCH = 2, + + SBI_PMU_HW_CACHE_OP_MAX, +}; + +enum sbi_pmu_hw_cache_op_result_id { + SBI_PMU_HW_CACHE_RESULT_ACCESS = 0, + SBI_PMU_HW_CACHE_RESULT_MISS = 1, + + SBI_PMU_HW_CACHE_RESULT_MAX, +}; + +/** + * Special "firmware" events provided by the OpenSBI, even if the hardware + * does not support performance events. These events are encoded as a raw + * event type in Linux kernel perf framework. + */ +enum sbi_pmu_fw_event_code_id { + SBI_PMU_FW_MISALIGNED_LOAD = 0, + SBI_PMU_FW_MISALIGNED_STORE = 1, + SBI_PMU_FW_ACCESS_LOAD = 2, + SBI_PMU_FW_ACCESS_STORE = 3, + SBI_PMU_FW_ILLEGAL_INSN = 4, + SBI_PMU_FW_SET_TIMER = 5, + SBI_PMU_FW_IPI_SENT = 6, + SBI_PMU_FW_IPI_RECVD = 7, + SBI_PMU_FW_FENCE_I_SENT = 8, + SBI_PMU_FW_FENCE_I_RECVD = 9, + SBI_PMU_FW_SFENCE_VMA_SENT = 10, + SBI_PMU_FW_SFENCE_VMA_RCVD = 11, + SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12, + SBI_PMU_FW_SFENCE_VMA_ASID_RCVD = 13, + + SBI_PMU_FW_HFENCE_GVMA_SENT = 14, + SBI_PMU_FW_HFENCE_GVMA_RCVD = 15, + SBI_PMU_FW_HFENCE_GVMA_VMID_SENT = 16, + SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD = 17, + + SBI_PMU_FW_HFENCE_VVMA_SENT = 18, + SBI_PMU_FW_HFENCE_VVMA_RCVD = 19, + SBI_PMU_FW_HFENCE_VVMA_ASID_SENT = 20, + SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD = 21, + SBI_PMU_FW_MAX, +}; + +/** SBI PMU event idx type */ +enum sbi_pmu_event_type_id { + SBI_PMU_EVENT_TYPE_HW = 0x0, + SBI_PMU_EVENT_TYPE_HW_CACHE = 0x1, + SBI_PMU_EVENT_TYPE_HW_RAW = 0x2, + SBI_PMU_EVENT_TYPE_FW = 0xf, + SBI_PMU_EVENT_TYPE_MAX, +}; + +/** SBI PMU counter type */ +enum sbi_pmu_ctr_type { + SBI_PMU_CTR_TYPE_HW = 0, + SBI_PMU_CTR_TYPE_FW, +}; + +/* Helper macros to decode event idx */ +#define SBI_PMU_EVENT_IDX_OFFSET 20 +#define SBI_PMU_EVENT_IDX_MASK 0xFFFFF +#define SBI_PMU_EVENT_IDX_CODE_MASK 0xFFFF +#define SBI_PMU_EVENT_IDX_TYPE_MASK 0xF0000 +#define SBI_PMU_EVENT_RAW_IDX 0x20000 + +#define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF + +/* Flags defined for config matching function */ +#define SBI_PMU_CFG_FLAG_SKIP_MATCH (1 << 0) +#define SBI_PMU_CFG_FLAG_CLEAR_VALUE (1 << 1) +#define SBI_PMU_CFG_FLAG_AUTO_START (1 << 2) +#define SBI_PMU_CFG_FLAG_SET_VUINH (1 << 3) +#define SBI_PMU_CFG_FLAG_SET_VSINH (1 << 4) +#define SBI_PMU_CFG_FLAG_SET_UINH (1 << 5) +#define SBI_PMU_CFG_FLAG_SET_SINH (1 << 6) +#define SBI_PMU_CFG_FLAG_SET_MINH (1 << 7) + +/* Flags defined for counter start function */ +#define SBI_PMU_START_FLAG_SET_INIT_VALUE (1 << 0) + +/* Flags defined for counter stop function */ +#define SBI_PMU_STOP_FLAG_RESET (1 << 0) + +/* SBI base specification related macros */ #define SBI_SPEC_VERSION_MAJOR_OFFSET 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f #define SBI_SPEC_VERSION_MINOR_MASK 0xffffff @@ -107,8 +241,10 @@ #define SBI_ERR_DENIED -4 #define SBI_ERR_INVALID_ADDRESS -5 #define SBI_ERR_ALREADY_AVAILABLE -6 +#define SBI_ERR_ALREADY_STARTED -7 +#define SBI_ERR_ALREADY_STOPPED -8 -#define SBI_LAST_ERR SBI_ERR_ALREADY_AVAILABLE +#define SBI_LAST_ERR SBI_ERR_ALREADY_STOPPED /* clang-format on */ diff --git a/include/sbi/sbi_error.h b/include/sbi/sbi_error.h index 3655d122006b..dd65e14b6fcd 100644 --- a/include/sbi/sbi_error.h +++ b/include/sbi/sbi_error.h @@ -21,6 +21,8 @@ #define SBI_EDENIED SBI_ERR_DENIED #define SBI_EINVALID_ADDR SBI_ERR_INVALID_ADDRESS #define SBI_EALREADY SBI_ERR_ALREADY_AVAILABLE +#define SBI_EALREADY_STARTED SBI_ERR_ALREADY_STARTED +#define SBI_EALREADY_STOPPED SBI_ERR_ALREADY_STOPPED #define SBI_ENODEV -1000 #define SBI_ENOSYS -1001 diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h new file mode 100644 index 000000000000..b3010cc5c1ce --- /dev/null +++ b/include/sbi/sbi_pmu.h @@ -0,0 +1,73 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __SBI_PMU_H__ +#define __SBI_PMU_H__ + +#include +#include +#include +#include + +/* Event related macros */ +/* Maximum number of hardware events that can mapped by OpenSBI */ +#define SBI_PMU_HW_EVENT_MAX 64 + +/* Maximum number of firmware events that can mapped by OpenSBI */ +#define SBI_PMU_FW_EVENT_MAX 32 + +/* Counter related macros */ +#define SBI_PMU_FW_CTR_MAX 16 +#define SBI_PMU_HW_CTR_MAX 32 +#define SBI_PMU_CTR_MAX (SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX) + +/** Initialize PMU */ +int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot); + +/** Reset PMU during hart exit */ +void sbi_pmu_exit(struct sbi_scratch *scratch); + +/** + * Add the hardware event to counter mapping information. This should be called + * from the platform code to update the mapping table. + * @param eidx_start Start of the event idx range for supported counters + * @param eidx_end End of the event idx range for supported counters + * @param cmap A bitmap representing counters supporting the event range + * @return 0 on success, error otherwise. + */ +int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap); + +/** + * Add the raw hardware event selector and supported counter information. This + * should be called from the platform code to update the mapping table. + * @param info a pointer to the hardware event info + * @return 0 on success, error otherwise. + */ + +int sbi_pmu_add_raw_event_counter_map(uint64_t select, u32 cmap); + +int sbi_pmu_ctr_read(uint32_t cidx, unsigned long *cval); + +int sbi_pmu_ctr_stop(unsigned long cidx_base, unsigned long cidx_mask, + unsigned long flag); + +int sbi_pmu_ctr_start(unsigned long cidx_base, unsigned long cidx_mask, + unsigned long flags, uint64_t ival); + +int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info); + +unsigned long sbi_pmu_num_ctr(void); + +int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, + unsigned long flags, unsigned long event_idx, + uint64_t event_data); + +int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id); + +#endif diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk index 6f2c06f5b501..d9068b707854 100644 --- a/lib/sbi/objects.mk +++ b/lib/sbi/objects.mk @@ -33,6 +33,7 @@ libsbi-objs-y += sbi_init.o libsbi-objs-y += sbi_ipi.o libsbi-objs-y += sbi_misaligned_ldst.o libsbi-objs-y += sbi_platform.o +libsbi-objs-y += sbi_pmu.o libsbi-objs-y += sbi_scratch.o libsbi-objs-y += sbi_string.o libsbi-objs-y += sbi_system.o diff --git a/lib/sbi/sbi_init.c b/lib/sbi/sbi_init.c index 30747776f3bf..89b66e852e1d 100644 --- a/lib/sbi/sbi_init.c +++ b/lib/sbi/sbi_init.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -251,6 +252,8 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid) if (rc) sbi_hart_hang(); + sbi_pmu_init(scratch, TRUE); + sbi_boot_print_banner(scratch); rc = sbi_platform_irqchip_init(plat, TRUE); @@ -352,6 +355,8 @@ static void init_warm_startup(struct sbi_scratch *scratch, u32 hartid) if (rc) sbi_hart_hang(); + sbi_pmu_init(scratch, FALSE); + rc = sbi_platform_irqchip_init(plat, FALSE); if (rc) sbi_hart_hang(); @@ -392,6 +397,8 @@ static void init_warm_resume(struct sbi_scratch *scratch) if (rc) sbi_hart_hang(); + sbi_pmu_init(scratch, FALSE); + rc = sbi_hart_pmp_configure(scratch); if (rc) sbi_hart_hang(); @@ -515,6 +522,8 @@ void __noreturn sbi_exit(struct sbi_scratch *scratch) sbi_platform_early_exit(plat); + sbi_pmu_exit(scratch); + sbi_timer_exit(scratch); sbi_ipi_exit(scratch); diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c new file mode 100644 index 000000000000..d9c74c0b0f26 --- /dev/null +++ b/lib/sbi/sbi_pmu.c @@ -0,0 +1,620 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** Information about hardware counters */ +struct sbi_pmu_hw_event { + unsigned long counters; + unsigned long start_idx; + unsigned long end_idx; + /* Event selector value used only for raw events */ + uint64_t select; +}; + +/** Representation of a firmware event */ +struct sbi_pmu_fw_event { + + /* Event associated with the particular counter */ + unsigned long event_idx; + + /* Current value of the counter */ + unsigned long curr_count; + + /* A flag indicating pmu event monitoring is started */ + bool bStarted; +}; + +/* Information about PMU counters as per SBI specification */ +union sbi_pmu_ctr_info { + unsigned long value; + struct { + unsigned long csr:12; + unsigned long width:6; +#if __riscv_xlen == 32 + unsigned long reserved:13; +#else + unsigned long reserved:45; +#endif + unsigned long type:1; + }; +}; + +/* Mapping between event range and possible counters */ +static struct sbi_pmu_hw_event hw_event_map[SBI_PMU_HW_EVENT_MAX] = {0}; + +/* counter to enabled event mapping */ +static uint32_t active_events[SBI_HARTMASK_MAX_BITS][SBI_PMU_HW_CTR_MAX + SBI_PMU_FW_CTR_MAX]; + +/* Contains all the information about firmwares events */ +static struct sbi_pmu_fw_event fw_event_map[SBI_HARTMASK_MAX_BITS][SBI_PMU_FW_EVENT_MAX] = {0}; + +/* Maximum number of hardware events available */ +static uint32_t num_hw_events; +/* Maximum number of hardware counters available */ +static uint32_t num_hw_ctrs; + +/* Maximum number of counters available */ +static uint32_t total_ctrs; + +/* Helper macros to retrieve event idx and code type */ +#define get_cidx_type(x) ((x & SBI_PMU_EVENT_IDX_TYPE_MASK) >> 16) +#define get_cidx_code(x) (x & SBI_PMU_EVENT_IDX_CODE_MASK) + +/** + * Perform a sanity check on event & counter mappings with event range overlap check + * @param evtA Pointer to the existing hw event structure + * @param evtB Pointer to the new hw event structure + * + * Return FALSE if the range doesn't overlap, TRUE otherwise + */ +static bool pmu_event_range_overlap(struct sbi_pmu_hw_event *evtA, + struct sbi_pmu_hw_event *evtB) +{ + /* check if the range of events overlap with a previous entry */ + if (((evtA->end_idx < evtB->start_idx) && (evtA->end_idx < evtB->end_idx)) || + ((evtA->start_idx > evtB->start_idx) && (evtA->start_idx > evtB->end_idx))) + return FALSE; + return TRUE; +} + +static bool pmu_event_select_overlap(struct sbi_pmu_hw_event *evt, + uint64_t select_val) +{ + if (evt->select == select_val) + return TRUE; + + return FALSE; +} + +static int pmu_ctr_validate(uint32_t cidx, uint32_t *event_idx_code) +{ + uint32_t event_idx_val; + uint32_t event_idx_type; + u32 hartid = current_hartid(); + + event_idx_val = active_events[hartid][cidx]; + + if (cidx >= total_ctrs || (event_idx_val == SBI_PMU_EVENT_IDX_INVALID)) + return SBI_EINVAL; + + event_idx_type = get_cidx_type(event_idx_val); + if (event_idx_type >= SBI_PMU_EVENT_TYPE_MAX) + return SBI_EINVAL; + + *event_idx_code = get_cidx_code(event_idx_val); + + return event_idx_type; +} + +static int pmu_ctr_read_fw(uint32_t cidx, unsigned long *cval, + uint32_t fw_evt_code) +{ + u32 hartid = current_hartid(); + struct sbi_pmu_fw_event fevent; + + fevent = fw_event_map[hartid][fw_evt_code]; + *cval = fevent.curr_count; + + return 0; +} + +/* Add a hardware counter read for completeness for future purpose */ +static int pmu_ctr_read_hw(uint32_t cidx, uint64_t *cval) +{ + /* Check for invalid hw counter read requests */ + if (unlikely(cidx == 1)) + return SBI_EINVAL; +#if __riscv_xlen == 32 + uint32_t temp, temph = 0; + + temp = csr_read_num(CSR_MCYCLE + cidx); + temph = csr_read_num(CSR_MCYCLEH + cidx); + *cval = ((uint64_t)temph << 32) | temp; +#else + *cval = csr_read_num(CSR_MCYCLE + cidx); +#endif + + return 0; +} + +int sbi_pmu_ctr_read(uint32_t cidx, unsigned long *cval) +{ + int event_idx_type; + uint32_t event_code; + uint64_t cval64; + + event_idx_type = pmu_ctr_validate(cidx, &event_code); + if (event_idx_type < 0) + return SBI_EINVAL; + else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) + pmu_ctr_read_fw(cidx, cval, event_code); + else + pmu_ctr_read_hw(cidx, &cval64); + + return 0; +} + +static int pmu_add_hw_event_map(u32 eidx_start, u32 eidx_end, u32 cmap, + uint64_t select) +{ + int i = 0; + bool is_overlap; + struct sbi_pmu_hw_event *event = &hw_event_map[num_hw_events]; + + /* The first two counters are reserved by priv spec */ + if ((eidx_start == SBI_PMU_HW_CPU_CYCLES && cmap != 0x1) || + (eidx_start == SBI_PMU_HW_INSTRUCTIONS && cmap != 0x4) || + (eidx_start > SBI_PMU_HW_INSTRUCTIONS && (cmap & 0x07))) + return SBI_EDENIED; + + if (num_hw_events >= SBI_PMU_HW_EVENT_MAX - 1) { + sbi_printf("Can not handle more than %d perf events\n", + SBI_PMU_HW_EVENT_MAX); + return SBI_EFAIL; + } + + event->start_idx = eidx_start; + event->end_idx = eidx_end; + event->counters = cmap; + event->select = select; + + /* Sanity check */ + for (i = 0; i < num_hw_events; i++) { + if (eidx_start == SBI_PMU_EVENT_RAW_IDX) + /* All raw events have same event idx. Just do sanity check on select */ + is_overlap = pmu_event_select_overlap(&hw_event_map[i], select); + else + is_overlap = pmu_event_range_overlap(&hw_event_map[i], event); + if (is_overlap) + return SBI_EINVALID_ADDR; + } + num_hw_events++; + + return 0; +} + +/** + * Logical counter ids are assigned to hardware counters are assigned consecutively. + * E.g. counter0 must count MCYCLE where counter2 must count minstret. Similarly, + * counterX will mhpmcounterX. + */ +int sbi_pmu_add_hw_event_counter_map(u32 eidx_start, u32 eidx_end, u32 cmap) +{ + if ((eidx_start > eidx_end) || eidx_start == SBI_PMU_EVENT_RAW_IDX || + eidx_end == SBI_PMU_EVENT_RAW_IDX) + return SBI_EINVAL; + + return pmu_add_hw_event_map(eidx_start, eidx_end, cmap, 0); +} + +int sbi_pmu_add_raw_event_counter_map(uint64_t select, u32 cmap) +{ + return pmu_add_hw_event_map(SBI_PMU_EVENT_RAW_IDX, + SBI_PMU_EVENT_RAW_IDX, cmap, select); +} + +static void pmu_ctr_write_hw(uint32_t cidx, uint64_t ival) +{ +#if __riscv_xlen == 32 + csr_write_num(CSR_MCYCLE + cidx, 0); + csr_write_num(CSR_MCYCLE + cidx, ival & 0xFFFF); + csr_write_num(CSR_MCYCLEH + cidx, ival >> BITS_PER_LONG); +#else + csr_write_num(CSR_MCYCLE + cidx, ival); +#endif +} + +static int pmu_ctr_start_hw(uint32_t cidx, uint64_t ival, bool ival_update) +{ + unsigned long mctr_en = csr_read(CSR_MCOUNTEREN); + unsigned long mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT); + + /* Make sure the counter index lies within the range and is not TM bit */ + if (cidx > num_hw_ctrs || cidx == 1) + return SBI_EINVAL; + + if (__test_bit(cidx, &mctr_en) && !__test_bit(cidx, &mctr_inhbt)) + return SBI_EALREADY_STARTED; + + __set_bit(cidx, &mctr_en); + __clear_bit(cidx, &mctr_inhbt); + + if (ival_update) + pmu_ctr_write_hw(cidx, ival); + + csr_write(CSR_MCOUNTEREN, mctr_en); + csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt); + + return 0; +} + +static int pmu_ctr_start_fw(uint32_t cidx, uint32_t fw_evt_code, + uint64_t ival, bool ival_update) +{ + u32 hartid = current_hartid(); + struct sbi_pmu_fw_event *fevent; + + fevent = &fw_event_map[hartid][fw_evt_code]; + if (ival_update) + fevent->curr_count = ival; + fevent->bStarted = TRUE; + + return 0; +} + +int sbi_pmu_ctr_start(unsigned long cbase, unsigned long cmask, + unsigned long flags, uint64_t ival) +{ + int event_idx_type; + uint32_t event_code; + unsigned long ctr_mask = cmask << cbase; + int ret = SBI_EINVAL; + bool bUpdate = FALSE; + + if (__fls(ctr_mask) >= total_ctrs) + return ret; + + if (flags & SBI_PMU_START_FLAG_SET_INIT_VALUE) + bUpdate = TRUE; + + for_each_set_bit_from(cbase, &ctr_mask, total_ctrs) { + event_idx_type = pmu_ctr_validate(cbase, &event_code); + if (event_idx_type < 0) + /* Continue the start operation for other counters */ + continue; + else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) + ret = pmu_ctr_start_fw(cbase, event_code, ival, bUpdate); + else + ret = pmu_ctr_start_hw(cbase, ival, bUpdate); + } + + return ret; +} + +static int pmu_ctr_stop_hw(uint32_t cidx) +{ + unsigned long mctr_en = csr_read(CSR_MCOUNTEREN); + unsigned long mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT); + + /* Make sure the counter index lies within the range and is not TM bit */ + if (cidx > num_hw_ctrs || cidx == 1) + return SBI_EINVAL; + + if (__test_bit(cidx, &mctr_en) && !__test_bit(cidx, &mctr_inhbt)) { + __set_bit(cidx, &mctr_inhbt); + __clear_bit(cidx, &mctr_en); + csr_write(CSR_MCOUNTEREN, mctr_en); + csr_write(CSR_MCOUNTINHIBIT, mctr_inhbt); + return 0; + } else + return SBI_EALREADY_STOPPED; +} + +static int pmu_ctr_stop_fw(uint32_t cidx, uint32_t fw_evt_code) +{ + u32 hartid = current_hartid(); + + fw_event_map[hartid][fw_evt_code].bStarted = FALSE; + + return 0; +} + +int sbi_pmu_ctr_stop(unsigned long cbase, unsigned long cmask, + unsigned long flag) +{ + u32 hartid = current_hartid(); + int ret = SBI_EINVAL; + int event_idx_type; + uint32_t event_code; + unsigned long ctr_mask = cmask << cbase; + + if (__fls(ctr_mask) >= total_ctrs) + return SBI_EINVAL; + + for_each_set_bit_from(cbase, &ctr_mask, total_ctrs) { + event_idx_type = pmu_ctr_validate(cbase, &event_code); + if (event_idx_type < 0) + /* Continue the stop operation for other counters */ + continue; + + else if (event_idx_type == SBI_PMU_EVENT_TYPE_FW) + ret = pmu_ctr_stop_fw(cbase, event_code); + else + ret = pmu_ctr_stop_hw(cbase); + + if (!ret && (flag & SBI_PMU_STOP_FLAG_RESET)) + active_events[hartid][cbase] = SBI_PMU_EVENT_IDX_INVALID; + } + + return ret; +} + +static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx, + unsigned long eindex, uint64_t data) +{ + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + const struct sbi_platform *plat = sbi_platform_ptr(scratch); + uint64_t mhpmevent_val; + + /* Get the final mhpmevent value to be written from platform */ + mhpmevent_val = sbi_platform_pmu_xlate_to_mhpmevent(plat, eindex, data); + + if (!mhpmevent_val || ctr_idx < 3 || ctr_idx >= SBI_PMU_HW_CTR_MAX) + return SBI_EFAIL; + + /* TODO: The upper 8 bits of mhpmevent is reserved by sscofpmf extension. + * Update those bits based on the flags received from supervisor. + * The OVF bit also should be cleared here in case it was not cleared + * during event stop. + */ + csr_write_num(CSR_MCOUNTINHIBIT + ctr_idx, mhpmevent_val); + + return 0; +} + +static int pmu_ctr_find_hw(unsigned long cbase, unsigned long cmask, + unsigned long event_idx, uint64_t data) +{ + unsigned long ctr_mask; + int i, ret = 0, ctr_idx = SBI_ENOTSUPP; + struct sbi_pmu_hw_event *temp; + unsigned long mctr_en = csr_read(CSR_MCOUNTEREN); + unsigned long mctr_inhbt = csr_read(CSR_MCOUNTINHIBIT); + int evt_idx_code = get_cidx_code(event_idx); + + if (cbase > num_hw_ctrs) + return SBI_EINVAL; + + /* Non-programmables counters are enabled always. No need to do lookup */ + if (evt_idx_code == SBI_PMU_HW_CPU_CYCLES) + return 0; + else if (evt_idx_code == SBI_PMU_HW_INSTRUCTIONS) + return 2; + + for (i = 0; i < num_hw_events; i++) { + temp = &hw_event_map[i]; + if ((temp->start_idx > event_idx && event_idx < temp->end_idx) || + (temp->start_idx < event_idx && event_idx > temp->end_idx)) + continue; + + /* For raw events, event data is used as the select value */ + if ((event_idx == SBI_PMU_EVENT_RAW_IDX) && temp->select != data) + continue; + + ctr_mask = temp->counters & (cmask << cbase); + for_each_set_bit_from(cbase, &ctr_mask, SBI_PMU_HW_CTR_MAX) { + if (!__test_bit(cbase, &mctr_en) && + __test_bit(cbase, &mctr_inhbt)) { + ctr_idx = cbase; + break; + } + } + } + + if (ctr_idx == SBI_ENOTSUPP) + return SBI_EFAIL; + + ret = pmu_update_hw_mhpmevent(temp, ctr_idx, event_idx, data); + + if (!ret) + ret = ctr_idx; + + return ret; +} + + +/** + * Any firmware counter can map to any firmware event. + * Thus, select the first available fw counter after sanity + * check. + */ +static int pmu_ctr_find_fw(unsigned long cbase, unsigned long cmask, u32 hartid) +{ + int i = 0; + int fw_base; + unsigned long ctr_mask = cmask << cbase; + + if (cbase <= num_hw_ctrs) + fw_base = num_hw_ctrs + 1; + else + fw_base = cbase; + + for (i = fw_base; i < total_ctrs; i++) + if ((active_events[hartid][i] == SBI_PMU_EVENT_IDX_INVALID) && + ((1UL << i) & ctr_mask)) + return i; + + return SBI_ENOTSUPP; +} + +int sbi_pmu_ctr_cfg_match(unsigned long cidx_base, unsigned long cidx_mask, + unsigned long flags, unsigned long event_idx, + uint64_t event_data) +{ + int ctr_idx = SBI_ENOTSUPP; + u32 hartid = current_hartid(); + int event_type = get_cidx_type(event_idx); + struct sbi_pmu_fw_event *fevent; + uint32_t fw_evt_code; + unsigned long tmp = cidx_mask << cidx_base; + + /* Do a basic sanity check of counter base & mask */ + if (__fls(tmp) >= total_ctrs || event_type >= SBI_PMU_EVENT_TYPE_MAX) + return SBI_EINVAL; + + if (flags & SBI_PMU_CFG_FLAG_SKIP_MATCH) { + /* The caller wants to skip the match because it already knows the + * counter idx for the given event. Verify that the counter idx + * is still valid. + */ + if (active_events[hartid][cidx_base] == SBI_PMU_EVENT_IDX_INVALID) + return SBI_EINVAL; + ctr_idx = cidx_base; + goto skip_match; + } + + if (event_type == SBI_PMU_EVENT_TYPE_FW) { + /* Any firmware counter can be used track any firmware event */ + ctr_idx = pmu_ctr_find_fw(cidx_base, cidx_mask, hartid); + } else { + ctr_idx = pmu_ctr_find_hw(cidx_base, cidx_mask, event_idx, event_data); + } + + if (ctr_idx < 0) + return SBI_ENOTSUPP; + + active_events[hartid][ctr_idx] = event_idx; +skip_match: + if (event_type == SBI_PMU_EVENT_TYPE_HW) { + if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) + pmu_ctr_write_hw(ctr_idx, 0); + if (flags & SBI_PMU_CFG_FLAG_AUTO_START) + pmu_ctr_start_hw(ctr_idx, 0, false); + } else if (event_type == SBI_PMU_EVENT_TYPE_FW) { + fw_evt_code = get_cidx_code(event_idx); + fevent = &fw_event_map[hartid][fw_evt_code]; + if (flags & SBI_PMU_CFG_FLAG_CLEAR_VALUE) + fevent->curr_count = 0; + if (flags & SBI_PMU_CFG_FLAG_AUTO_START) + fevent->bStarted = TRUE; + } + + return ctr_idx; +} + +inline int sbi_pmu_ctr_incr_fw(enum sbi_pmu_fw_event_code_id fw_id) +{ + u32 hartid = current_hartid(); + struct sbi_pmu_fw_event *fevent; + + if (unlikely(fw_id >= SBI_PMU_FW_MAX)) + return SBI_EINVAL; + + fevent = &fw_event_map[hartid][fw_id]; + + /* PMU counters will be only enabled during performance debugging */ + if (unlikely(fevent->bStarted)) + fevent->curr_count++; + + return 0; +} + +unsigned long sbi_pmu_num_ctr(void) +{ + return (num_hw_ctrs + SBI_PMU_FW_CTR_MAX); +} + +int sbi_pmu_ctr_get_info(uint32_t cidx, unsigned long *ctr_info) +{ + union sbi_pmu_ctr_info cinfo = {0}; + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + + /* Sanity check. Counter1 is not mapped at all */ + if (cidx >= total_ctrs || cidx == 1) + return SBI_EINVAL; + + /* We have 31 HW counters with 31 being the last index(MHPMCOUNTER31) */ + if (cidx <= num_hw_ctrs) { + cinfo.type = SBI_PMU_CTR_TYPE_HW; + cinfo.csr = CSR_CYCLE + cidx; + /* mcycle & minstret are always 64 bit */ + if (cidx == 0 || cidx == 2) + cinfo.width = 63; + else + cinfo.width = sbi_hart_mhpm_bits(scratch); + } else { + /* it's a firmware counter */ + cinfo.type = SBI_PMU_CTR_TYPE_FW; + /* Firmware counters are XLEN bits wide */ + cinfo.width = BITS_PER_LONG - 1; + } + + *ctr_info = cinfo.value; + + return 0; +} + +static void pmu_reset_event_map(u32 hartid) +{ + int j; + + /* Initialize the counter to event mapping table */ + for (j = 3; j < total_ctrs; j++) + active_events[hartid][j] = SBI_PMU_EVENT_IDX_INVALID; + for (j = 0; j < SBI_PMU_FW_CTR_MAX; j++) + sbi_memset(&fw_event_map[hartid][j], 0, + sizeof(struct sbi_pmu_fw_event)); +} + +void sbi_pmu_exit(struct sbi_scratch *scratch) +{ + u32 hartid = current_hartid(); + + csr_write(CSR_MCOUNTINHIBIT, 0xFFFFFFF8); + csr_write(CSR_MCOUNTEREN, 7); + pmu_reset_event_map(hartid); +} + +int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot) +{ + const struct sbi_platform *plat; + u32 hartid = current_hartid(); + + if (!sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT)) + return SBI_ENOTSUPP; + + if (cold_boot) { + plat = sbi_platform_ptr(scratch); + /* Initialize hw pmu events */ + sbi_platform_pmu_init(plat); + + /* mcycle & minstret is available always */ + num_hw_ctrs = sbi_hart_mhpm_count(scratch) + 2; + total_ctrs = num_hw_ctrs + SBI_PMU_FW_CTR_MAX; + } + + pmu_reset_event_map(hartid); + + /* First three counters are fixed by the priv spec and we enable it by default */ + active_events[hartid][0] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET | + SBI_PMU_HW_CPU_CYCLES; + active_events[hartid][1] = SBI_PMU_EVENT_IDX_INVALID; + active_events[hartid][2] = SBI_PMU_EVENT_TYPE_HW << SBI_PMU_EVENT_IDX_OFFSET | + SBI_PMU_HW_INSTRUCTIONS; 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25 Jun 2021 17:57:52 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , anup.patel@wdc.com Subject: [PATCH v3 11/15] utils: fdt: Add fdt helper functions to parse PMU DT nodes Date: Fri, 25 Jun 2021 17:57:17 -0700 Message-Id: <20210626005721.3600114-12-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175753_590955_EB171A58 X-CRM114-Status: GOOD ( 23.10 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The PMU DT node bindings are defined in docs/pmu_support.md Add few fdt helper functions to parse the DT node and update the event-counter mapping tables. Signed-off-by: Atish Patra --- include/sbi_utils/fdt/fdt_pmu.h | 46 +++++++++++++ lib/utils/fdt/fdt_fixup.c | 2 + lib/utils/fdt/fdt_pmu.c | 111 ++++++++++++++++++++++++++++++++ l [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The PMU DT node bindings are defined in docs/pmu_support.md Add few fdt helper functions to parse the DT node and update the event-counter mapping tables. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi_utils/fdt/fdt_pmu.h | 46 +++++++++++++ lib/utils/fdt/fdt_fixup.c | 2 + lib/utils/fdt/fdt_pmu.c | 111 ++++++++++++++++++++++++++++++++ lib/utils/fdt/objects.mk | 1 + 4 files changed, 160 insertions(+) create mode 100644 include/sbi_utils/fdt/fdt_pmu.h create mode 100644 lib/utils/fdt/fdt_pmu.c diff --git a/include/sbi_utils/fdt/fdt_pmu.h b/include/sbi_utils/fdt/fdt_pmu.h new file mode 100644 index 000000000000..2fa01edc0743 --- /dev/null +++ b/include/sbi_utils/fdt/fdt_pmu.h @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * fdt_pmu.c - Flat Device Tree PMU helper routines + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#ifndef __FDT_PMU_H__ +#define __FDT_PMU_H__ + +#include + +/** + * Fix up the PMU node in the device tree + * + * This routine: + * 1. Disables opensbi specific properties from the DT + * + * It is recommended that platform support call this function in + * their final_init() platform operation. + * + * @param fdt device tree blob + */ +void fdt_pmu_fixup(void *fdt); + +/** + * Setup PMU data from device tree + * + * @param fdt device tree blob + * + * @return 0 on success and negative error code on failure + */ +int fdt_pmu_setup(void *fdt); + +/** + * Get the mhpmevent select value read from DT for a given event + * @param event_idx Event ID of the given event + * + * @return The select value read from DT or 0 if given index was not found + */ +uint64_t fdt_pmu_get_select_value(uint32_t event_idx); + +#endif diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c index 14655000b815..ac01ba3dfac1 100644 --- a/lib/utils/fdt/fdt_fixup.c +++ b/lib/utils/fdt/fdt_fixup.c @@ -15,6 +15,7 @@ #include #include #include +#include #include void fdt_cpu_fixup(void *fdt) @@ -263,6 +264,7 @@ void fdt_fixups(void *fdt) fdt_plic_fixup(fdt); fdt_reserved_memory_fixup(fdt); + fdt_pmu_fixup(fdt); } diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c new file mode 100644 index 000000000000..910bf30ee761 --- /dev/null +++ b/lib/utils/fdt/fdt_pmu.c @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * fdt_pmu.c - Flat Device Tree PMU helper routines + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include + +#define FDT_PMU_HW_EVENT_MAX (SBI_PMU_HW_EVENT_MAX * 2) + +struct fdt_pmu_hw_event_select { + uint32_t eidx; + uint64_t select; +}; + +static struct fdt_pmu_hw_event_select fdt_pmu_evt_select[FDT_PMU_HW_EVENT_MAX] = {0}; +static uint32_t hw_event_count; + +uint64_t fdt_pmu_get_select_value(uint32_t event_idx) +{ + int i; + struct fdt_pmu_hw_event_select *event; + + for (i = 0; i < SBI_PMU_HW_EVENT_MAX; i++) { + event = &fdt_pmu_evt_select[i]; + if (event->eidx == event_idx) + return event->select; + } + + return 0; +} + +int fdt_pmu_fixup(void *fdt) +{ + int pmu_offset; + + if (!fdt) + return SBI_EINVAL; + + pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu"); + if (pmu_offset < 0) + return SBI_EFAIL; + + fdt_delprop(fdt, pmu_offset, "opensbi,event-to-counters"); + fdt_delprop(fdt, pmu_offset, "opensbi,event-to-mhpmevent"); + fdt_delprop(fdt, pmu_offset, "opensbi,raw-event-to-counters"); + + return 0; +} + +int fdt_pmu_setup(void *fdt) +{ + int i, pmu_offset, len, result; + const u32 *event_val; + const u32 *event_ctr_map; + struct fdt_pmu_hw_event_select *event; + uint64_t raw_selector; + u32 event_idx_start, event_idx_end, ctr_map; + + if (!fdt) + return SBI_EINVAL; + + pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu"); + if (pmu_offset < 0) + return SBI_EFAIL; + + event_ctr_map = fdt_getprop(fdt, pmu_offset, "opensbi,event-to-counters", &len); + if (!event_ctr_map || len < 8) + return SBI_EFAIL; + len = len / (sizeof(u32) * 3); + for (i = 0; i < len; i++) { + event_idx_start = fdt32_to_cpu(event_ctr_map[3 * i]); + event_idx_end = fdt32_to_cpu(event_ctr_map[3 * i + 1]); + ctr_map = fdt32_to_cpu(event_ctr_map[3 * i + 2]); + sbi_pmu_add_hw_event_counter_map(event_idx_start, event_idx_end, ctr_map); + } + + event_val = fdt_getprop(fdt, pmu_offset, "opensbi,event-to-mhpmevent", &len); + if (!event_val || len < 8) + return SBI_EFAIL; + len = len / (sizeof(u32) * 3); + for (i = 0; i < len; i++) { + event = &fdt_pmu_evt_select[hw_event_count]; + event->eidx = fdt32_to_cpu(event_val[3 * i]); + event->select = fdt32_to_cpu(event_val[3 * i + 1]); + event->select = (event->select << 32) | fdt32_to_cpu(event_val[3 * i + 2]); + hw_event_count++; + } + + event_val = fdt_getprop(fdt, pmu_offset, "opensbi,raw-event-to-counters", &len); + if (!event_val || len < 8) + return SBI_EFAIL; + len = len / (sizeof(u32) * 3); + for (i = 0; i < len; i++) { + raw_selector = fdt32_to_cpu(event_val[3 * i]); + raw_selector = (raw_selector << 32) | fdt32_to_cpu(event_val[3 * i + 1]); + ctr_map = fdt32_to_cpu(event_val[3 * i + 2]); + result = sbi_pmu_add_raw_event_counter_map(raw_selector, ctr_map); + if (!result) + hw_event_count++; + } + + return 0; +} diff --git a/lib/utils/fdt/objects.mk b/lib/utils/fdt/objects.mk index d9f1eae19292..03800f96d74d 100644 --- a/lib/utils/fdt/objects.mk +++ b/lib/utils/fdt/objects.mk @@ -5,5 +5,6 @@ # libsbiutils-objs-y += fdt/fdt_domain.o +libsbiutils-objs-y += fdt/fdt_pmu.o libsbiutils-objs-y += fdt/fdt_helper.o libsbiutils-objs-y += fdt/fdt_fixup.o From patchwork Sat Jun 26 00:57:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; 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25 Jun 2021 17:36:27 -0700 IronPort-SDR: B0i1uVODFeOq30NH7LZ28FRksY0tW+7Uvkaa9ffbaBjC68Ie1CjQ3bWybAtOKzitSLBAlmAsmz Dm7ZWcoMTPgzQumPhj4de70c0cUU7iG62PFF6Hz6LEni8JJIurWhchefwfoYMJOiANxi5X+Vp4 nwf2xFhUGGvLLQdk+PaBX5X6abZ+EaW8arepn1pg2LZt0dXHRfVsUwRVx0fB0gWHCbRijStKJs pcERuhBOHprfZk2pLjyeRXXeiHq71XkjumuFryL4gmKjVxr6YjIP+Q+lWYtzuZWpDh5etUAIGg /2Y= WDCIronportException: Internal Received: from unknown (HELO jedi-01.wdc.com) ([10.225.163.19]) by uls-op-cesaip02.wdc.com with ESMTP; 25 Jun 2021 17:57:54 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , anup.patel@wdc.com Subject: [PATCH v3 12/15] lib: sbi: Implement SBI PMU extension Date: Fri, 25 Jun 2021 17:57:18 -0700 Message-Id: <20210626005721.3600114-13-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175755_422304_DE47FF35 X-CRM114-Status: GOOD ( 18.96 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: RISC-V SBI specfication 0.3 defines a PMU extension that allows supervisor mode to start/stop/configure pmu related events. This patch implements all of the functionality defined in the specification. Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org RISC-V SBI specfication 0.3 defines a PMU extension that allows supervisor mode to start/stop/configure pmu related events. This patch implements all of the functionality defined in the specification. Signed-off-by: Atish Patra Reviewed-by: Anup Patel --- include/sbi/sbi_ecall.h | 1 + lib/sbi/objects.mk | 1 + lib/sbi/sbi_ecall.c | 5 +++ lib/sbi/sbi_ecall_pmu.c | 93 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 100 insertions(+) create mode 100644 lib/sbi/sbi_ecall_pmu.c diff --git a/include/sbi/sbi_ecall.h b/include/sbi/sbi_ecall.h index 63ef866ba2d4..9500d0430429 100644 --- a/include/sbi/sbi_ecall.h +++ b/include/sbi/sbi_ecall.h @@ -39,6 +39,7 @@ extern struct sbi_ecall_extension ecall_ipi; extern struct sbi_ecall_extension ecall_vendor; extern struct sbi_ecall_extension ecall_hsm; extern struct sbi_ecall_extension ecall_srst; +extern struct sbi_ecall_extension ecall_pmu; u16 sbi_ecall_version_major(void); diff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk index d9068b707854..7096f245ae0c 100644 --- a/lib/sbi/objects.mk +++ b/lib/sbi/objects.mk @@ -20,6 +20,7 @@ libsbi-objs-y += sbi_ecall.o libsbi-objs-y += sbi_ecall_base.o libsbi-objs-y += sbi_ecall_hsm.o libsbi-objs-y += sbi_ecall_legacy.o +libsbi-objs-y += sbi_ecall_pmu.o libsbi-objs-y += sbi_ecall_replace.o libsbi-objs-y += sbi_ecall_vendor.o libsbi-objs-y += sbi_emulate_csr.o diff --git a/lib/sbi/sbi_ecall.c b/lib/sbi/sbi_ecall.c index e92a53930460..fad05bcc2c62 100644 --- a/lib/sbi/sbi_ecall.c +++ b/lib/sbi/sbi_ecall.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include u16 sbi_ecall_version_major(void) @@ -162,6 +164,9 @@ int sbi_ecall_init(void) if (ret) return ret; ret = sbi_ecall_register_extension(&ecall_srst); + if (ret) + return ret; + ret = sbi_ecall_register_extension(&ecall_pmu); if (ret) return ret; ret = sbi_ecall_register_extension(&ecall_legacy); diff --git a/lib/sbi/sbi_ecall_pmu.c b/lib/sbi/sbi_ecall_pmu.c new file mode 100644 index 000000000000..39d3857680c1 --- /dev/null +++ b/lib/sbi/sbi_ecall_pmu.c @@ -0,0 +1,93 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int sbi_ecall_pmu_handler(unsigned long extid, unsigned long funcid, + const struct sbi_trap_regs *regs, + unsigned long *out_val, + struct sbi_trap_info *out_trap) +{ + int ret = 0; + uint64_t temp; + + switch (funcid) { + case SBI_EXT_PMU_NUM_COUNTERS: + ret = sbi_pmu_num_ctr(); + if (ret >= 0) { + *out_val = ret; + ret = 0; + } + break; + case SBI_EXT_PMU_COUNTER_GET_INFO: + ret = sbi_pmu_ctr_get_info(regs->a0, out_val); + break; + case SBI_EXT_PMU_COUNTER_CFG_MATCH: +#if __riscv_xlen == 32 + temp = ((uint64_t)regs->a5 << 32) | regs->a4; +#else + temp = regs->a4; +#endif + ret = sbi_pmu_ctr_cfg_match(regs->a0, regs->a1, regs->a2, + regs->a3, temp); + if (ret >= 0) { + *out_val = ret; + ret = 0; + } + + break; + case SBI_EXT_PMU_COUNTER_FW_READ: + ret = sbi_pmu_ctr_read(regs->a0, out_val); + break; + case SBI_EXT_PMU_COUNTER_START: + +#if __riscv_xlen == 32 + temp = ((uint64_t)regs->a4 << 32) | regs->a3; +#else + temp = regs->a3; +#endif + ret = sbi_pmu_ctr_start(regs->a0, regs->a1, regs->a2, temp); + break; + case SBI_EXT_PMU_COUNTER_STOP: + ret = sbi_pmu_ctr_stop(regs->a0, regs->a1, regs->a2); + break; + default: + ret = SBI_ENOTSUPP; + }; + + return ret; +} + +static int sbi_ecall_pmu_probe(unsigned long extid, unsigned long *out_val) +{ + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr(); + + /* SBI PMU extension is useless without mcount inhibit features */ + if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTINHIBIT)) + *out_val = 1; + else + *out_val = 0; + + return 0; +} + +struct sbi_ecall_extension ecall_pmu = { + .extid_start = SBI_EXT_PMU, + .extid_end = SBI_EXT_PMU, + .handle = sbi_ecall_pmu_handler, + .probe = sbi_ecall_pmu_probe, +}; From patchwork Sat Jun 26 00:57:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497529 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=xfhxC/7A; dkim=fail reason="signature verification failed" (2048-bit key; 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25 Jun 2021 17:36:29 -0700 IronPort-SDR: tBZBhoLxdkP+cMnYtI5GvmiCFmjC7y7Xa1APllOS/t4JPCLq63LPW+8t0qKkGkWucGfPekNLZZ KHgcZgq8dnVUAbCAOD6jJCWMFsfCtLFeNChpJOVmIKKfiCS4/eXQ6UckXW9IjsPi5fu0o9gt7N 4hU8TnCb1FEGfqxPjMTwXCD3iVSDQ1H33gl/mr3soGpBvbr1eGwZ17umduOTKwaUm1Pfbj1aWS DteAHKfttcUX9GtTBz5ogDUb4UehA00NcNjrdAb+m35OCHldhH4oUfGbY9BGtDdVdXcGWEhkRy JVY= WDCIronportException: Internal Received: from unknown (HELO jedi-01.wdc.com) ([10.225.163.19]) by uls-op-cesaip02.wdc.com with ESMTP; 25 Jun 2021 17:57:55 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 13/15] lib: sbi: Implement firmware counters Date: Fri, 25 Jun 2021 17:57:19 -0700 Message-Id: <20210626005721.3600114-14-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175756_801485_3FDF58A2 X-CRM114-Status: GOOD ( 16.55 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: RISC-V SBI v0.3 specification defines a set of firmware events that can provide additional information about the current firmware context. All of the firmware event monitoring are enabled now. The fir [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org RISC-V SBI v0.3 specification defines a set of firmware events that can provide additional information about the current firmware context. All of the firmware event monitoring are enabled now. The firmware events must be defined as raw perf event with MSB set as specified in the specification. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_illegal_insn.c | 2 ++ lib/sbi/sbi_ipi.c | 6 ++++++ lib/sbi/sbi_misaligned_ldst.c | 5 +++++ lib/sbi/sbi_timer.c | 2 ++ lib/sbi/sbi_tlb.c | 38 +++++++++++++++++++++++++++++++++++ lib/sbi/sbi_trap.c | 7 +++++++ 6 files changed, 60 insertions(+) diff --git a/lib/sbi/sbi_illegal_insn.c b/lib/sbi/sbi_illegal_insn.c index 9af3d24d797e..bfe7d6195898 100644 --- a/lib/sbi/sbi_illegal_insn.c +++ b/lib/sbi/sbi_illegal_insn.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -129,6 +130,7 @@ int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs) * instruction trap. */ + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_ILLEGAL_INSN); if (unlikely((insn & 3) != 3)) { insn = sbi_get_insn(regs->mepc, &uptrap); if (uptrap.cause) { diff --git a/lib/sbi/sbi_ipi.c b/lib/sbi/sbi_ipi.c index 75f86d8e76f3..1014909bcfa3 100644 --- a/lib/sbi/sbi_ipi.c +++ b/lib/sbi/sbi_ipi.c @@ -19,6 +19,9 @@ #include #include #include +#include +#include +#include struct sbi_ipi_data { unsigned long ipi_type; @@ -64,6 +67,8 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid, if (ipi_dev && ipi_dev->ipi_send) ipi_dev->ipi_send(remote_hartid); + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_IPI_SENT); + if (ipi_ops->sync) ipi_ops->sync(scratch); @@ -183,6 +188,7 @@ void sbi_ipi_process(void) sbi_scratch_offset_ptr(scratch, ipi_data_off); u32 hartid = current_hartid(); + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_IPI_RECVD); if (ipi_dev && ipi_dev->ipi_clear) ipi_dev->ipi_clear(hartid); diff --git a/lib/sbi/sbi_misaligned_ldst.c b/lib/sbi/sbi_misaligned_ldst.c index 5057cb5ecd58..c879ce72f61a 100644 --- a/lib/sbi/sbi_misaligned_ldst.c +++ b/lib/sbi/sbi_misaligned_ldst.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -29,6 +30,8 @@ int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst, struct sbi_trap_info uptrap; int i, fp = 0, shift = 0, len = 0; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_LOAD); + if (tinst & 0x1) { /* * Bit[0] == 1 implies trapped instruction value is @@ -149,6 +152,8 @@ int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst, struct sbi_trap_info uptrap; int i, len = 0; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_MISALIGNED_STORE); + if (tinst & 0x1) { /* * Bit[0] == 1 implies trapped instruction value is diff --git a/lib/sbi/sbi_timer.c b/lib/sbi/sbi_timer.c index 77d6f95032a7..275950125baf 100644 --- a/lib/sbi/sbi_timer.c +++ b/lib/sbi/sbi_timer.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -88,6 +89,7 @@ void sbi_timer_set_delta_upper(ulong delta_upper) void sbi_timer_event_start(u64 next_event) { + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SET_TIMER); if (timer_dev && timer_dev->timer_event_start) timer_dev->timer_event_start(next_event); csr_clear(CSR_MIP, MIP_STIP); diff --git a/lib/sbi/sbi_tlb.c b/lib/sbi/sbi_tlb.c index 8bbe92b0978e..1a9cb1d2b5df 100644 --- a/lib/sbi/sbi_tlb.c +++ b/lib/sbi/sbi_tlb.c @@ -21,6 +21,7 @@ #include #include #include +#include static unsigned long tlb_sync_off; static unsigned long tlb_fifo_off; @@ -39,6 +40,8 @@ void sbi_tlb_local_hfence_vvma(struct sbi_tlb_info *tinfo) unsigned long vmid = tinfo->vmid; unsigned long i, hgatp; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_RCVD); + hgatp = csr_swap(CSR_HGATP, (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK); @@ -61,6 +64,8 @@ void sbi_tlb_local_hfence_gvma(struct sbi_tlb_info *tinfo) unsigned long size = tinfo->size; unsigned long i; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_RCVD); + if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) { __sbi_hfence_gvma_all(); return; @@ -77,6 +82,8 @@ void sbi_tlb_local_sfence_vma(struct sbi_tlb_info *tinfo) unsigned long size = tinfo->size; unsigned long i; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_RCVD); + if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) { sbi_tlb_flush_all(); return; @@ -98,6 +105,8 @@ void sbi_tlb_local_hfence_vvma_asid(struct sbi_tlb_info *tinfo) unsigned long vmid = tinfo->vmid; unsigned long i, hgatp; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_ASID_RCVD); + hgatp = csr_swap(CSR_HGATP, (vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK); @@ -126,6 +135,8 @@ void sbi_tlb_local_hfence_gvma_vmid(struct sbi_tlb_info *tinfo) unsigned long vmid = tinfo->vmid; unsigned long i; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_VMID_RCVD); + if (start == 0 && size == 0) { __sbi_hfence_gvma_all(); return; @@ -148,6 +159,8 @@ void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo) unsigned long asid = tinfo->asid; unsigned long i; + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_RCVD); + if (start == 0 && size == 0) { sbi_tlb_flush_all(); return; @@ -172,9 +185,32 @@ void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo) void sbi_tlb_local_fence_i(struct sbi_tlb_info *tinfo) { + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_FENCE_I_RECVD); + __asm__ __volatile("fence.i"); } +static void tlb_pmu_incr_fw_ctr(struct sbi_tlb_info *data) +{ + if (unlikely(!data)) + return; + + if (data->local_fn == sbi_tlb_local_fence_i) + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_FENCE_I_SENT); + else if (data->local_fn == sbi_tlb_local_sfence_vma) + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_SENT); + else if (data->local_fn == sbi_tlb_local_sfence_vma_asid) + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_SENT); + else if (data->local_fn == sbi_tlb_local_hfence_gvma) + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_SENT); + else if (data->local_fn == sbi_tlb_local_hfence_gvma_vmid) + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_GVMA_VMID_SENT); + else if (data->local_fn == sbi_tlb_local_hfence_vvma) + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_SENT); + else if (data->local_fn == sbi_tlb_local_hfence_vvma_asid) + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_ASID_SENT); +} + static void sbi_tlb_entry_process(struct sbi_tlb_info *tinfo) { u32 rhartid; @@ -369,6 +405,8 @@ int sbi_tlb_request(ulong hmask, ulong hbase, struct sbi_tlb_info *tinfo) if (!tinfo->local_fn) return SBI_EINVAL; + tlb_pmu_incr_fw_ctr(tinfo); + return sbi_ipi_send_many(hmask, hbase, tlb_event, tinfo); } diff --git a/lib/sbi/sbi_trap.c b/lib/sbi/sbi_trap.c index 1ba649074b75..5781fea2a115 100644 --- a/lib/sbi/sbi_trap.c +++ b/lib/sbi/sbi_trap.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -257,6 +258,12 @@ struct sbi_trap_regs *sbi_trap_handler(struct sbi_trap_regs *regs) rc = sbi_ecall_handler(regs); msg = "ecall handler failed"; break; + case CAUSE_LOAD_ACCESS: + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_ACCESS_LOAD); + break; + case CAUSE_STORE_ACCESS: + sbi_pmu_ctr_incr_fw(SBI_PMU_FW_ACCESS_STORE); + break; default: /* If the trap came from S or U mode, redirect it there */ trap.epc = regs->mepc; From patchwork Sat Jun 26 00:57:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497531 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=GZEM8OD2; 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25 Jun 2021 17:36:30 -0700 IronPort-SDR: 08JEV48rZJy5/GouPgHNREs7XtJCLpE/e31udrO29LVEIbM891HJXYqiul3lGyqvcQGxWVUDwW fS8YfuVISPfNhZD1tDGBvZmdKA9TRap1bc4e5X9Yn5MNr/ShkDdznxyP708Z34n9hHyp9K5p/1 SxstKLouSBecT1mPERQv7ovtD6KedofaXVATwZ6zIDSZVN9gIRQEAxwd6Xkdk40UM+9GP2EWie mv08C4Fgw3n/FZkFD8VkWEkLnnwpSuI9rmSrlgjzs4mMh/O9ODK+T76C05rqG+ciGVwZ85ay3T yVw= WDCIronportException: Internal Received: from unknown (HELO jedi-01.wdc.com) ([10.225.163.19]) by uls-op-cesaip02.wdc.com with ESMTP; 25 Jun 2021 17:57:57 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 14/15] lib:sbi:tlb: Improve function naming Date: Fri, 25 Jun 2021 17:57:20 -0700 Message-Id: <20210626005721.3600114-15-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175758_381463_C0C97555 X-CRM114-Status: GOOD ( 14.93 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. 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Content preview: Follow the standard conventon for static function names: All global functions should be start with sbi__ All static functions should be start with _ Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_tlb.c | 41 ++++++++++++++++++++ 1 file changed, 20 insertions(+), 21 [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Follow the standard conventon for static function names: All global functions should be start with sbi__ All static functions should be start with _ Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- lib/sbi/sbi_tlb.c | 41 ++++++++++++++++++++--------------------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/lib/sbi/sbi_tlb.c b/lib/sbi/sbi_tlb.c index 1a9cb1d2b5df..efa74a7542b3 100644 --- a/lib/sbi/sbi_tlb.c +++ b/lib/sbi/sbi_tlb.c @@ -28,7 +28,7 @@ static unsigned long tlb_fifo_off; static unsigned long tlb_fifo_mem_off; static unsigned long tlb_range_flush_limit; -static void sbi_tlb_flush_all(void) +static void tlb_flush_all(void) { __asm__ __volatile("sfence.vma"); } @@ -85,7 +85,7 @@ void sbi_tlb_local_sfence_vma(struct sbi_tlb_info *tinfo) sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_RCVD); if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) { - sbi_tlb_flush_all(); + tlb_flush_all(); return; } @@ -162,7 +162,7 @@ void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo) sbi_pmu_ctr_incr_fw(SBI_PMU_FW_SFENCE_VMA_ASID_RCVD); if (start == 0 && size == 0) { - sbi_tlb_flush_all(); + tlb_flush_all(); return; } @@ -211,7 +211,7 @@ static void tlb_pmu_incr_fw_ctr(struct sbi_tlb_info *data) sbi_pmu_ctr_incr_fw(SBI_PMU_FW_HFENCE_VVMA_ASID_SENT); } -static void sbi_tlb_entry_process(struct sbi_tlb_info *tinfo) +static void tlb_entry_process(struct sbi_tlb_info *tinfo) { u32 rhartid; struct sbi_scratch *rscratch = NULL; @@ -229,8 +229,7 @@ static void sbi_tlb_entry_process(struct sbi_tlb_info *tinfo) } } -static void sbi_tlb_process_count(struct sbi_scratch *scratch, - unsigned int count) +static void tlb_process_count(struct sbi_scratch *scratch, int count) { struct sbi_tlb_info tinfo; unsigned int deq_count = 0; @@ -238,7 +237,7 @@ static void sbi_tlb_process_count(struct sbi_scratch *scratch, sbi_scratch_offset_ptr(scratch, tlb_fifo_off); while (!sbi_fifo_dequeue(tlb_fifo, &tinfo)) { - sbi_tlb_entry_process(&tinfo); + tlb_entry_process(&tinfo); deq_count++; if (deq_count > count) break; @@ -246,17 +245,17 @@ static void sbi_tlb_process_count(struct sbi_scratch *scratch, } } -static void sbi_tlb_process(struct sbi_scratch *scratch) +static void tlb_process(struct sbi_scratch *scratch) { struct sbi_tlb_info tinfo; struct sbi_fifo *tlb_fifo = sbi_scratch_offset_ptr(scratch, tlb_fifo_off); while (!sbi_fifo_dequeue(tlb_fifo, &tinfo)) - sbi_tlb_entry_process(&tinfo); + tlb_entry_process(&tinfo); } -static void sbi_tlb_sync(struct sbi_scratch *scratch) +static void tlb_sync(struct sbi_scratch *scratch) { unsigned long *tlb_sync = sbi_scratch_offset_ptr(scratch, tlb_sync_off); @@ -266,13 +265,13 @@ static void sbi_tlb_sync(struct sbi_scratch *scratch) * While we are waiting for remote hart to set the sync, * consume fifo requests to avoid deadlock. */ - sbi_tlb_process_count(scratch, 1); + tlb_process_count(scratch, 1); } return; } -static inline int __sbi_tlb_range_check(struct sbi_tlb_info *curr, +static inline int tlb_range_check(struct sbi_tlb_info *curr, struct sbi_tlb_info *next) { unsigned long curr_end; @@ -315,7 +314,7 @@ static inline int __sbi_tlb_range_check(struct sbi_tlb_info *curr, * before continuing the while loop. This method is preferred over wfi/ipi because * of MMIO cost involved in later method. */ -static int sbi_tlb_update_cb(void *in, void *data) +static int tlb_update_cb(void *in, void *data) { struct sbi_tlb_info *curr; struct sbi_tlb_info *next; @@ -330,16 +329,16 @@ static int sbi_tlb_update_cb(void *in, void *data) if (next->local_fn == sbi_tlb_local_sfence_vma_asid && curr->local_fn == sbi_tlb_local_sfence_vma_asid) { if (next->asid == curr->asid) - ret = __sbi_tlb_range_check(curr, next); + ret = tlb_range_check(curr, next); } else if (next->local_fn == sbi_tlb_local_sfence_vma && curr->local_fn == sbi_tlb_local_sfence_vma) { - ret = __sbi_tlb_range_check(curr, next); + ret = tlb_range_check(curr, next); } return ret; } -static int sbi_tlb_update(struct sbi_scratch *scratch, +static int tlb_update(struct sbi_scratch *scratch, struct sbi_scratch *remote_scratch, u32 remote_hartid, void *data) { @@ -369,7 +368,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch, tlb_fifo_r = sbi_scratch_offset_ptr(remote_scratch, tlb_fifo_off); - ret = sbi_fifo_inplace_update(tlb_fifo_r, data, sbi_tlb_update_cb); + ret = sbi_fifo_inplace_update(tlb_fifo_r, data, tlb_update_cb); if (ret != SBI_FIFO_UNCHANGED) { return 1; } @@ -383,7 +382,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch, * TODO: Introduce a wait/wakeup event mechanism to handle * this properly. */ - sbi_tlb_process_count(scratch, 1); + tlb_process_count(scratch, 1); sbi_dprintf("hart%d: hart%d tlb fifo full\n", curr_hartid, remote_hartid); } @@ -393,9 +392,9 @@ static int sbi_tlb_update(struct sbi_scratch *scratch, static struct sbi_ipi_event_ops tlb_ops = { .name = "IPI_TLB", - .update = sbi_tlb_update, - .sync = sbi_tlb_sync, - .process = sbi_tlb_process, + .update = tlb_update, + .sync = tlb_sync, + .process = tlb_process, }; static u32 tlb_event = SBI_IPI_EVENT_MAX; From patchwork Sat Jun 26 00:57:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1497530 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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25 Jun 2021 17:57:59 -0700 From: Atish Patra To: opensbi@lists.infradead.org Cc: Atish Patra , Anup Patel Subject: [PATCH v3 15/15] platform: generic: Add PMU support Date: Fri, 25 Jun 2021 17:57:21 -0700 Message-Id: <20210626005721.3600114-16-atish.patra@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210626005721.3600114-1-atish.patra@wdc.com> References: <20210626005721.3600114-1-atish.patra@wdc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210625_175800_014651_EF897D59 X-CRM114-Status: GOOD ( 13.70 ) X-Spam-Score: -2.5 (--) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Add PMU support for generic platform. Generic platform solely relies on the device tree to parse all pmu related information. If any event is not described in device tree, generic platform will not su [...] Content analysis details: (-2.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [68.232.141.245 listed in list.dnswl.org] 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Add PMU support for generic platform. Generic platform solely relies on the device tree to parse all pmu related information. If any event is not described in device tree, generic platform will not support it. Reviewed-by: Anup Patel Signed-off-by: Atish Patra --- platform/generic/platform.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/platform/generic/platform.c b/platform/generic/platform.c index da0c1af8f92e..44a9c73fba0c 100644 --- a/platform/generic/platform.c +++ b/platform/generic/platform.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -184,6 +185,33 @@ static u64 generic_tlbr_flush_limit(void) return SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT; } +static int generic_pmu_init(void) +{ + return fdt_pmu_setup(sbi_scratch_thishart_arg1_ptr()); +} + +static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx, + uint64_t data) +{ + uint64_t evt_val = 0; + + /* data is valid only for raw events and is equal to event selector */ + if (event_idx == SBI_PMU_EVENT_RAW_IDX) + evt_val = data; + else { + /** + * Generic platform follows the SBI specification recommendation + * i.e. zero extended event_idx is used as mhpmevent value for + * hardware general/cache events if platform does't define one. + */ + evt_val = fdt_pmu_get_select_value(event_idx); + if (!evt_val) + evt_val = (uint64_t)event_idx; + } + + return evt_val; +} + const struct sbi_platform_operations platform_ops = { .early_init = generic_early_init, .final_init = generic_final_init, @@ -195,6 +223,8 @@ const struct sbi_platform_operations platform_ops = { .irqchip_exit = fdt_irqchip_exit, .ipi_init = fdt_ipi_init, .ipi_exit = fdt_ipi_exit, + .pmu_init = generic_pmu_init, + .pmu_xlate_to_mhpmevent = generic_pmu_xlate_to_mhpmevent, .get_tlbr_flush_limit = generic_tlbr_flush_limit, .timer_init = fdt_timer_init, .timer_exit = fdt_timer_exit,