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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 01/27] spi: spi-mem: allow specifying whether an op is DTR
or not
Date: Sat, 26 Jun 2021 00:47:03 +0530
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Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8 ++++++++
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index c095ae9505..427f7c13c5 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -164,6 +164,9 @@ bool spi_mem_default_supports_op(struct spi_slave *slave,
op->data.dir == SPI_MEM_DATA_OUT))
return false;
+ if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
+ return false;
+
return true;
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/spi-mem.h b/include/spi-mem.h
index e354c38897..8bd4459674 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -71,6 +71,7 @@ enum spi_mem_data_dir {
* struct spi_mem_op - describes a SPI memory operation
* @cmd.buswidth: number of IO lines used to transmit the command
* @cmd.opcode: operation opcode
+ * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
* @addr.nbytes: number of address bytes to send. Can be zero if the operation
* does not need to send an address
* @addr.buswidth: number of IO lines used to transmit the address cycles
@@ -78,10 +79,13 @@ enum spi_mem_data_dir {
* Note that only @addr.nbytes are taken into account in this
* address value, so users should make sure the value fits in the
* assigned number of bytes.
+ * @addr.dtr: whether the address should be sent in DTR mode or not
* @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can
* be zero if the operation does not require dummy bytes
* @dummy.buswidth: number of IO lanes used to transmit the dummy bytes
+ * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
* @data.buswidth: number of IO lanes used to send/receive the data
+ * @data.dtr: whether the data should be sent in DTR mode or not
* @data.dir: direction of the transfer
* @data.buf.in: input buffer
* @data.buf.out: output buffer
@@ -90,21 +94,25 @@ struct spi_mem_op {
struct {
u8 buswidth;
u8 opcode;
+ u8 dtr : 1;
} cmd;
struct {
u8 nbytes;
u8 buswidth;
+ u8 dtr : 1;
u64 val;
} addr;
struct {
u8 nbytes;
u8 buswidth;
+ u8 dtr : 1;
} dummy;
struct {
u8 buswidth;
+ u8 dtr : 1;
enum spi_mem_data_dir dir;
unsigned int nbytes;
/* buf.{in,out} must be DMA-able. */
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 02/27] spi: spi-mem: allow specifying a command's
extension
Date: Sat, 26 Jun 2021 00:47:04 +0530
Message-ID: <20210625191729.31798-3-p.yadav@ti.com>
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In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the opcode. When it is "hex" an additional opcode byte based
is sent with the command whose value can be anything.
So, make opcode a 16-bit value and add a 'nbytes', similar to how
multiple address widths are handled.
All usages of sizeof(op->cmd.opcode) also need to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav
---
drivers/spi/mtk_snfi_spi.c | 3 +--
drivers/spi/spi-mem-nodm.c | 4 ++--
drivers/spi/spi-mem.c | 13 +++++++------
include/spi-mem.h | 6 +++++-
4 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/mtk_snfi_spi.c b/drivers/spi/mtk_snfi_spi.c
index b6ab5fa3ad..65d0ce0981 100644
--- a/drivers/spi/mtk_snfi_spi.c
+++ b/drivers/spi/mtk_snfi_spi.c
@@ -64,8 +64,7 @@ static int mtk_snfi_adjust_op_size(struct spi_slave *slave,
* or the output+input data must not exceed the GPRAM size.
*/
- nbytes = sizeof(op->cmd.opcode) + op->addr.nbytes +
- op->dummy.nbytes;
+ nbytes = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
if (nbytes + op->data.nbytes <= SNFI_GPRAM_SIZE)
return 0;
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
index 765f05fe54..db54101383 100644
--- a/drivers/spi/spi-mem-nodm.c
+++ b/drivers/spi/spi-mem-nodm.c
@@ -27,7 +27,7 @@ int spi_mem_exec_op(struct spi_slave *slave,
tx_buf = op->data.buf.out;
}
- op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
op_buf = calloc(1, op_len);
ret = spi_claim_bus(slave);
@@ -89,7 +89,7 @@ int spi_mem_adjust_op_size(struct spi_slave *slave,
{
unsigned int len;
- len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
if (slave->max_write_size && len > slave->max_write_size)
return -EINVAL;
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 427f7c13c5..541cd0e5a7 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -167,6 +167,9 @@ bool spi_mem_default_supports_op(struct spi_slave *slave,
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
return false;
+ if (op->cmd.nbytes != 1)
+ return false;
+
return true;
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
@@ -273,8 +276,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
}
#ifndef __UBOOT__
- tmpbufsize = sizeof(op->cmd.opcode) + op->addr.nbytes +
- op->dummy.nbytes;
+ tmpbufsize = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
/*
* Allocate a buffer to transmit the CMD, ADDR cycles with kmalloc() so
@@ -289,7 +291,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
tmpbuf[0] = op->cmd.opcode;
xfers[xferpos].tx_buf = tmpbuf;
- xfers[xferpos].len = sizeof(op->cmd.opcode);
+ xfers[xferpos].len = op->cmd.nbytes;
xfers[xferpos].tx_nbits = op->cmd.buswidth;
spi_message_add_tail(&xfers[xferpos], &msg);
xferpos++;
@@ -353,7 +355,7 @@ int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
tx_buf = op->data.buf.out;
}
- op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
/*
* Avoid using malloc() here so that we can use this code in SPL where
@@ -442,8 +444,7 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
if (!ops->mem_ops || !ops->mem_ops->exec_op) {
unsigned int len;
- len = sizeof(op->cmd.opcode) + op->addr.nbytes +
- op->dummy.nbytes;
+ len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
if (slave->max_write_size && len > slave->max_write_size)
return -EINVAL;
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 8bd4459674..fe249f77ba 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -17,6 +17,7 @@ struct udevice;
{ \
.buswidth = __buswidth, \
.opcode = __opcode, \
+ .nbytes = 1, \
}
#define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \
@@ -69,6 +70,8 @@ enum spi_mem_data_dir {
/**
* struct spi_mem_op - describes a SPI memory operation
+ * @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is
+ * sent MSB-first.
* @cmd.buswidth: number of IO lines used to transmit the command
* @cmd.opcode: operation opcode
* @cmd.dtr: whether the command opcode should be sent in DTR mode or not
@@ -92,9 +95,10 @@ enum spi_mem_data_dir {
*/
struct spi_mem_op {
struct {
+ u8 nbytes;
u8 buswidth;
- u8 opcode;
u8 dtr : 1;
+ u16 opcode;
} cmd;
struct {
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 03/27] spi: spi-mem: export spi_mem_default_supports_op()
Date: Sat, 26 Jun 2021 00:47:05 +0530
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Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Reviewed-by: Sean Anderson
Signed-off-by: Pratyush Yadav
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index fe249f77ba..de3c11c8e2 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -250,6 +250,9 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op);
bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op);
+bool spi_mem_default_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op);
+
int spi_mem_exec_op(struct spi_slave *slave, const struct spi_mem_op *op);
bool spi_mem_default_supports_op(struct spi_slave *mem,
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
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Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 04/27] spi: spi-mem: add spi_mem_dtr_supports_op()
Date: Sat, 26 Jun 2021 00:47:06 +0530
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spi_mem_default_supports_op() rejects DTR ops by default to ensure that
the controller drivers that haven't been updated with DTR support
continue to reject them. It also makes sure that controllers that don't
support DTR mode at all (which is most of them at the moment) also
reject them.
This means that controller drivers that want to support DTR mode can't
use spi_mem_default_supports_op(). Driver authors have to roll their own
supports_op() function and mimic the buswidth checks. Or even worse,
driver authors might skip it completely or get it wrong.
Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 32 +++++++++++++++++++++++++++++---
include/spi-mem.h | 2 ++
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 541cd0e5a7..9c1ede1b61 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -145,8 +145,8 @@ static int spi_check_buswidth_req(struct spi_slave *slave, u8 buswidth, bool tx)
return -ENOTSUPP;
}
-bool spi_mem_default_supports_op(struct spi_slave *slave,
- const struct spi_mem_op *op)
+static bool spi_mem_check_buswidth(struct spi_slave *slave,
+ const struct spi_mem_op *op)
{
if (spi_check_buswidth_req(slave, op->cmd.buswidth, true))
return false;
@@ -164,13 +164,39 @@ bool spi_mem_default_supports_op(struct spi_slave *slave,
op->data.dir == SPI_MEM_DATA_OUT))
return false;
+ return true;
+}
+
+bool spi_mem_dtr_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ if (op->cmd.buswidth == 8 && op->cmd.nbytes % 2)
+ return false;
+
+ if (op->addr.nbytes && op->addr.buswidth == 8 && op->addr.nbytes % 2)
+ return false;
+
+ if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2)
+ return false;
+
+ if (op->data.dir != SPI_MEM_NO_DATA &&
+ op->dummy.buswidth == 8 && op->data.nbytes % 2)
+ return false;
+
+ return spi_mem_check_buswidth(slave, op);
+}
+EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op);
+
+bool spi_mem_default_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
return false;
if (op->cmd.nbytes != 1)
return false;
- return true;
+ return spi_mem_check_buswidth(slave, op);
}
EXPORT_SYMBOL_GPL(spi_mem_default_supports_op);
diff --git a/include/spi-mem.h b/include/spi-mem.h
index de3c11c8e2..32ffdc2e0f 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -249,6 +249,8 @@ spi_controller_dma_unmap_mem_op_data(struct spi_controller *ctlr,
int spi_mem_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op);
bool spi_mem_supports_op(struct spi_slave *slave, const struct spi_mem_op *op);
+bool spi_mem_dtr_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op);
bool spi_mem_default_supports_op(struct spi_slave *slave,
const struct spi_mem_op *op);
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 05/27] spi: cadence-qspi: Do not calibrate when device
tree sets read delay
Date: Sat, 26 Jun 2021 00:47:07 +0530
Message-ID: <20210625191729.31798-6-p.yadav@ti.com>
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If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 26 +++++++++++++++++++++-----
drivers/spi/cadence_qspi.h | 1 +
2 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 67980431ba..de7628de27 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -141,12 +141,20 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz)
cadence_qspi_apb_controller_disable(priv->regbase);
/*
- * Calibration required for different current SCLK speed, requested
- * SCLK speed or chip select
+ * If the device tree already provides a read delay value, use that
+ * instead of calibrating.
*/
- if (priv->previous_hz != hz ||
- priv->qspi_calibrated_hz != hz ||
- priv->qspi_calibrated_cs != spi_chip_select(bus)) {
+ if (plat->read_delay >= 0) {
+ cadence_spi_write_speed(bus, hz);
+ cadence_qspi_apb_readdata_capture(priv->regbase, 1,
+ plat->read_delay);
+ } else if (priv->previous_hz != hz ||
+ priv->qspi_calibrated_hz != hz ||
+ priv->qspi_calibrated_cs != spi_chip_select(bus)) {
+ /*
+ * Calibration required for different current SCLK speed,
+ * requested SCLK speed or chip select
+ */
err = spi_calibration(bus, hz);
if (err)
return err;
@@ -320,6 +328,14 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
255);
plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
+ /*
+ * Read delay should be an unsigned value but we use a signed integer
+ * so that negative values can indicate that the device tree did not
+ * specify any signed values and we need to perform the calibration
+ * sequence to find it out.
+ */
+ plat->read_delay = ofnode_read_s32_default(subnode, "cdns,read-delay",
+ -1);
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 64c5867609..b06d7750e2 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -26,6 +26,7 @@ struct cadence_spi_plat {
u32 trigger_address;
fdt_addr_t ahbsize;
bool use_dac_mode;
+ int read_delay;
/* Flash parameters */
u32 page_size;
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 06/27] spi: cadence-qspi: Add a small delay before
indirect writes
Date: Sat, 26 Jun 2021 00:47:08 +0530
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Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 4 ++++
drivers/spi/cadence_qspi.h | 1 +
drivers/spi/cadence_qspi_apb.c | 6 ++++++
3 files changed, 11 insertions(+)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index de7628de27..a961193cdc 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -20,6 +20,8 @@
#include
#include "cadence_qspi.h"
+#define NSEC_PER_SEC 1000000000L
+
#define CQSPI_STIG_READ 0
#define CQSPI_STIG_WRITE 1
#define CQSPI_READ 2
@@ -208,6 +210,8 @@ static int cadence_spi_probe(struct udevice *bus)
priv->qspi_is_init = 1;
}
+ plat->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, plat->ref_clk_hz);
+
return 0;
}
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index b06d7750e2..5c745541a6 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -27,6 +27,7 @@ struct cadence_spi_plat {
fdt_addr_t ahbsize;
bool use_dac_mode;
int read_delay;
+ u32 wr_delay;
/* Flash parameters */
u32 page_size;
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index b051f462ed..92e57730bd 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -730,6 +730,12 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
writel(CQSPI_REG_INDIRECTWR_START,
plat->regbase + CQSPI_REG_INDIRECTWR);
+ /*
+ * Some delay is required for the above bit to be internally
+ * synchronized by the QSPI module.
+ */
+ ndelay(plat->wr_delay);
+
while (remaining > 0) {
write_bytes = remaining > page_size ? page_size : remaining;
writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 07/27] spi: cadence-qspi: Add support for octal DTR
flashes
Date: Sat, 26 Jun 2021 00:47:09 +0530
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Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can not use
automatic write completion polling in DTR mode. Further, no write
completion polling makes it impossible to use DAC mode for DTR writes.
In that mode, the controller does not know beforehand how long a write
will be and so it can de-assert Chip Select (CS#) at any time. Once CS#
is de-assert, the flash will go into burning phase. But since the
controller does not do write completion polling, it does not know when
the flash is busy and might send in writes while the flash is not ready.
So, disable write completion polling and make writes go through indirect
mode for DTR writes and let spi-mem take care of polling the SR.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 39 ++++-
drivers/spi/cadence_qspi.h | 14 +-
drivers/spi/cadence_qspi_apb.c | 286 ++++++++++++++++++++++++++++++---
3 files changed, 313 insertions(+), 26 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index a961193cdc..d1b3808c4d 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -43,20 +43,22 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
return 0;
}
-static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
+static int cadence_spi_read_id(struct cadence_spi_plat *plat, u8 len,
+ u8 *idcode)
{
struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(len, idcode, 1));
- return cadence_qspi_apb_command_read(reg_base, &op);
+ return cadence_qspi_apb_command_read(plat, &op);
}
/* Calibration sequence to determine the read data capture delay register */
static int spi_calibration(struct udevice *bus, uint hz)
{
struct cadence_spi_priv *priv = dev_get_priv(bus);
+ struct cadence_spi_plat *plat = dev_get_plat(bus);
void *base = priv->regbase;
unsigned int idcode = 0, temp = 0;
int err = 0, i, range_lo = -1, range_hi = -1;
@@ -71,7 +73,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
cadence_qspi_apb_controller_enable(base);
/* read the ID which will be our golden value */
- err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
+ err = cadence_spi_read_id(plat, 3, (u8 *)&idcode);
if (err) {
puts("SF: Calibration failed (read)\n");
return err;
@@ -90,7 +92,7 @@ static int spi_calibration(struct udevice *bus, uint hz)
cadence_qspi_apb_controller_enable(base);
/* issue a RDID to get the ID value */
- err = cadence_spi_read_id(base, 3, (u8 *)&temp);
+ err = cadence_spi_read_id(plat, 3, (u8 *)&temp);
if (err) {
puts("SF: Calibration failed (read)\n");
return err;
@@ -271,10 +273,14 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
switch (mode) {
case CQSPI_STIG_READ:
- err = cadence_qspi_apb_command_read(base, op);
+ err = cadence_qspi_apb_command_read_setup(plat, op);
+ if (!err)
+ err = cadence_qspi_apb_command_read(plat, op);
break;
case CQSPI_STIG_WRITE:
- err = cadence_qspi_apb_command_write(base, op);
+ err = cadence_qspi_apb_command_write_setup(plat, op);
+ if (!err)
+ err = cadence_qspi_apb_command_write(plat, op);
break;
case CQSPI_READ:
err = cadence_qspi_apb_read_setup(plat, op);
@@ -294,6 +300,26 @@ static int cadence_spi_mem_exec_op(struct spi_slave *spi,
return err;
}
+static bool cadence_spi_mem_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ bool all_true, all_false;
+
+ all_true = op->cmd.dtr && op->addr.dtr && op->dummy.dtr &&
+ op->data.dtr;
+ all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
+ !op->data.dtr;
+
+ /* Mixed DTR modes not supported. */
+ if (!(all_true || all_false))
+ return false;
+
+ if (all_true)
+ return spi_mem_dtr_supports_op(slave, op);
+ else
+ return spi_mem_default_supports_op(slave, op);
+}
+
static int cadence_spi_of_to_plat(struct udevice *bus)
{
struct cadence_spi_plat *plat = dev_get_plat(bus);
@@ -350,6 +376,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus)
static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
.exec_op = cadence_spi_mem_exec_op,
+ .supports_op = cadence_spi_mem_supports_op,
};
static const struct dm_spi_ops cadence_spi_ops = {
diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 5c745541a6..49b401168f 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -36,6 +36,12 @@ struct cadence_spi_plat {
u32 tsd2d_ns;
u32 tchsh_ns;
u32 tslch_ns;
+
+ /* Transaction protocol parameters. */
+ u8 inst_width;
+ u8 addr_width;
+ u8 data_width;
+ bool dtr;
};
struct cadence_spi_priv {
@@ -59,9 +65,13 @@ void cadence_qspi_apb_controller_enable(void *reg_base_addr);
void cadence_qspi_apb_controller_disable(void *reg_base_addr);
void cadence_qspi_apb_dac_mode_enable(void *reg_base);
-int cadence_qspi_apb_command_read(void *reg_base_addr,
+int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op);
+int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
-int cadence_qspi_apb_command_write(void *reg_base_addr,
+int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op);
+int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat,
const struct spi_mem_op *op);
int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 92e57730bd..c36a652211 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -51,7 +51,7 @@
#define CQSPI_STIG_DATA_LEN_MAX 8
#define CQSPI_DUMMY_CLKS_PER_BYTE 8
-#define CQSPI_DUMMY_BYTES_MAX 4
+#define CQSPI_DUMMY_CLKS_MAX 31
/****************************************************************************
* Controller's configuration and status register (offset from QSPI_BASE)
@@ -65,6 +65,8 @@
#define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_BAUD_LSB 19
+#define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
+#define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
#define CQSPI_REG_CONFIG_IDLE_LSB 31
#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
@@ -83,6 +85,7 @@
#define CQSPI_REG_WR_INSTR 0x08
#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
+#define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
#define CQSPI_REG_DELAY 0x0C
@@ -120,6 +123,9 @@
#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
+#define CQSPI_REG_WR_COMPLETION_CTRL 0x38
+#define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
+
#define CQSPI_REG_IRQSTATUS 0x40
#define CQSPI_REG_IRQMASK 0x44
@@ -166,6 +172,11 @@
#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
+#define CQSPI_REG_OP_EXT_LOWER 0xE0
+#define CQSPI_REG_OP_EXT_READ_LSB 24
+#define CQSPI_REG_OP_EXT_WRITE_LSB 16
+#define CQSPI_REG_OP_EXT_STIG_LSB 0
+
#define CQSPI_REG_IS_IDLE(base) \
((readl(base + CQSPI_REG_CONFIG) >> \
CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
@@ -203,6 +214,75 @@ void cadence_qspi_apb_dac_mode_enable(void *reg_base)
writel(reg, reg_base + CQSPI_REG_CONFIG);
}
+static unsigned int cadence_qspi_calc_dummy(const struct spi_mem_op *op,
+ bool dtr)
+{
+ unsigned int dummy_clk;
+
+ dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
+ if (dtr)
+ dummy_clk /= 2;
+
+ return dummy_clk;
+}
+
+static u32 cadence_qspi_calc_rdreg(struct cadence_spi_plat *plat)
+{
+ u32 rdreg = 0;
+
+ rdreg |= plat->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
+ rdreg |= plat->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
+ rdreg |= plat->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
+
+ return rdreg;
+}
+
+static int cadence_qspi_buswidth_to_inst_type(u8 buswidth)
+{
+ switch (buswidth) {
+ case 0:
+ case 1:
+ return CQSPI_INST_TYPE_SINGLE;
+
+ case 2:
+ return CQSPI_INST_TYPE_DUAL;
+
+ case 4:
+ return CQSPI_INST_TYPE_QUAD;
+
+ case 8:
+ return CQSPI_INST_TYPE_OCTAL;
+
+ default:
+ return -ENOTSUPP;
+ }
+}
+
+static int cadence_qspi_set_protocol(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op)
+{
+ int ret;
+
+ plat->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
+
+ ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
+ if (ret < 0)
+ return ret;
+ plat->inst_width = ret;
+
+ ret = cadence_qspi_buswidth_to_inst_type(op->addr.buswidth);
+ if (ret < 0)
+ return ret;
+ plat->addr_width = ret;
+
+ ret = cadence_qspi_buswidth_to_inst_type(op->data.buswidth);
+ if (ret < 0)
+ return ret;
+ plat->data_width = ret;
+
+ return 0;
+}
+
/* Return 1 if idle, otherwise return 0 (busy). */
static unsigned int cadence_qspi_wait_idle(void *reg_base)
{
@@ -434,21 +514,109 @@ static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
return 0;
}
+static int cadence_qspi_setup_opcode_ext(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op,
+ unsigned int shift)
+{
+ unsigned int reg;
+ u8 ext;
+
+ if (op->cmd.nbytes != 2)
+ return -EINVAL;
+
+ /* Opcode extension is the LSB. */
+ ext = op->cmd.opcode & 0xff;
+
+ reg = readl(plat->regbase + CQSPI_REG_OP_EXT_LOWER);
+ reg &= ~(0xff << shift);
+ reg |= ext << shift;
+ writel(reg, plat->regbase + CQSPI_REG_OP_EXT_LOWER);
+
+ return 0;
+}
+
+static int cadence_qspi_enable_dtr(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op,
+ unsigned int shift,
+ bool enable)
+{
+ unsigned int reg;
+ int ret;
+
+ reg = readl(plat->regbase + CQSPI_REG_CONFIG);
+
+ if (enable) {
+ reg |= CQSPI_REG_CONFIG_DTR_PROTO;
+ reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
+
+ /* Set up command opcode extension. */
+ ret = cadence_qspi_setup_opcode_ext(plat, op, shift);
+ if (ret)
+ return ret;
+ } else {
+ reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
+ reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
+ }
+
+ writel(reg, plat->regbase + CQSPI_REG_CONFIG);
+
+ return 0;
+}
+
+int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op)
+{
+ int ret;
+ unsigned int reg;
+
+ ret = cadence_qspi_set_protocol(plat, op);
+ if (ret)
+ return ret;
+
+ ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_STIG_LSB,
+ plat->dtr);
+ if (ret)
+ return ret;
+
+ reg = cadence_qspi_calc_rdreg(plat);
+ writel(reg, plat->regbase + CQSPI_REG_RD_INSTR);
+
+ return 0;
+}
+
/* For command RDID, RDSR. */
-int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
+int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op)
{
+ void *reg_base = plat->regbase;
unsigned int reg;
unsigned int read_len;
int status;
unsigned int rxlen = op->data.nbytes;
void *rxbuf = op->data.buf.in;
+ unsigned int dummy_clk;
+ u8 opcode;
if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
return -EINVAL;
}
- reg = op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+ if (plat->dtr)
+ opcode = op->cmd.opcode >> 8;
+ else
+ opcode = op->cmd.opcode;
+
+ reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+
+ /* Set up dummy cycles. */
+ dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr);
+ if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
+ return -ENOTSUPP;
+
+ if (dummy_clk)
+ reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
+ << CQSPI_REG_CMDCTRL_DUMMY_LSB;
reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
@@ -475,15 +643,39 @@ int cadence_qspi_apb_command_read(void *reg_base, const struct spi_mem_op *op)
return 0;
}
+int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op)
+{
+ int ret;
+ unsigned int reg;
+
+ ret = cadence_qspi_set_protocol(plat, op);
+ if (ret)
+ return ret;
+
+ ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_STIG_LSB,
+ plat->dtr);
+ if (ret)
+ return ret;
+
+ reg = cadence_qspi_calc_rdreg(plat);
+ writel(reg, plat->regbase + CQSPI_REG_RD_INSTR);
+
+ return 0;
+}
+
/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
-int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
+int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat,
+ const struct spi_mem_op *op)
{
unsigned int reg = 0;
unsigned int wr_data;
unsigned int wr_len;
unsigned int txlen = op->data.nbytes;
const void *txbuf = op->data.buf.out;
+ void *reg_base = plat->regbase;
u32 addr;
+ u8 opcode;
/* Reorder address to SPI bus order if only transferring address */
if (!txlen) {
@@ -499,7 +691,12 @@ int cadence_qspi_apb_command_write(void *reg_base, const struct spi_mem_op *op)
return -EINVAL;
}
- reg |= op->cmd.opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
+ if (plat->dtr)
+ opcode = op->cmd.opcode >> 8;
+ else
+ opcode = op->cmd.opcode;
+
+ reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
if (txlen) {
/* writing data = yes */
@@ -533,29 +730,39 @@ int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
unsigned int rd_reg;
unsigned int dummy_clk;
unsigned int dummy_bytes = op->dummy.nbytes;
+ int ret;
+ u8 opcode;
+
+ ret = cadence_qspi_set_protocol(plat, op);
+ if (ret)
+ return ret;
+
+ ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_READ_LSB,
+ plat->dtr);
+ if (ret)
+ return ret;
/* Setup the indirect trigger address */
writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
- rd_reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
+ if (plat->dtr)
+ opcode = op->cmd.opcode >> 8;
+ else
+ opcode = op->cmd.opcode;
- if (op->data.buswidth == 8)
- /* Instruction and address at DQ0, data at DQ0-7. */
- rd_reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
- else if (op->data.buswidth == 4)
- /* Instruction and address at DQ0, data at DQ0-3. */
- rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
+ rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
+ rd_reg |= cadence_qspi_calc_rdreg(plat);
writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
if (dummy_bytes) {
- if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
- dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
-
/* Convert to clock cycles. */
- dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
+ dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr);
+
+ if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
+ return -ENOTSUPP;
if (dummy_clk)
rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
@@ -682,17 +889,52 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
const struct spi_mem_op *op)
{
unsigned int reg;
+ int ret;
+ u8 opcode;
+
+ ret = cadence_qspi_set_protocol(plat, op);
+ if (ret)
+ return ret;
+
+ ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_WRITE_LSB,
+ plat->dtr);
+ if (ret)
+ return ret;
/* Setup the indirect trigger address */
writel(plat->trigger_address,
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure the opcode */
- reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
+ if (plat->dtr)
+ opcode = op->cmd.opcode >> 8;
+ else
+ opcode = op->cmd.opcode;
+
+ reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
+ reg |= plat->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
+ reg |= plat->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
+ reg = cadence_qspi_calc_rdreg(plat);
+ writel(reg, plat->regbase + CQSPI_REG_RD_INSTR);
+
writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
+ if (plat->dtr) {
+ /*
+ * Some flashes like the cypress Semper flash expect a 4-byte
+ * dummy address with the Read SR command in DTR mode, but this
+ * controller does not support sending address with the Read SR
+ * command. So, disable write completion polling on the
+ * controller's side. spi-nor will take care of polling the
+ * status register.
+ */
+ reg = readl(plat->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
+ reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
+ writel(reg, plat->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
+ }
+
reg = readl(plat->regbase + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
reg |= (op->addr.nbytes - 1);
@@ -787,7 +1029,15 @@ int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
const void *buf = op->data.buf.out;
size_t len = op->data.nbytes;
- if (plat->use_dac_mode && (to + len < plat->ahbsize)) {
+ /*
+ * Some flashes like the Cypress Semper flash expect a dummy 4-byte
+ * address (all 0s) with the read status register command in DTR mode.
+ * But this controller does not support sending dummy address bytes to
+ * the flash when it is polling the write completion register in DTR
+ * mode. So, we can not use direct mode when in DTR mode for writing
+ * data.
+ */
+ if (!plat->dtr && plat->use_dac_mode && (to + len < plat->ahbsize)) {
memcpy_toio(plat->ahbbase + to, buf, len);
if (!cadence_qspi_wait_idle(plat->regbase))
return -EIO;
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 08/27] mtd: spi-nor-core: Fix address width on flash chips
> 16MB
Date: Sat, 26 Jun 2021 00:47:10 +0530
Message-ID: <20210625191729.31798-9-p.yadav@ti.com>
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If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.
The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.
Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6af9c675a4..bfe7ea55c4 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2603,7 +2603,11 @@ int spi_nor_scan(struct spi_nor *nor)
/* already configured from SFDP */
} else if (info->addr_width) {
nor->addr_width = info->addr_width;
- } else if (mtd->size > SZ_16M) {
+ } else {
+ nor->addr_width = 3;
+ }
+
+ if (nor->addr_width == 3 && mtd->size > SZ_16M) {
#ifndef CONFIG_SPI_FLASH_BAR
/* enable 4-byte addressing if the device exceeds 16MiB */
nor->addr_width = 4;
@@ -2617,8 +2621,6 @@ int spi_nor_scan(struct spi_nor *nor)
if (ret < 0)
return ret;
#endif
- } else {
- nor->addr_width = 3;
}
if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) {
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 09/27] mtd: spi-nor-core: Add a ->setup() hook
Date: Sat, 26 Jun 2021 00:47:11 +0530
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nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to avoid forward declarations.
Inspired by the Linux kernel's setup() hook.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 84 +++------------
drivers/mtd/spi/spi-nor-tiny.c | 22 ----
include/linux/mtd/spi-nor.h | 192 ++++++++++++++++++++++-----------
3 files changed, 147 insertions(+), 151 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index bfe7ea55c4..b782709f14 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1451,71 +1451,6 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
#endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
#endif /* CONFIG_SPI_FLASH_SPANSION */
-struct spi_nor_read_command {
- u8 num_mode_clocks;
- u8 num_wait_states;
- u8 opcode;
- enum spi_nor_protocol proto;
-};
-
-struct spi_nor_pp_command {
- u8 opcode;
- enum spi_nor_protocol proto;
-};
-
-enum spi_nor_read_command_index {
- SNOR_CMD_READ,
- SNOR_CMD_READ_FAST,
- SNOR_CMD_READ_1_1_1_DTR,
-
- /* Dual SPI */
- SNOR_CMD_READ_1_1_2,
- SNOR_CMD_READ_1_2_2,
- SNOR_CMD_READ_2_2_2,
- SNOR_CMD_READ_1_2_2_DTR,
-
- /* Quad SPI */
- SNOR_CMD_READ_1_1_4,
- SNOR_CMD_READ_1_4_4,
- SNOR_CMD_READ_4_4_4,
- SNOR_CMD_READ_1_4_4_DTR,
-
- /* Octo SPI */
- SNOR_CMD_READ_1_1_8,
- SNOR_CMD_READ_1_8_8,
- SNOR_CMD_READ_8_8_8,
- SNOR_CMD_READ_1_8_8_DTR,
-
- SNOR_CMD_READ_MAX
-};
-
-enum spi_nor_pp_command_index {
- SNOR_CMD_PP,
-
- /* Quad SPI */
- SNOR_CMD_PP_1_1_4,
- SNOR_CMD_PP_1_4_4,
- SNOR_CMD_PP_4_4_4,
-
- /* Octo SPI */
- SNOR_CMD_PP_1_1_8,
- SNOR_CMD_PP_1_8_8,
- SNOR_CMD_PP_8_8_8,
-
- SNOR_CMD_PP_MAX
-};
-
-struct spi_nor_flash_parameter {
- u64 size;
- u32 page_size;
-
- struct spi_nor_hwcaps hwcaps;
- struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
- struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
-
- int (*quad_enable)(struct spi_nor *nor);
-};
-
static void
spi_nor_set_read_settings(struct spi_nor_read_command *read,
u8 num_mode_clocks,
@@ -2377,9 +2312,10 @@ static int spi_nor_select_erase(struct spi_nor *nor,
return 0;
}
-static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
- const struct spi_nor_flash_parameter *params,
- const struct spi_nor_hwcaps *hwcaps)
+static int spi_nor_default_setup(struct spi_nor *nor,
+ const struct flash_info *info,
+ const struct spi_nor_flash_parameter *params,
+ const struct spi_nor_hwcaps *hwcaps)
{
u32 ignored_mask, shared_mask;
bool enable_quad_io;
@@ -2438,6 +2374,16 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
return 0;
}
+static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info,
+ const struct spi_nor_flash_parameter *params,
+ const struct spi_nor_hwcaps *hwcaps)
+{
+ if (!nor->setup)
+ return 0;
+
+ return nor->setup(nor, info, params, hwcaps);
+}
+
static int spi_nor_init(struct spi_nor *nor)
{
int err;
@@ -2504,6 +2450,8 @@ int spi_nor_scan(struct spi_nor *nor)
nor->read_reg = spi_nor_read_reg;
nor->write_reg = spi_nor_write_reg;
+ nor->setup = spi_nor_default_setup;
+
if (spi->mode & SPI_RX_OCTAL) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c
index b0aa97d324..70061f1a61 100644
--- a/drivers/mtd/spi/spi-nor-tiny.c
+++ b/drivers/mtd/spi/spi-nor-tiny.c
@@ -555,28 +555,6 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
}
#endif /* CONFIG_SPI_FLASH_SPANSION */
-struct spi_nor_read_command {
- u8 num_mode_clocks;
- u8 num_wait_states;
- u8 opcode;
- enum spi_nor_protocol proto;
-};
-
-enum spi_nor_read_command_index {
- SNOR_CMD_READ,
- SNOR_CMD_READ_FAST,
-
- /* Quad SPI */
- SNOR_CMD_READ_1_1_4,
-
- SNOR_CMD_READ_MAX
-};
-
-struct spi_nor_flash_parameter {
- struct spi_nor_hwcaps hwcaps;
- struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
-};
-
static void
spi_nor_set_read_settings(struct spi_nor_read_command *read,
u8 num_mode_clocks,
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index c3e38e499e..47a2eced69 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -249,6 +249,134 @@ enum spi_nor_option_flags {
SNOR_F_BROKEN_RESET = BIT(6),
};
+struct spi_nor;
+
+/**
+ * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
+ * supported by the SPI controller (bus master).
+ * @mask: the bitmask listing all the supported hw capabilies
+ */
+struct spi_nor_hwcaps {
+ u32 mask;
+};
+
+/*
+ *(Fast) Read capabilities.
+ * MUST be ordered by priority: the higher bit position, the higher priority.
+ * As a matter of performances, it is relevant to use Octo SPI protocols first,
+ * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
+ * (Slow) Read.
+ */
+#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
+#define SNOR_HWCAPS_READ BIT(0)
+#define SNOR_HWCAPS_READ_FAST BIT(1)
+#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
+
+#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
+#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
+#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
+#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
+#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
+
+#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
+#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
+#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
+#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
+#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
+
+#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
+#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
+#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
+#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
+#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
+
+/*
+ * Page Program capabilities.
+ * MUST be ordered by priority: the higher bit position, the higher priority.
+ * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
+ * legacy SPI 1-1-1 protocol.
+ * Note that Dual Page Programs are not supported because there is no existing
+ * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
+ * implements such commands.
+ */
+#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
+#define SNOR_HWCAPS_PP BIT(16)
+
+#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
+#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
+#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
+#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
+
+#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
+#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
+#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
+#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
+
+struct spi_nor_read_command {
+ u8 num_mode_clocks;
+ u8 num_wait_states;
+ u8 opcode;
+ enum spi_nor_protocol proto;
+};
+
+struct spi_nor_pp_command {
+ u8 opcode;
+ enum spi_nor_protocol proto;
+};
+
+enum spi_nor_read_command_index {
+ SNOR_CMD_READ,
+ SNOR_CMD_READ_FAST,
+ SNOR_CMD_READ_1_1_1_DTR,
+
+ /* Dual SPI */
+ SNOR_CMD_READ_1_1_2,
+ SNOR_CMD_READ_1_2_2,
+ SNOR_CMD_READ_2_2_2,
+ SNOR_CMD_READ_1_2_2_DTR,
+
+ /* Quad SPI */
+ SNOR_CMD_READ_1_1_4,
+ SNOR_CMD_READ_1_4_4,
+ SNOR_CMD_READ_4_4_4,
+ SNOR_CMD_READ_1_4_4_DTR,
+
+ /* Octo SPI */
+ SNOR_CMD_READ_1_1_8,
+ SNOR_CMD_READ_1_8_8,
+ SNOR_CMD_READ_8_8_8,
+ SNOR_CMD_READ_1_8_8_DTR,
+
+ SNOR_CMD_READ_MAX
+};
+
+enum spi_nor_pp_command_index {
+ SNOR_CMD_PP,
+
+ /* Quad SPI */
+ SNOR_CMD_PP_1_1_4,
+ SNOR_CMD_PP_1_4_4,
+ SNOR_CMD_PP_4_4_4,
+
+ /* Octo SPI */
+ SNOR_CMD_PP_1_1_8,
+ SNOR_CMD_PP_1_8_8,
+ SNOR_CMD_PP_8_8_8,
+
+ SNOR_CMD_PP_MAX
+};
+
+struct spi_nor_flash_parameter {
+ u64 size;
+ u32 page_size;
+
+ struct spi_nor_hwcaps hwcaps;
+ struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
+ struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
+
+ int (*quad_enable)(struct spi_nor *nor);
+};
+
/**
* struct flash_info - Forward declaration of a structure used internally by
* spi_nor_scan()
@@ -330,6 +458,9 @@ struct spi_nor {
u32 flags;
u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
+ int (*setup)(struct spi_nor *nor, const struct flash_info *info,
+ const struct spi_nor_flash_parameter *params,
+ const struct spi_nor_hwcaps *hwcaps);
int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
@@ -368,67 +499,6 @@ device_node *spi_nor_get_flash_node(struct spi_nor *nor)
}
#endif /* __UBOOT__ */
-/**
- * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
- * supported by the SPI controller (bus master).
- * @mask: the bitmask listing all the supported hw capabilies
- */
-struct spi_nor_hwcaps {
- u32 mask;
-};
-
-/*
- *(Fast) Read capabilities.
- * MUST be ordered by priority: the higher bit position, the higher priority.
- * As a matter of performances, it is relevant to use Octo SPI protocols first,
- * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
- * (Slow) Read.
- */
-#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
-#define SNOR_HWCAPS_READ BIT(0)
-#define SNOR_HWCAPS_READ_FAST BIT(1)
-#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
-
-#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
-#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
-#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
-#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
-#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
-
-#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
-#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
-#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
-#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
-#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
-
-#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
-#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
-#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
-#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
-#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
-
-/*
- * Page Program capabilities.
- * MUST be ordered by priority: the higher bit position, the higher priority.
- * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
- * legacy SPI 1-1-1 protocol.
- * Note that Dual Page Programs are not supported because there is no existing
- * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
- * implements such commands.
- */
-#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
-#define SNOR_HWCAPS_PP BIT(16)
-
-#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
-#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
-#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
-#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
-
-#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
-#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
-#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
-#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
-
/**
* spi_nor_scan() - scan the SPI NOR
* @nor: the spi_nor structure
From patchwork Fri Jun 25 19:17:12 2021
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From: Pratyush Yadav
To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 10/27] mtd: spi-nor-core: Move SFDP related declarations
to top
Date: Sat, 26 Jun 2021 00:47:12 +0530
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These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224 ++++++++++++++++-----------------
1 file changed, 112 insertions(+), 112 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b782709f14..312628c080 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -40,6 +40,118 @@
#define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ)
+struct sfdp_parameter_header {
+ u8 id_lsb;
+ u8 minor;
+ u8 major;
+ u8 length; /* in double words */
+ u8 parameter_table_pointer[3]; /* byte address */
+ u8 id_msb;
+};
+
+#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
+#define SFDP_PARAM_HEADER_PTP(p) \
+ (((p)->parameter_table_pointer[2] << 16) | \
+ ((p)->parameter_table_pointer[1] << 8) | \
+ ((p)->parameter_table_pointer[0] << 0))
+
+#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
+#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
+#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
+
+#define SFDP_SIGNATURE 0x50444653U
+#define SFDP_JESD216_MAJOR 1
+#define SFDP_JESD216_MINOR 0
+#define SFDP_JESD216A_MINOR 5
+#define SFDP_JESD216B_MINOR 6
+
+struct sfdp_header {
+ u32 signature; /* Ox50444653U <=> "SFDP" */
+ u8 minor;
+ u8 major;
+ u8 nph; /* 0-base number of parameter headers */
+ u8 unused;
+
+ /* Basic Flash Parameter Table. */
+ struct sfdp_parameter_header bfpt_header;
+};
+
+/* Basic Flash Parameter Table */
+
+/*
+ * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
+ * They are indexed from 1 but C arrays are indexed from 0.
+ */
+#define BFPT_DWORD(i) ((i) - 1)
+#define BFPT_DWORD_MAX 16
+
+/* The first version of JESB216 defined only 9 DWORDs. */
+#define BFPT_DWORD_MAX_JESD216 9
+
+/* 1st DWORD. */
+#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
+#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
+#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
+#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
+#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
+#define BFPT_DWORD1_DTR BIT(19)
+#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
+#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
+#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
+
+/* 5th DWORD. */
+#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
+#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
+
+/* 11th DWORD. */
+#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
+#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
+
+/* 15th DWORD. */
+
+/*
+ * (from JESD216 rev B)
+ * Quad Enable Requirements (QER):
+ * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
+ * reads based on instruction. DQ3/HOLD# functions are hold during
+ * instruction phase.
+ * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
+ * two data bytes where bit 1 of the second byte is one.
+ * [...]
+ * Writing only one byte to the status register has the side-effect of
+ * clearing status register 2, including the QE bit. The 100b code is
+ * used if writing one byte to the status register does not modify
+ * status register 2.
+ * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
+ * one data byte where bit 6 is one.
+ * [...]
+ * - 011b: QE is bit 7 of status register 2. It is set via Write status
+ * register 2 instruction 3Eh with one data byte where bit 7 is one.
+ * [...]
+ * The status register 2 is read using instruction 3Fh.
+ * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
+ * two data bytes where bit 1 of the second byte is one.
+ * [...]
+ * In contrast to the 001b code, writing one byte to the status
+ * register does not modify status register 2.
+ * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
+ * Read Status instruction 05h. Status register2 is read using
+ * instruction 35h. QE is set via Writ Status instruction 01h with
+ * two data bytes where bit 1 of the second byte is one.
+ * [...]
+ */
+#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
+#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
+#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
+#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
+#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
+#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
+#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
+
+struct sfdp_bfpt {
+ u32 dwords[BFPT_DWORD_MAX];
+};
+
static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op
*op, void *buf)
{
@@ -1528,118 +1640,6 @@ read_err:
return ret;
}
-struct sfdp_parameter_header {
- u8 id_lsb;
- u8 minor;
- u8 major;
- u8 length; /* in double words */
- u8 parameter_table_pointer[3]; /* byte address */
- u8 id_msb;
-};
-
-#define SFDP_PARAM_HEADER_ID(p) (((p)->id_msb << 8) | (p)->id_lsb)
-#define SFDP_PARAM_HEADER_PTP(p) \
- (((p)->parameter_table_pointer[2] << 16) | \
- ((p)->parameter_table_pointer[1] << 8) | \
- ((p)->parameter_table_pointer[0] << 0))
-
-#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
-#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
-#define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */
-
-#define SFDP_SIGNATURE 0x50444653U
-#define SFDP_JESD216_MAJOR 1
-#define SFDP_JESD216_MINOR 0
-#define SFDP_JESD216A_MINOR 5
-#define SFDP_JESD216B_MINOR 6
-
-struct sfdp_header {
- u32 signature; /* Ox50444653U <=> "SFDP" */
- u8 minor;
- u8 major;
- u8 nph; /* 0-base number of parameter headers */
- u8 unused;
-
- /* Basic Flash Parameter Table. */
- struct sfdp_parameter_header bfpt_header;
-};
-
-/* Basic Flash Parameter Table */
-
-/*
- * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs.
- * They are indexed from 1 but C arrays are indexed from 0.
- */
-#define BFPT_DWORD(i) ((i) - 1)
-#define BFPT_DWORD_MAX 16
-
-/* The first version of JESB216 defined only 9 DWORDs. */
-#define BFPT_DWORD_MAX_JESD216 9
-
-/* 1st DWORD. */
-#define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
-#define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17)
-#define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17)
-#define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17)
-#define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17)
-#define BFPT_DWORD1_DTR BIT(19)
-#define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
-#define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
-#define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
-
-/* 5th DWORD. */
-#define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
-#define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4)
-
-/* 11th DWORD. */
-#define BFPT_DWORD11_PAGE_SIZE_SHIFT 4
-#define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4)
-
-/* 15th DWORD. */
-
-/*
- * (from JESD216 rev B)
- * Quad Enable Requirements (QER):
- * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
- * reads based on instruction. DQ3/HOLD# functions are hold during
- * instruction phase.
- * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
- * two data bytes where bit 1 of the second byte is one.
- * [...]
- * Writing only one byte to the status register has the side-effect of
- * clearing status register 2, including the QE bit. The 100b code is
- * used if writing one byte to the status register does not modify
- * status register 2.
- * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
- * one data byte where bit 6 is one.
- * [...]
- * - 011b: QE is bit 7 of status register 2. It is set via Write status
- * register 2 instruction 3Eh with one data byte where bit 7 is one.
- * [...]
- * The status register 2 is read using instruction 3Fh.
- * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
- * two data bytes where bit 1 of the second byte is one.
- * [...]
- * In contrast to the 001b code, writing one byte to the status
- * register does not modify status register 2.
- * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
- * Read Status instruction 05h. Status register2 is read using
- * instruction 35h. QE is set via Writ Status instruction 01h with
- * two data bytes where bit 1 of the second byte is one.
- * [...]
- */
-#define BFPT_DWORD15_QER_MASK GENMASK(22, 20)
-#define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */
-#define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20)
-#define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */
-#define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20)
-#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)
-#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */
-
-struct sfdp_bfpt {
- u32 dwords[BFPT_DWORD_MAX];
-};
-
/* Fast Read settings. */
static void
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To: Jagan Teki , Vignesh R ,
Ryder Lee , Weijie Gao ,
Chunfeng Yun , GSS_MTK_Uboot_upstream
,
CC: Pratyush Yadav
Subject: [PATCH v10 11/27] mtd: spi-nor-core: Introduce flash-specific fixup
hooks
Date: Sat, 26 Jun 2021 00:47:13 +0530
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