From patchwork Tue Jan 23 17:56:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lina Iyer X-Patchwork-Id: 864927 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=codeaurora.org header.i=@codeaurora.org header.b="obaBiYLE"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=codeaurora.org header.i=@codeaurora.org header.b="obaBiYLE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zQwz13T46z9sBW for ; Wed, 24 Jan 2018 04:58:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752027AbeAWR6X (ORCPT ); Tue, 23 Jan 2018 12:58:23 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:60548 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751863AbeAWR5t (ORCPT ); Tue, 23 Jan 2018 12:57:49 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id B6495607A4; Tue, 23 Jan 2018 17:57:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516730268; bh=WWBjSp/4ZNjWAyL6yo3GP4bWgSu2STU+V3OjxjCJKSo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=obaBiYLEuSfCTofzZ0YIwohOqn184KKyBdkqry985YJLhyf1udQJa38wNzT2M/IXy QZMGDznH9Zsw9BPwU80TYrVZ98XbK9cHWMSWC3AuTW+1778Vjg6Ugu09wAmlWJO97C uIe5d1yixzib++mQ+ReLJnP/J0X3Nb1zEJb972gQ= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from codeaurora.org (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: ilina@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4841F6090E; Tue, 23 Jan 2018 17:57:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1516730268; bh=WWBjSp/4ZNjWAyL6yo3GP4bWgSu2STU+V3OjxjCJKSo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=obaBiYLEuSfCTofzZ0YIwohOqn184KKyBdkqry985YJLhyf1udQJa38wNzT2M/IXy QZMGDznH9Zsw9BPwU80TYrVZ98XbK9cHWMSWC3AuTW+1778Vjg6Ugu09wAmlWJO97C uIe5d1yixzib++mQ+ReLJnP/J0X3Nb1zEJb972gQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4841F6090E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilina@codeaurora.org From: Lina Iyer To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, sboyd@codeaurora.org, rnayak@codeaurora.org, asathyak@codeaurora.org, Lina Iyer , devicetree@vger.kernel.org Subject: [PATCH RFC 2/4] dt-bindings/interrupt-controller: pdc: descibe PDC device binding Date: Tue, 23 Jan 2018 10:56:54 -0700 Message-Id: <20180123175656.11942-3-ilina@codeaurora.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180123175656.11942-1-ilina@codeaurora.org> References: <20180123175656.11942-1-ilina@codeaurora.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Archana Sathyakumar Add device binding documentation for the PDC Interrupt controller on QCOM SoC's like the SDM845. The interrupt-controller can be used to sense edge low interrupts and wakeup interrupts when the GIC is non-operational. Cc: devicetree@vger.kernel.org Signed-off-by: Archana Sathyakumar Signed-off-by: Lina Iyer --- .../bindings/interrupt-controller/qcom,pdc.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt new file mode 100644 index 000000000000..c4592bbf678d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -0,0 +1,55 @@ +PDC interrupt controller + +Qualcomm Technologies Inc. SoCs based on the RPM Hardened archicture have a +Power Domain Controller (PDC) that is on always-on domain. In addition to +providing power control for the power domains, the hardware also has an +interrupt controller that can be used to help detect edge low interrupts as +well detect interrupts when the GIC is non-operational. + +GIC is parent interrupt controller at the highest level. Platform interrupt +controller PDC is next in hierarchy, followed by others. This driver only +configures the interrupts, does not handle them. + +Properties: + +- compatible: + Usage: required + Value type: + Definition: Should contain "qcom,pdc" and "qcom,pdc-" + - "qcom,pdc-sdm845": For sdm845 pin data + +- reg: + Usage: required + Value type: + Definition: Specifies the base physical address for PDC hardware. + +- interrupt-cells: + Usage: required + Value type: + Definition: Specifies the number of cells needed to encode an interrupt + source. + Value must be 3. + The encoding of these cells are same as described in [1]. + +- interrupt-parent: + Usage: required + Value type: + Definition: Specifies the interrupt parent necessary for hierarchical + domain to operate. + +- interrupt-controller: + Usage: required + Value type: + Definition: Identifies the node as an interrupt controller. + +Example: + + pdc: interrupt-controller@b220000 { + compatible = "qcom,pdc", "qcom,pdc-sdm845"; + reg = <0xb220000 0x30000>; + #interrupt-cells = <3>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + +[1]. Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt