From patchwork Wed Jun 9 09:16:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 1489761 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=rudOZYqi; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4G0M2W2vvSz9sRN for ; Wed, 9 Jun 2021 19:17:38 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 79E6638618D1 for ; Wed, 9 Jun 2021 09:17:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 79E6638618D1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1623230255; bh=NZgvUqDdCfURtffBUoCh03x8XaM4sSBQCkLwx6IRvkU=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=rudOZYqi6jCdhUTe/WriKsBGWyFMH3Lj1sF+YZwvO5fW5NjKQ8QK3MQAqA7qDdhEt IlVlmNa/+lahhddR9NJEWbpLtZSFoFtvI/7CDOzMZPBztqOzqSdmrMhHB4e+1u+P+m SPsn0V58Ghbg3P0jBjxGF3Ok3rAKrEkgYeU8HoIg= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by sourceware.org (Postfix) with ESMTPS id 06EE8385802D for ; Wed, 9 Jun 2021 09:16:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 06EE8385802D Received: by mail-ej1-x62a.google.com with SMTP id c10so37324194eja.11 for ; Wed, 09 Jun 2021 02:16:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=NZgvUqDdCfURtffBUoCh03x8XaM4sSBQCkLwx6IRvkU=; b=e1fS4vaaf3rF7xA4eV2iWTagxnlqYNdbgg2cSgT/OtUsAPIRtvPqzCYzLB1hzAyTS9 Ct7gv6tTucPKdKvJmXvAy/zK3w2N1LVRY/v4YOAaZhU6jpIUJv/womnJGU/gX630ughB uRBlhhbWeToGWr3XxWeriAb7/+CAtgAPhTWi1y9NZf4Yzud9HLM9Mb32fzygxB5EHd0V zkOGwljifcqq5QOVp3eZd6WdgWy2ZeEjAwIWp2ZjXGXskN6FHZ7DAOzKSoshIA90il4w Nhcp9kRBDPa+TUHuJ/m8+o7U28jz1LfcmL751q94jT+4dE7ry4UfjOTUFpXN8pW7U3q9 /rfw== X-Gm-Message-State: AOAM532jfynevusX3gN2HuJj2Mf0u0z2ch+Cq9Kh2kit3oUztJ4CglWQ mzKd8cPYvxpj9ExRJVireqOIjOyuVChxAg== X-Google-Smtp-Source: ABdhPJwgLs08fYTXA+XoL4DFM9Joq51BmTB11G5U297c59EYHkukcj4miVk51N0RGE1InS4LADnk+g== X-Received: by 2002:a17:907:9813:: with SMTP id ji19mr28148193ejc.318.1623230210624; Wed, 09 Jun 2021 02:16:50 -0700 (PDT) Received: from localhost.localdomain ([79.115.44.61]) by smtp.gmail.com with ESMTPSA id t2sm825371ejx.72.2021.06.09.02.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jun 2021 02:16:50 -0700 (PDT) X-Google-Original-From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Subject: [committed] arc: Update 64bit move split patterns. Date: Wed, 9 Jun 2021 12:16:42 +0300 Message-Id: <20210609091644.476605-1-claziss@synopsys.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Claudiu Zissulescu via Gcc-patches From: Claudiu Zissulescu Reply-To: Claudiu Zissulescu Cc: fbedard@synopsys.com Errors-To: gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org Sender: "Gcc-patches" ARCv2HS can use a limited number of instructions to implement 64bit moves. The VADD2 is used as a 64bit move, the LDD/STD are 64 bit loads and stores. All those instructions are not baseline, hence we need to provide alternatives when they are not available or cannot be generate due to instruction restriction. This patch is cleaning up those move patterns, and updates splits instruction lengths. Backported to gcc11 too. gcc/ 2021-06-09 Claudiu Zissulescu * config/arc/arc-protos.h (arc_split_move_p): New prototype. * config/arc/arc.c (arc_split_move_p): New function. (arc_split_move): Clean up. * config/arc/arc.md (movdi_insn): Clean up, use arc_split_move_p. (movdf_insn): Likewise. * config/arc/simdext.md (mov_insn): Likewise. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc-protos.h | 1 + gcc/config/arc/arc.c | 44 ++++++++++-------- gcc/config/arc/arc.md | 91 ++++++++----------------------------- gcc/config/arc/simdext.md | 38 ++++------------ 4 files changed, 52 insertions(+), 122 deletions(-) diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index 1f56a0d82e4..62d7e45d29d 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -50,6 +50,7 @@ extern void arc_split_ior (rtx *); extern bool arc_check_mov_const (HOST_WIDE_INT ); extern bool arc_split_mov_const (rtx *); extern bool arc_can_use_return_insn (void); +extern bool arc_split_move_p (rtx *); #endif /* RTX_CODE */ extern bool arc_ccfsm_branch_deleted_p (void); diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 0d34c964963..69f6ae464e1 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -10108,6 +10108,31 @@ arc_process_double_reg_moves (rtx *operands) return true; } + +/* Check if we need to split a 64bit move. We do not need to split it if we can + use vadd2 or ldd/std instructions. */ + +bool +arc_split_move_p (rtx *operands) +{ + machine_mode mode = GET_MODE (operands[0]); + + if (TARGET_LL64 + && ((memory_operand (operands[0], mode) + && (even_register_operand (operands[1], mode) + || satisfies_constraint_Cm3 (operands[1]))) + || (memory_operand (operands[1], mode) + && even_register_operand (operands[0], mode)))) + return false; + + if (TARGET_PLUS_QMACW + && even_register_operand (operands[0], mode) + && even_register_operand (operands[1], mode)) + return false; + + return true; +} + /* operands 0..1 are the operands of a 64 bit move instruction. split it into two moves with operands 2/3 and 4/5. */ @@ -10125,25 +10150,6 @@ arc_split_move (rtx *operands) return; } - if (TARGET_LL64 - && ((memory_operand (operands[0], mode) - && (even_register_operand (operands[1], mode) - || satisfies_constraint_Cm3 (operands[1]))) - || (memory_operand (operands[1], mode) - && even_register_operand (operands[0], mode)))) - { - emit_move_insn (operands[0], operands[1]); - return; - } - - if (TARGET_PLUS_QMACW - && even_register_operand (operands[0], mode) - && even_register_operand (operands[1], mode)) - { - emit_move_insn (operands[0], operands[1]); - return; - } - if (TARGET_PLUS_QMACW && GET_CODE (operands[1]) == CONST_VECTOR) { diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index de61b2b790f..6f13b3a01d8 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1330,47 +1330,20 @@ (define_insn_and_split "*movdi_insn" "register_operand (operands[0], DImode) || register_operand (operands[1], DImode) || (satisfies_constraint_Cm3 (operands[1]) - && memory_operand (operands[0], DImode))" - "* -{ - switch (which_alternative) - { - default: - return \"#\"; - - case 0: - if (TARGET_PLUS_QMACW - && even_register_operand (operands[0], DImode) - && even_register_operand (operands[1], DImode)) - return \"vadd2%?\\t%0,%1,0\"; - return \"#\"; - - case 2: - if (TARGET_LL64 - && memory_operand (operands[1], DImode) - && even_register_operand (operands[0], DImode)) - return \"ldd%U1%V1 %0,%1%&\"; - return \"#\"; - - case 3: - if (TARGET_LL64 - && memory_operand (operands[0], DImode) - && (even_register_operand (operands[1], DImode) - || satisfies_constraint_Cm3 (operands[1]))) - return \"std%U0%V0 %1,%0\"; - return \"#\"; - } -}" - "&& reload_completed" + && memory_operand (operands[0], DImode))" + "@ + vadd2\\t%0,%1,0 + # + ldd%U1%V1\\t%0,%1 + std%U0%V0\\t%1,%0" + "&& reload_completed && arc_split_move_p (operands)" [(const_int 0)] { arc_split_move (operands); DONE; } [(set_attr "type" "move,move,load,store") - ;; ??? The ld/st values could be 4 if it's [reg,bignum]. - (set_attr "length" "8,16,*,*")]) - + (set_attr "length" "8,16,16,16")]) ;; Floating point move insns. @@ -1409,50 +1382,22 @@ (define_expand "movdf" (define_insn_and_split "*movdf_insn" [(set (match_operand:DF 0 "move_dest_operand" "=D,r,r,r,r,m") (match_operand:DF 1 "move_double_src_operand" "r,D,r,E,m,r"))] - "register_operand (operands[0], DFmode) - || register_operand (operands[1], DFmode)" - "* -{ - switch (which_alternative) - { - default: - return \"#\"; - - case 2: - if (TARGET_PLUS_QMACW - && even_register_operand (operands[0], DFmode) - && even_register_operand (operands[1], DFmode)) - return \"vadd2%?\\t%0,%1,0\"; - return \"#\"; - - case 4: - if (TARGET_LL64 - && ((even_register_operand (operands[0], DFmode) - && memory_operand (operands[1], DFmode)) - || (memory_operand (operands[0], DFmode) - && even_register_operand (operands[1], DFmode)))) - return \"ldd%U1%V1 %0,%1%&\"; - return \"#\"; - - case 5: - if (TARGET_LL64 - && ((even_register_operand (operands[0], DFmode) - && memory_operand (operands[1], DFmode)) - || (memory_operand (operands[0], DFmode) - && even_register_operand (operands[1], DFmode)))) - return \"std%U0%V0 %1,%0\"; - return \"#\"; - } -}" - "reload_completed" + "(register_operand (operands[0], DFmode) + || register_operand (operands[1], DFmode))" + "@ + # + # + vadd2\\t%0,%1,0 + # + ldd%U1%V1\\t%0,%1 + std%U0%V0\\t%1,%0" + "&& reload_completed && arc_split_move_p (operands)" [(const_int 0)] { arc_split_move (operands); DONE; } [(set_attr "type" "move,move,move,move,load,store") - (set_attr "predicable" "no,no,no,yes,no,no") - ;; ??? The ld/st values could be 16 if it's [reg,bignum]. (set_attr "length" "4,16,8,16,16,16")]) (define_insn_and_split "*movdf_insn_nolrsr" diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index dd63f93b3fd..303f52cf260 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -1472,41 +1472,19 @@ (define_insn_and_split "*mov_insn" (match_operand:VWH 1 "general_operand" "i,r,m,r"))] "(register_operand (operands[0], mode) || register_operand (operands[1], mode))" - "* -{ - switch (which_alternative) - { - default: - return \"#\"; - - case 1: - if (TARGET_PLUS_QMACW - && even_register_operand (operands[0], mode) - && even_register_operand (operands[1], mode)) - return \"vadd2%?\\t%0,%1,0\"; - return \"#\"; - - case 2: - if (TARGET_LL64) - return \"ldd%U1%V1\\t%0,%1\"; - return \"#\"; - - case 3: - if (TARGET_LL64) - return \"std%U0%V0\\t%1,%0\"; - return \"#\"; - } -}" - "reload_completed" + "@ + # + vadd2\\t%0,%1,0 + ldd%U1%V1\\t%0,%1 + std%U0%V0\\t%1,%0" + "&& reload_completed && arc_split_move_p (operands)" [(const_int 0)] { arc_split_move (operands); DONE; } - [(set_attr "type" "move,multi,load,store") - (set_attr "predicable" "no,no,no,no") - (set_attr "iscompact" "false,false,false,false") - ]) + [(set_attr "type" "move,move,load,store") + (set_attr "length" "16,8,16,16")]) (define_expand "movmisalign" [(set (match_operand:VWH 0 "general_operand" "")