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From: Pratyush Yadav
To: Maxime Ripard ,
Mauro Carvalho Chehab ,
Rob Herring ,
Pratyush Yadav ,
Kishon Vijay Abraham I ,
Vinod Koul ,
Peter Ujfalusi ,
Steve Longerbeam ,
Benoit Parrot , ,
, ,
,
CC: Vignesh Raghavendra ,
Tomi Valkeinen ,
Chunfeng Yun ,
Laurent Pinchart
Subject: [PATCH v2 14/18] media: dt-bindings: Add DT bindings for TI J721E
CSI2RX driver
Date: Wed, 26 May 2021 20:53:04 +0530
Message-ID: <20210526152308.16525-15-p.yadav@ti.com>
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TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate
capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the
parts together.
Signed-off-by: Pratyush Yadav
---
Changes in v2:
- Rename to ti,j721e-csi2rx.yaml
- Add an entry in MAINTAINERS.
- Add a description for the binding.
- Change compatible to ti,j721e-csi2rx to make it SoC specific.
- Remove description from dmas, reg, power-domains.
- Remove a limit of 2 from #address-cells and #size-cells.
- Fix add ^ to csi-bridge subnode regex.
- Make ranges mandatory.
- Add unit address in example.
- Add a reference to cdns,csi2rx in csi-bridge subnode.
- Expand the example to include the csi-bridge subnode as well.
- Re-order subject prefixes.
.../bindings/media/ti,j721e-csi2rx.yaml | 101 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 102 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml
diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml
new file mode 100644
index 000000000000..db87cfd65bed
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI J721E CSI2RX Wrapper Device Tree Bindings
+
+description: |
+ The TI J721E CSI2RX Wrapper is a wrapper around Cadence CSI2RX bridge that
+ enables sending captured frames to memory over PSI-L DMA. In the J721E
+ Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the
+ CSI_RX_IF section.
+
+maintainers:
+ - Pratyush Yadav
+
+properties:
+ compatible:
+ items:
+ - const: ti,j721e-csi2rx
+
+ dmas:
+ maxItems: 1
+
+ dma-names:
+ items:
+ - const: rx0
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+patternProperties:
+ "^csi-bridge@":
+ type: object
+ description: CSI2 bridge node.
+ $ref: cdns,csi2rx.yaml#
+
+required:
+ - compatible
+ - reg
+ - dmas
+ - dma-names
+ - power-domains
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include
+
+ ti_csi2rx0: ticsi2rx@4500000 {
+ compatible = "ti,j721e-csi2rx";
+ dmas = <&main_udmap 0x4940>;
+ dma-names = "rx0";
+ reg = <0x4500000 0x1000>;
+ power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ cdns_csi2rx: csi-bridge@4504000 {
+ compatible = "cdns,csi2rx";
+ reg = <0x4504000 0x1000>;
+ clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
+ <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
+ clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
+ "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi2_0: port@0 {
+
+ reg = <0>;
+
+ csi2rx0_in_sensor: endpoint {
+ remote-endpoint = <&csi2_cam0>;
+ bus-type = <4>; /* CSI2 DPHY. */
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2cf140a02063..1f9de488564d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -18336,6 +18336,7 @@ TI J721E CSI2RX DRIVER
M: Pratyush Yadav
L: linux-media@vger.kernel.org
S: Supported
+F: Documentation/devicetree/bindings/media/ti,j721e-csi2rx.yaml
F: drivers/media/platform/ti/j721e-csi2rx/
TI DAVINCI MACHINE SUPPORT
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From: Pratyush Yadav
To: Maxime Ripard ,
Mauro Carvalho Chehab ,
Rob Herring ,
Pratyush Yadav ,
Kishon Vijay Abraham I ,
Vinod Koul ,
Peter Ujfalusi ,
Steve Longerbeam ,
Benoit Parrot , ,
, ,
,
CC: Vignesh Raghavendra ,
Tomi Valkeinen ,
Chunfeng Yun ,
Laurent Pinchart
Subject: [PATCH v2 15/18] media: dt-bindings: Convert Cadence CSI2RX binding
to YAML
Date: Wed, 26 May 2021 20:53:05 +0530
Message-ID: <20210526152308.16525-16-p.yadav@ti.com>
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Convert the Cadence CSI2RX binding to use YAML schema.
Signed-off-by: Pratyush Yadav
---
Changes in v2:
- New in v2.
.../devicetree/bindings/media/cdns,csi2rx.txt | 100 -----------
.../bindings/media/cdns,csi2rx.yaml | 164 ++++++++++++++++++
2 files changed, 164 insertions(+), 100 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt
create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt
deleted file mode 100644
index 6b02a0657ad9..000000000000
--- a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt
+++ /dev/null
@@ -1,100 +0,0 @@
-Cadence MIPI-CSI2 RX controller
-===============================
-
-The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
-lanes in input, and 4 different pixel streams in output.
-
-Required properties:
- - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
- - reg: base address and size of the memory mapped region
- - clocks: phandles to the clocks driving the controller
- - clock-names: must contain:
- * sys_clk: main clock
- * p_clk: register bank clock
- * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
- implemented in hardware, between 0 and 3
-
-Optional properties:
- - phys: phandle to the external D-PHY, phy-names must be provided
- - phy-names: must contain "dphy", if the implementation uses an
- external D-PHY
-
-Required subnodes:
- - ports: A ports node with one port child node per device input and output
- port, in accordance with the video interface bindings defined in
- Documentation/devicetree/bindings/media/video-interfaces.txt. The
- port nodes are numbered as follows:
-
- Port Description
- -----------------------------
- 0 CSI-2 input
- 1 Stream 0 output
- 2 Stream 1 output
- 3 Stream 2 output
- 4 Stream 3 output
-
- The stream output port nodes are optional if they are not
- connected to anything at the hardware level or implemented
- in the design.Since there is only one endpoint per port,
- the endpoints are not numbered.
-
-
-Example:
-
-csi2rx: csi-bridge@0d060000 {
- compatible = "cdns,csi2rx";
- reg = <0x0d060000 0x1000>;
- clocks = <&byteclock>, <&byteclock>
- <&coreclock>, <&coreclock>,
- <&coreclock>, <&coreclock>;
- clock-names = "sys_clk", "p_clk",
- "pixel_if0_clk", "pixel_if1_clk",
- "pixel_if2_clk", "pixel_if3_clk";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- csi2rx_in_sensor: endpoint {
- remote-endpoint = <&sensor_out_csi2rx>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- csi2rx_out_grabber0: endpoint {
- remote-endpoint = <&grabber0_in_csi2rx>;
- };
- };
-
- port@2 {
- reg = <2>;
-
- csi2rx_out_grabber1: endpoint {
- remote-endpoint = <&grabber1_in_csi2rx>;
- };
- };
-
- port@3 {
- reg = <3>;
-
- csi2rx_out_grabber2: endpoint {
- remote-endpoint = <&grabber2_in_csi2rx>;
- };
- };
-
- port@4 {
- reg = <4>;
-
- csi2rx_out_grabber3: endpoint {
- remote-endpoint = <&grabber3_in_csi2rx>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
new file mode 100644
index 000000000000..ff5dd4211ac9
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/cdns,csi2rx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MIPI-CSI2 RX controller
+
+description: |
+ The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
+ lanes in input, and 4 different pixel streams in output.
+
+maintainers:
+ - Pratyush Yadav
+
+properties:
+ compatible:
+ items:
+ - const: cdns,csi2rx
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+ maxItems: 6
+
+ clock-names:
+ minItems: 3
+ maxItems: 6
+ items:
+ - const: sys_clk # main clock
+ - const: p_clk # register bank clock
+ - const: pixel_if0_clk # pixel stream 0 output clock
+ - const: pixel_if1_clk # pixel stream 1 output clock
+ - const: pixel_if2_clk # pixel stream 2 output clock
+ - const: pixel_if3_clk # pixel stream 3 output clock
+
+ phys:
+ maxItems: 1
+ description: phandle to the external D-PHY
+
+ phy-names:
+ items:
+ - const: dphy
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: CSI-2 input
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ maxItems: 1
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Stream 0 output
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Stream 1 output
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Stream 2 output
+
+ port@4:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Stream 3 output
+
+ required:
+ - port@0
+
+
+dependencies:
+ phys: [ 'phy-names' ]
+ phy-names: [ 'phys' ]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ csi2rx: csi-bridge@d060000 {
+ compatible = "cdns,csi2rx";
+ reg = <0x0d060000 0x1000>;
+ clocks = <&byteclock>, <&byteclock>,
+ <&coreclock>, <&coreclock>,
+ <&coreclock>, <&coreclock>;
+ clock-names = "sys_clk", "p_clk",
+ "pixel_if0_clk", "pixel_if1_clk",
+ "pixel_if2_clk", "pixel_if3_clk";
+ phys = <&dphy0>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi2rx_in_sensor: endpoint {
+ remote-endpoint = <&sensor_out_csi2rx>;
+ clock-lanes = <0>;
+ data-lanes = <1 2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csi2rx_out_grabber0: endpoint {
+ remote-endpoint = <&grabber0_in_csi2rx>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ csi2rx_out_grabber1: endpoint {
+ remote-endpoint = <&grabber1_in_csi2rx>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ csi2rx_out_grabber2: endpoint {
+ remote-endpoint = <&grabber2_in_csi2rx>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ csi2rx_out_grabber3: endpoint {
+ remote-endpoint = <&grabber3_in_csi2rx>;
+ };
+ };
+ };
+ };
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From: Pratyush Yadav
To: Maxime Ripard ,
Mauro Carvalho Chehab ,
Rob Herring ,
Pratyush Yadav ,
Kishon Vijay Abraham I ,
Vinod Koul ,
Peter Ujfalusi ,
Steve Longerbeam ,
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, ,
,
CC: Vignesh Raghavendra ,
Tomi Valkeinen ,
Chunfeng Yun ,
Laurent Pinchart
Subject: [PATCH v2 16/18] phy: dt-bindings: Convert Cadence DPHY binding to
YAML
Date: Wed, 26 May 2021 20:53:06 +0530
Message-ID: <20210526152308.16525-17-p.yadav@ti.com>
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Convert Cadence DPHY binding to YAML.
Signed-off-by: Pratyush Yadav
Reviewed-by: Laurent Pinchart
Reviewed-by: Rob Herring
---
Changes in v2:
- Drop reg description.
- Add a description for each DPHY clock.
- Rename dphy@... to phy@... in example.
- Add Laurent's R-by.
- Re-order subject prefixes.
.../devicetree/bindings/phy/cdns,dphy.txt | 20 --------
.../devicetree/bindings/phy/cdns,dphy.yaml | 51 +++++++++++++++++++
2 files changed, 51 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.txt
create mode 100644 Documentation/devicetree/bindings/phy/cdns,dphy.yaml
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.txt b/Documentation/devicetree/bindings/phy/cdns,dphy.txt
deleted file mode 100644
index 1095bc4e72d9..000000000000
--- a/Documentation/devicetree/bindings/phy/cdns,dphy.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Cadence DPHY
-============
-
-Cadence DPHY block.
-
-Required properties:
-- compatible: should be set to "cdns,dphy".
-- reg: physical base address and length of the DPHY registers.
-- clocks: DPHY reference clocks.
-- clock-names: must contain "psm" and "pll_ref".
-- #phy-cells: must be set to 0.
-
-Example:
- dphy0: dphy@fd0e0000{
- compatible = "cdns,dphy";
- reg = <0x0 0xfd0e0000 0x0 0x1000>;
- clocks = <&psm_clk>, <&pll_ref_clk>;
- clock-names = "psm", "pll_ref";
- #phy-cells = <0>;
- };
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
new file mode 100644
index 000000000000..b90a58773bf2
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/cdns,dphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence DPHY Device Tree Bindings
+
+maintainers:
+ - Pratyush Yadav
+
+properties:
+ compatible:
+ items:
+ - const: cdns,dphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PMA state machine clock
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: psm
+ - const: pll_ref
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+
+ dphy0: phy@fd0e0000{
+ compatible = "cdns,dphy";
+ reg = <0xfd0e0000 0x1000>;
+ clocks = <&psm_clk>, <&pll_ref_clk>;
+ clock-names = "psm", "pll_ref";
+ #phy-cells = <0>;
+ };
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From: Pratyush Yadav
To: Maxime Ripard ,
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Rob Herring ,
Pratyush Yadav ,
Kishon Vijay Abraham I ,
Vinod Koul ,
Peter Ujfalusi ,
Steve Longerbeam ,
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, ,
,
CC: Vignesh Raghavendra ,
Tomi Valkeinen ,
Chunfeng Yun ,
Laurent Pinchart
Subject: [PATCH v2 17/18] phy: dt-bindings: cdns,dphy: make clocks optional
Date: Wed, 26 May 2021 20:53:07 +0530
Message-ID: <20210526152308.16525-18-p.yadav@ti.com>
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The clocks are not used by the DPHY when used in Rx mode so make them
optional.
Signed-off-by: Pratyush Yadav
Acked-by: Rob Herring
---
Changes in v2:
- Re-order subject prefixes.
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
index b90a58773bf2..3bb5be05e825 100644
--- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
@@ -33,8 +33,6 @@ properties:
required:
- compatible
- reg
- - clocks
- - clock-names
- "#phy-cells"
additionalProperties: false
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From: Pratyush Yadav
To: Maxime Ripard ,
Mauro Carvalho Chehab ,
Rob Herring ,
Pratyush Yadav ,
Kishon Vijay Abraham I ,
Vinod Koul ,
Peter Ujfalusi ,
Steve Longerbeam ,
Benoit Parrot , ,
, ,
,
CC: Vignesh Raghavendra ,
Tomi Valkeinen ,
Chunfeng Yun ,
Laurent Pinchart
Subject: [PATCH v2 18/18] phy: dt-bindings: cdns,dphy: add power-domains
property
Date: Wed, 26 May 2021 20:53:08 +0530
Message-ID: <20210526152308.16525-19-p.yadav@ti.com>
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This property is needed on TI platforms to enable the PD of the DPHY
before it can be used.
Signed-off-by: Pratyush Yadav
Reviewed-by: Laurent Pinchart
Acked-by: Rob Herring
---
Changes in v2:
- Add power-domain to the example.
- Add Laurent's R-by.
- Re-order subject prefixes.
Documentation/devicetree/bindings/phy/cdns,dphy.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
index 3bb5be05e825..d5a5e1f0b671 100644
--- a/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/cdns,dphy.yaml
@@ -30,6 +30,9 @@ properties:
"#phy-cells":
const: 0
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -39,11 +42,13 @@ additionalProperties: false
examples:
- |
+ #include
dphy0: phy@fd0e0000{
compatible = "cdns,dphy";
reg = <0xfd0e0000 0x1000>;
clocks = <&psm_clk>, <&pll_ref_clk>;
clock-names = "psm", "pll_ref";
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
#phy-cells = <0>;
};