From patchwork Wed May 19 11:16:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Green Wan X-Patchwork-Id: 1480847 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FlVhP0wtzz9sW1 for ; Wed, 19 May 2021 21:17:24 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 78DA282E3A; Wed, 19 May 2021 13:17:19 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 58E3682E3F; Wed, 19 May 2021 13:17:17 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from transporter.internal.sifive.com (unknown [64.62.193.209]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3633D82E1E for ; Wed, 19 May 2021 13:17:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=green.wan@sifive.com Received: from gamma15.internal.sifive.com (gamma15.internal.sifive.com [10.14.21.64]) by transporter.internal.sifive.com (Postfix) with ESMTPS id 1550C20429; Wed, 19 May 2021 04:17:12 -0700 (PDT) Received: from localhost (gamma15.internal.sifive.com [local]) by gamma15.internal.sifive.com (OpenSMTPD) with ESMTPA id 691b3d15; Wed, 19 May 2021 11:17:12 +0000 (UTC) From: Green Wan To: Cc: bmeng.cn@gmail.com, ycliang@andestech.com, Green Wan , Neil Armstrong , u-boot@lists.denx.de (open list) Subject: [PATCH v2] drivers: pci: pcie_dw_common: fix Werror compilation error Date: Wed, 19 May 2021 04:16:15 -0700 Message-Id: <20210519111616.306316-1-green.wan@sifive.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Fix compilation error when Werror is turned on. The warning could possible break some CI builds. Signed-off-by: Green Wan Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Neil Armstrong --- drivers/pci/pcie_dw_common.c | 54 +++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 25 deletions(-) diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 785fd3aad0..e66fb1490a 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -213,7 +213,7 @@ int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, va_address = set_cfg_address(pcie, bdf, offset); - value = readl(va_address); + value = readl((void __iomem *)va_address); debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); *valuep = pci_conv_32_to_size(value, offset, size); @@ -257,9 +257,9 @@ int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, va_address = set_cfg_address(pcie, bdf, offset); - old = readl(va_address); + old = readl((void __iomem *)va_address); value = pci_conv_size_to_32(old, value, offset, size); - writel(value, va_address); + writel(value, (void __iomem *)va_address); return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1, PCIE_ATU_TYPE_IO, pcie->io.phys_start, @@ -333,33 +333,37 @@ void pcie_dw_setup_host(struct pcie_dw *pci) } } - dev_dbg(pci->dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n", - pci->cfg_base, pci->cfg_base + pci->cfg_size, - pci->cfg_size); + dev_dbg(pci->dev, "Config space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->cfg_base, (u64)pci->cfg_base + pci->cfg_size, + (u64)pci->cfg_size); - dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%lx]\n", - pci->io.phys_start, pci->io.phys_start + pci->io.size, - pci->io.size); + dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->io.phys_start, (u64)pci->io.phys_start + pci->io.size, + (u64)pci->io.size); - dev_dbg(pci->dev, "IO bus: [0x%lx - 0x%lx, size 0x%lx]\n", - pci->io.bus_start, pci->io.bus_start + pci->io.size, - pci->io.size); + dev_dbg(pci->dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->io.bus_start, (u64)pci->io.bus_start + pci->io.size, + (u64)pci->io.size); - dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%lx]\n", - pci->mem.phys_start, pci->mem.phys_start + pci->mem.size, - pci->mem.size); + dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->mem.phys_start, + (u64)pci->mem.phys_start + pci->mem.size, + (u64)pci->mem.size); - dev_dbg(pci->dev, "MEM bus: [0x%lx - 0x%lx, size 0x%lx]\n", - pci->mem.bus_start, pci->mem.bus_start + pci->mem.size, - pci->mem.size); + dev_dbg(pci->dev, "MEM bus: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->mem.bus_start, + (u64)pci->mem.bus_start + pci->mem.size, + (u64)pci->mem.size); if (pci->prefetch.size) { - dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%lx]\n", - pci->prefetch.phys_start, pci->prefetch.phys_start + pci->prefetch.size, - pci->prefetch.size); - - dev_dbg(pci->dev, "PREFETCH bus: [0x%lx - 0x%lx, size 0x%lx]\n", - pci->prefetch.bus_start, pci->prefetch.bus_start + pci->prefetch.size, - pci->prefetch.size); + dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->prefetch.phys_start, + (u64)pci->prefetch.phys_start + pci->prefetch.size, + (u64)pci->prefetch.size); + + dev_dbg(pci->dev, "PREFETCH bus: [0x%llx - 0x%llx, size 0x%llx]\n", + (u64)pci->prefetch.bus_start, + (u64)pci->prefetch.bus_start + pci->prefetch.size, + (u64)pci->prefetch.size); } }