From patchwork Mon May 10 17:24:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1476598 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=G7lCjgyF; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ff7HK67xyz9sWD for ; Tue, 11 May 2021 03:25:33 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3025282EF5; Mon, 10 May 2021 19:25:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="G7lCjgyF"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 804F082ED6; Mon, 10 May 2021 19:25:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 3758182EDD for ; Mon, 10 May 2021 19:25:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP7R7120165; Mon, 10 May 2021 12:25:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1620667507; bh=YtKai2WK0su9wACicm6/UW8eJtQE36Wc8ZQWnms/6Nc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G7lCjgyFPpd9SvSkzIbk/lHoR67hCd48C9aUU8qfAyWc4V+DhXi5msX0hVUnWTcxx jsSbIzCPbWRVUpcpBFX4KWudym4fBV18CzUtZMdMqu0roQBz5l9h+b7UkTzJKZtDDF Vf9xn+A9WlS32wlj8Q/eqCsjk0M8xGlXlByQprTc= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 14AHP6ua013380 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 May 2021 12:25:07 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Mon, 10 May 2021 12:25:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 10 May 2021 12:25:06 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP1na023176; Mon, 10 May 2021 12:25:04 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: , Nishanth Menon , Dave Gerlach , Tero Kristo , Tom Rini Subject: [PATCH 1/7] mailbox: k3-sec-proxy: Add DM to DMSC communication thread Date: Mon, 10 May 2021 22:54:36 +0530 Message-ID: <20210510172442.11146-2-vigneshr@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510172442.11146-1-vigneshr@ti.com> References: <20210510172442.11146-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean R5 SPL would need to talk to DMSC using DM to DMSC sec-proxy threads. Mark these as valid threads in the driver. Signed-off-by: Vignesh Raghavendra --- drivers/mailbox/k3-sec-proxy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c index 88f320515a..20fdb09f31 100644 --- a/drivers/mailbox/k3-sec-proxy.c +++ b/drivers/mailbox/k3-sec-proxy.c @@ -409,7 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev) return 0; } -static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 }; +static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23 }; static const struct k3_sec_proxy_desc am654_desc = { .thread_count = 90, From patchwork Mon May 10 17:24:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1476599 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 10 May 2021 12:25:09 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP1nb023176; Mon, 10 May 2021 12:25:07 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: , Nishanth Menon , Dave Gerlach , Tero Kristo , Tom Rini Subject: [PATCH 2/7] firmware: ti_sci: Implement GET_RANGE with static data Date: Mon, 10 May 2021 22:54:37 +0530 Message-ID: <20210510172442.11146-3-vigneshr@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510172442.11146-1-vigneshr@ti.com> References: <20210510172442.11146-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean In case of R5 SPL, GET_RANGE API service is not available (as DM services are not yet up), therefore service such calls locally using per SoC static data. Signed-off-by: Vignesh Raghavendra --- drivers/firmware/ti_sci.c | 36 +++++++++++ drivers/firmware/ti_sci_static_data.h | 92 +++++++++++++++++++++++++++ 2 files changed, 128 insertions(+) create mode 100644 drivers/firmware/ti_sci_static_data.h diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 2aec2e34d3..c27fbc682a 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -23,6 +23,7 @@ #include #include "ti_sci.h" +#include "ti_sci_static_data.h" /* List of all TI SCI devices active in system */ static LIST_HEAD(ti_sci_list); @@ -1667,6 +1668,33 @@ fail: return ret; } +static int __maybe_unused +ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start, + u16 *range_num) +{ + struct ti_sci_resource_static_data *data; + int i = 0; + + while (1) { + data = &rm_static_data[i]; + + if (!data->dev_id) + return -EINVAL; + + if (data->dev_id != dev_id || data->subtype != subtype) { + i++; + continue; + } + + *range_start = data->range_start; + *range_num = data->range_num; + + return 0; + } + + return -EINVAL; +} + /** * ti_sci_cmd_get_resource_range - Get a range of resources assigned to host * that is same as ti sci interface host. @@ -1683,6 +1711,11 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u16 *range_start, u16 *range_num) { + if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) + return ti_sci_get_resource_range_static(dev_id, subtype, + range_start, + range_num); + return ti_sci_get_resource_range(handle, dev_id, subtype, TI_SCI_IRQ_SECONDARY_HOST_INVALID, range_start, range_num); @@ -1706,6 +1739,9 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, u16 *range_start, u16 *range_num) { + if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) + return -EINVAL; + return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, range_start, range_num); } diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h new file mode 100644 index 0000000000..2816cb2827 --- /dev/null +++ b/drivers/firmware/ti_sci_static_data.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * + */ + +#ifndef __TI_SCI_STATIC_DATA_H +#define __TI_SCI_STATIC_DATA_H + +struct ti_sci_resource_static_data { + u32 dev_id; + u16 range_start; + u16 range_num; + u8 subtype; +}; + +#if IS_ENABLED(CONFIG_K3_DM_FW) + +#ifdef CONFIG_TARGET_J721E_R5_EVM +static struct ti_sci_resource_static_data rm_static_data[] = { + /* Free rings */ + { + .dev_id = 235, + .subtype = 1, + .range_start = 124, + .range_num = 32, + }, + /* TX channels */ + { + .dev_id = 236, + .subtype = 13, + .range_start = 6, + .range_num = 2, + }, + /* RX channels */ + { + .dev_id = 236, + .subtype = 10, + .range_start = 6, + .range_num = 2, + }, + /* RX Free flows */ + { + .dev_id = 236, + .subtype = 0, + .range_start = 60, + .range_num = 8, + }, + { }, +}; +#endif /* CONFIG_TARGET_J721E_R5_EVM */ + +#ifdef CONFIG_TARGET_J7200_R5_EVM +static struct ti_sci_resource_static_data rm_static_data[] = { + /* Free rings */ + { + .dev_id = 235, + .subtype = 1, + .range_start = 144, + .range_num = 32, + }, + /* TX channels */ + { + .dev_id = 236, + .subtype = 13, + .range_start = 7, + .range_num = 2, + }, + /* RX channels */ + { + .dev_id = 236, + .subtype = 10, + .range_start = 7, + .range_num = 2, + }, + /* RX Free flows */ + { + .dev_id = 236, + .subtype = 0, + .range_start = 60, + .range_num = 8, + }, + { }, +}; +#endif /* CONFIG_TARGET_J7200_R5_EVM */ + +#else +static struct ti_sci_resource_static_data rm_static_data[] = { + { }, +}; +#endif /* CONFIG_K3_DM_FW */ +#endif /* __TI_SCI_STATIC_DATA_H */ From patchwork Mon May 10 17:24:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1476600 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=zT8rx2w9; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ff7Hl4X9sz9sWD for ; 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Mon, 10 May 2021 12:25:11 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 10 May 2021 12:25:11 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP1nc023176; Mon, 10 May 2021 12:25:09 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: , Nishanth Menon , Dave Gerlach , Tero Kristo , Tom Rini Subject: [PATCH 3/7] firmware: ti_sci: Add support for Resoure Management at R5 SPL stage. Date: Mon, 10 May 2021 22:54:38 +0530 Message-ID: <20210510172442.11146-4-vigneshr@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510172442.11146-1-vigneshr@ti.com> References: <20210510172442.11146-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean On J721e and J7200, MCU R5 core (boot master) itself would run Device Manager (DM) Firmware and interact with TI Foundational Security (TIFS) firmware to enable DMA and such other Resource Management (RM) services. So, during R5 SPL stage there is no such RM service available and ti_sci driver will have to directly interact with TIFS using DM to DMSC channels to request RM resources. Therefore add DT binding and driver for the same. This driver will handle Resource Management services at R5 SPL stage. Signed-off-by: Vignesh Raghavendra --- .../firmware/ti,j721e-dm-sci.txt | 32 +++++++ drivers/firmware/ti_sci.c | 91 +++++++++++++++++-- 2 files changed, 113 insertions(+), 10 deletions(-) create mode 100644 doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt diff --git a/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt new file mode 100644 index 0000000000..0217341f0c --- /dev/null +++ b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt @@ -0,0 +1,32 @@ +Bindings for Texas Instruments System Control Interface (TI-SCI) Message +Protocol for Device Manager(DM) to TI Foundational Security(TIFS) +Firmware communication + +Required properties: +-------------------- +- compatible: should be "ti,j721e-dm-sci" +- mbox-names: + "rx" - Mailbox corresponding to receive path + "tx" - Mailbox corresponding to transmit path + +- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes + property should contain a phandle to the mailbox controller device + node and an args specifier that will be the phandle to the intended + sub-mailbox child node to be used for communication. + +- ti,host-id: Host ID to use for communication. + +Optional Properties: +-------------------- +- ti,secure-host: If the host is defined as secure. + +Example: +-------- + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + }; diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index c27fbc682a..f75ad5db67 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -1669,8 +1669,9 @@ fail: } static int __maybe_unused -ti_sci_get_resource_range_static(u32 dev_id, u8 subtype, u16 *range_start, - u16 *range_num) +ti_sci_cmd_get_resource_range_static(const struct ti_sci_handle *handle, + u32 dev_id, u8 subtype, + u16 *range_start, u16 *range_num) { struct ti_sci_resource_static_data *data; int i = 0; @@ -1711,11 +1712,6 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u16 *range_start, u16 *range_num) { - if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) - return ti_sci_get_resource_range_static(dev_id, subtype, - range_start, - range_num); - return ti_sci_get_resource_range(handle, dev_id, subtype, TI_SCI_IRQ_SECONDARY_HOST_INVALID, range_start, range_num); @@ -1739,9 +1735,6 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, u16 *range_start, u16 *range_num) { - if (CONFIG_IS_ENABLED(TI_K3_RAW_RM)) - return -EINVAL; - return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, range_start, range_num); } @@ -3051,6 +3044,58 @@ static int ti_sci_probe(struct udevice *dev) return ret; } +/** + * ti_sci_dm_probe() - Basic probe for DM to TIFS SCI + * @dev: corresponding system controller interface device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static __maybe_unused int ti_sci_dm_probe(struct udevice *dev) +{ + struct ti_sci_rm_core_ops *rm_core_ops; + struct ti_sci_rm_udmap_ops *udmap_ops; + struct ti_sci_rm_ringacc_ops *rops; + struct ti_sci_rm_psil_ops *psilops; + struct ti_sci_ops *ops; + struct ti_sci_info *info; + int ret; + + debug("%s(dev=%p)\n", __func__, dev); + + info = dev_get_priv(dev); + info->desc = (void *)dev_get_driver_data(dev); + + ret = ti_sci_of_to_info(dev, info); + if (ret) { + dev_err(dev, "%s: Probe failed with error %d\n", __func__, ret); + return ret; + } + + info->dev = dev; + info->seq = 0xA; + + list_add_tail(&info->list, &ti_sci_list); + + ops = &info->handle.ops; + + rm_core_ops = &ops->rm_core_ops; + rm_core_ops->get_range = ti_sci_cmd_get_resource_range_static; + + rops = &ops->rm_ring_ops; + rops->config = ti_sci_cmd_ring_config; + + psilops = &ops->rm_psil_ops; + psilops->pair = ti_sci_cmd_rm_psil_pair; + psilops->unpair = ti_sci_cmd_rm_psil_unpair; + + udmap_ops = &ops->rm_udmap_ops; + udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg; + udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg; + udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg; + + return ret; +} + /* * ti_sci_get_free_resource() - Get a free resource from TISCI resource. * @res: Pointer to the TISCI resource @@ -3188,6 +3233,14 @@ static const struct ti_sci_desc ti_sci_pmmc_am654_desc = { .max_msg_size = 60, }; +/* Description for J721e DM to DMSC communication */ +static const struct ti_sci_desc ti_sci_dm_j721e_desc = { + .default_host_id = 3, + .max_rx_timeout_ms = 10000, + .max_msgs = 20, + .max_msg_size = 60, +}; + static const struct udevice_id ti_sci_ids[] = { { .compatible = "ti,k2g-sci", @@ -3200,6 +3253,14 @@ static const struct udevice_id ti_sci_ids[] = { { /* Sentinel */ }, }; +static __maybe_unused const struct udevice_id ti_sci_dm_ids[] = { + { + .compatible = "ti,j721e-dm-sci", + .data = (ulong)&ti_sci_dm_j721e_desc + }, + { /* Sentinel */ }, +}; + U_BOOT_DRIVER(ti_sci) = { .name = "ti_sci", .id = UCLASS_FIRMWARE, @@ -3207,3 +3268,13 @@ U_BOOT_DRIVER(ti_sci) = { .probe = ti_sci_probe, .priv_auto = sizeof(struct ti_sci_info), }; + +#if IS_ENABLED(CONFIG_K3_DM_FW) +U_BOOT_DRIVER(ti_sci_dm) = { + .name = "ti_sci_dm", + .id = UCLASS_FIRMWARE, + .of_match = ti_sci_dm_ids, + .probe = ti_sci_dm_probe, + .priv_auto = sizeof(struct ti_sci_info), +}; +#endif From patchwork Mon May 10 17:24:39 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1476601 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=M6DZO/vr; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ff7Hy4zn2z9sWD for ; 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Mon, 10 May 2021 12:25:13 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 10 May 2021 12:25:13 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP1nd023176; Mon, 10 May 2021 12:25:11 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: , Nishanth Menon , Dave Gerlach , Tero Kristo , Tom Rini Subject: [PATCH 4/7] ARM: dts: j72xx-r5-common-proc-board: Add DM firmware node Date: Mon, 10 May 2021 22:54:39 +0530 Message-ID: <20210510172442.11146-5-vigneshr@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510172442.11146-1-vigneshr@ti.com> References: <20210510172442.11146-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add DM firmware node which will provide DM services during R5 SPL stage. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 17 +++++++++++++++++ arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 18 ++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index 0491432060..9963746c1d 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -79,6 +79,16 @@ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; mbox-names = "tx", "rx"; }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + u-boot,dm-spl; + }; }; &dmsc { @@ -276,4 +286,11 @@ }; }; +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; #include "k3-j7200-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 4e8422e662..0542b2f8b8 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -76,6 +76,16 @@ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; #thermal-sensor-cells = <1>; }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <3>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&mcu_secproxy 21>, + <&mcu_secproxy 23>; + u-boot,dm-spl; + }; }; &cbass_main { @@ -345,3 +355,11 @@ u-boot,dm-spl; }; }; + +&mcu_ringacc { + ti,sci = <&dm_tifs>; +}; + +&mcu_udmap { + ti,sci = <&dm_tifs>; +}; From patchwork Mon May 10 17:24:40 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1476602 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=PJlAHOiF; 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Mon, 10 May 2021 12:25:16 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 10 May 2021 12:25:16 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP1ne023176; Mon, 10 May 2021 12:25:14 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: , Nishanth Menon , Dave Gerlach , Tero Kristo , Tom Rini Subject: [PATCH 5/7] ARM: dts: k3: Add cfg register space for ringacc and udmap Date: Mon, 10 May 2021 22:54:40 +0530 Message-ID: <20210510172442.11146-6-vigneshr@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510172442.11146-1-vigneshr@ti.com> References: <20210510172442.11146-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges. Signed-off-by: Vignesh Raghavendra --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ 3 files changed, 54 insertions(+) diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index b0602d1dad..2840258518 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -35,11 +35,25 @@ u-boot,dm-spl; ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; ti,dma-ring-reset-quirk; }; dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index c3aae65b39..41ce9fcb59 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -40,6 +40,32 @@ chipid@43000014 { u-boot,dm-spl; }; + + mcu-navss{ + u-boot,dm-spl; + + ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + u-boot,dm-spl; + }; + + dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + u-boot,dm-spl; + }; + }; }; &secure_proxy_main { diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 1135de5a92..ed64f2720d 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -54,10 +54,24 @@ u-boot,dm-spl; ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; }; dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; u-boot,dm-spl; }; }; From patchwork Mon May 10 17:24:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1476603 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=igx3HtmH; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4Ff7JP6bc3z9sWD for ; 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Mon, 10 May 2021 12:25:18 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Mon, 10 May 2021 12:25:18 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP1nf023176; Mon, 10 May 2021 12:25:16 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: , Nishanth Menon , Dave Gerlach , Tero Kristo , Tom Rini Subject: [PATCH 6/7] soc: ti: k3-navss-ringacc: Add support for native configuration of rings Date: Mon, 10 May 2021 22:54:41 +0530 Message-ID: <20210510172442.11146-7-vigneshr@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510172442.11146-1-vigneshr@ti.com> References: <20210510172442.11146-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup Ring Cfg registers. Add support for the same. Note that we still need to send RING_CFG message to TIFS via TISCI client driver in order to open up firewalls around Rings. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra --- drivers/soc/ti/k3-navss-ringacc-u-boot.c | 61 ++++++++++++++++++++++++ drivers/soc/ti/k3-navss-ringacc.c | 36 ++++++++++++-- 2 files changed, 94 insertions(+), 3 deletions(-) create mode 100644 drivers/soc/ti/k3-navss-ringacc-u-boot.c diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c b/drivers/soc/ti/k3-navss-ringacc-u-boot.c new file mode 100644 index 0000000000..f958239c2a --- /dev/null +++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator + * Manager (RA) subsystem driver + * + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +struct k3_nav_ring_cfg_regs { + u32 resv_64[16]; + u32 ba_lo; /* Ring Base Address Lo Register */ + u32 ba_hi; /* Ring Base Address Hi Register */ + u32 size; /* Ring Size Register */ + u32 event; /* Ring Event Register */ + u32 orderid; /* Ring OrderID Register */ +}; + +#define KNAV_RINGACC_CFG_REGS_STEP 0x100 + +#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK GENMASK(15, 0) + +#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK GENMASK(31, 30) +#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT (30) + +#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24) +#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT (24) + +static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring) +{ + writel(0, &ring->cfg->size); +} + +static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode) +{ + u32 val; + + val = readl(&ring->cfg->size); + val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK; + val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT; + writel(val, &ring->cfg->size); +} + +static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring) +{ + writel(0, &ring->cfg->ba_hi); + writel(0, &ring->cfg->ba_lo); + writel(0, &ring->cfg->size); +} + +static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring) +{ + u32 val; + + writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo); + writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi); + + val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT | + ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT | + ring->size; + writel(val, &ring->cfg->size); +} diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c index b5a5c9da98..f110d78ce1 100644 --- a/drivers/soc/ti/k3-navss-ringacc.c +++ b/drivers/soc/ti/k3-navss-ringacc.c @@ -124,6 +124,7 @@ struct k3_nav_ring_state { /** * struct k3_nav_ring - RA Ring descriptor * + * @cfg - Ring configuration registers * @rt - Ring control/status registers * @fifos - Ring queues registers * @ring_mem_dma - Ring buffer dma address @@ -138,6 +139,7 @@ struct k3_nav_ring_state { * @use_count - Use count for shared rings */ struct k3_nav_ring { + struct k3_nav_ring_cfg_regs __iomem *cfg; struct k3_nav_ring_rt_regs __iomem *rt; struct k3_nav_ring_fifo_regs __iomem *fifos; dma_addr_t ring_mem_dma; @@ -195,6 +197,8 @@ struct k3_nav_ringacc { bool dual_ring; }; +#include "k3-navss-ringacc-u-boot.c" + static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring) { return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK; @@ -330,6 +334,9 @@ static void k3_ringacc_ring_reset_sci(struct k3_nav_ring *ring) struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_reset_raw(ring); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci, TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID, @@ -362,6 +369,9 @@ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_nav_ring *ring, struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_reconfig_qmode_raw(ring, mode); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci, TI_SCI_MSG_VALUE_RM_RING_MODE_VALID, @@ -442,6 +452,9 @@ static void k3_ringacc_ring_free_sci(struct k3_nav_ring *ring) struct k3_nav_ringacc *ringacc = ring->parent; int ret; + if (IS_ENABLED(CONFIG_K3_DM_FW)) + return k3_ringacc_ring_free_raw(ring); + ret = ringacc->tisci_ring_ops->config( ringacc->tisci, TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER, @@ -531,11 +544,21 @@ static int k3_nav_ringacc_ring_cfg_sci(struct k3_nav_ring *ring) ring->mode, ring->elm_size, 0); - if (ret) + if (ret) { dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n", ret, ring_idx); + return ret; + } - return ret; + /* + * Above TI SCI call handles firewall configuration, cfg + * register configuration still has to be done locally in + * absence of RM services. + */ + if (IS_ENABLED(CONFIG_K3_DM_FW)) + k3_nav_ringacc_ring_cfg_raw(ring); + + return 0; } static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg) @@ -951,13 +974,18 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc) static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc) { - void __iomem *base_rt; + void __iomem *base_cfg, *base_rt; int ret, i; ret = k3_nav_ringacc_probe_dt(ringacc); if (ret) return ret; + base_cfg = dev_remap_addr_name(dev, "cfg"); + pr_debug("cfg %p\n", base_cfg); + if (!base_cfg) + return -EINVAL; + base_rt = (uint32_t *)devfdt_get_addr_name(dev, "rt"); pr_debug("rt %p\n", base_rt); if (IS_ERR(base_rt)) @@ -975,6 +1003,8 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa return -ENOMEM; for (i = 0; i < ringacc->num_rings; i++) { + ringacc->rings[i].cfg = base_cfg + + KNAV_RINGACC_CFG_REGS_STEP * i; ringacc->rings[i].rt = base_rt + KNAV_RINGACC_RT_REGS_STEP * i; ringacc->rings[i].parent = ringacc; From patchwork Mon May 10 17:24:42 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1476604 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 10 May 2021 12:25:21 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 14AHP1ng023176; Mon, 10 May 2021 12:25:19 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: , Nishanth Menon , Dave Gerlach , Tero Kristo , Tom Rini Subject: [PATCH 7/7] dma: ti: k3-udma: Add support for native configuration of chan/flow Date: Mon, 10 May 2021 22:54:42 +0530 Message-ID: <20210510172442.11146-8-vigneshr@ti.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210510172442.11146-1-vigneshr@ti.com> References: <20210510172442.11146-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean In absence of Device Manager (DM) services such as at R5 SPL stage, driver will have to natively setup TCHAN/RCHAN/RFLOW cfg registers. Add support for the same. Note that we still need to send chan/flow cfg message to TIFS via TISCI client driver in order to open up firewalls around chan/flow but setting up of cfg registers is handled locally. U-Boot specific code is in a separate file included in main driver so as to maintain similarity with kernel driver in order to ease porting of code in future. Signed-off-by: Vignesh Raghavendra --- drivers/dma/ti/k3-udma-u-boot.c | 177 ++++++++++++++++++++++++++++++++ drivers/dma/ti/k3-udma.c | 42 +++++++- 2 files changed, 215 insertions(+), 4 deletions(-) create mode 100644 drivers/dma/ti/k3-udma-u-boot.c diff --git a/drivers/dma/ti/k3-udma-u-boot.c b/drivers/dma/ti/k3-udma-u-boot.c new file mode 100644 index 0000000000..3e04f551e2 --- /dev/null +++ b/drivers/dma/ti/k3-udma-u-boot.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com + */ + +#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT (16) + +/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */ +#define UDMA_RFLOW_SRCTAG_NONE 0 +#define UDMA_RFLOW_SRCTAG_CFG_TAG 1 +#define UDMA_RFLOW_SRCTAG_FLOW_ID 2 +#define UDMA_RFLOW_SRCTAG_SRC_TAG 4 + +#define UDMA_RFLOW_DSTTAG_NONE 0 +#define UDMA_RFLOW_DSTTAG_CFG_TAG 1 +#define UDMA_RFLOW_DSTTAG_FLOW_ID 2 +#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4 +#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5 + +#define UDMA_RFLOW_RFC_DEFAULT \ + ((UDMA_RFLOW_SRCTAG_NONE << UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT) | \ + (UDMA_RFLOW_SRCTAG_SRC_TAG << UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT) | \ + (UDMA_RFLOW_DSTTAG_DST_TAG_HI << UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT) | \ + (UDMA_RFLOW_DSTTAG_DST_TAG_LO << UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT)) + +#define UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT (16) + +/* TCHAN */ +static inline u32 udma_tchan_read(struct udma_tchan *tchan, int reg) +{ + if (!tchan) + return 0; + return udma_read(tchan->reg_chan, reg); +} + +static inline void udma_tchan_write(struct udma_tchan *tchan, int reg, u32 val) +{ + if (!tchan) + return; + udma_write(tchan->reg_chan, reg, val); +} + +static inline void udma_tchan_update_bits(struct udma_tchan *tchan, int reg, + u32 mask, u32 val) +{ + if (!tchan) + return; + udma_update_bits(tchan->reg_chan, reg, mask, val); +} + +/* RCHAN */ +static inline u32 udma_rchan_read(struct udma_rchan *rchan, int reg) +{ + if (!rchan) + return 0; + return udma_read(rchan->reg_chan, reg); +} + +static inline void udma_rchan_write(struct udma_rchan *rchan, int reg, u32 val) +{ + if (!rchan) + return; + udma_write(rchan->reg_chan, reg, val); +} + +static inline void udma_rchan_update_bits(struct udma_rchan *rchan, int reg, + u32 mask, u32 val) +{ + if (!rchan) + return; + udma_update_bits(rchan->reg_chan, reg, mask, val); +} + +/* RFLOW */ +static inline u32 udma_rflow_read(struct udma_rflow *rflow, int reg) +{ + if (!rflow) + return 0; + return udma_read(rflow->reg_rflow, reg); +} + +static inline void udma_rflow_write(struct udma_rflow *rflow, int reg, u32 val) +{ + if (!rflow) + return; + udma_write(rflow->reg_rflow, reg, val); +} + +static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg, + u32 mask, u32 val) +{ + if (!rflow) + return; + udma_update_bits(rflow->reg_rflow, reg, mask, val); +} + +static void udma_alloc_tchan_raw(struct udma_chan *uc) +{ + u32 mode, fetch_size; + + if (uc->config.pkt_mode) + mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR; + else + mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR; + + udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG, + UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode); + + if (uc->config.dir == DMA_MEM_TO_MEM) + fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2; + else + fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, + uc->config.psd_size, 0) >> 2; + + udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG, + UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size); + udma_tchan_write(uc->tchan, UDMA_TCHAN_TCQ_REG, + k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring)); +} + +static void udma_alloc_rchan_raw(struct udma_chan *uc) +{ + struct udma_dev *ud = uc->ud; + int fd_ring = k3_nav_ringacc_get_ring_id(uc->rflow->fd_ring); + int rx_ring = k3_nav_ringacc_get_ring_id(uc->rflow->r_ring); + int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring); + u32 rx_einfo_present = 0, rx_psinfo_present = 0; + u32 mode, fetch_size, rxcq_num; + + if (uc->config.pkt_mode) + mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR; + else + mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR; + + udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG, + UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode); + + if (uc->config.dir == DMA_MEM_TO_MEM) { + fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2; + rxcq_num = tc_ring; + } else { + fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib, + uc->config.psd_size, 0) >> 2; + rxcq_num = rx_ring; + } + + udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG, + UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size); + udma_rchan_write(uc->rchan, UDMA_RCHAN_RCQ_REG, rxcq_num); + + if (uc->config.dir == DMA_MEM_TO_MEM) + return; + + if (ud->match_data->type == DMA_TYPE_UDMA && + uc->rflow->id != uc->rchan->id && + uc->config.dir != DMA_MEM_TO_MEM) + udma_rchan_write(uc->rchan, UDMA_RCHAN_RFLOW_RNG_REG, uc->rflow->id | + 1 << UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT); + + if (uc->config.needs_epib) + rx_einfo_present = UDMA_RFLOW_RFA_EINFO; + + if (uc->config.psd_size) + rx_psinfo_present = UDMA_RFLOW_RFA_PSINFO; + + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(A), + rx_einfo_present | rx_psinfo_present | rxcq_num); + + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(C), UDMA_RFLOW_RFC_DEFAULT); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(D), + fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(E), + fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(G), fd_ring); + udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(H), + fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT); +} diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 601868d7fc..411edef3a7 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -48,6 +48,9 @@ enum udma_mmr { MMR_BCHANRT, MMR_RCHANRT, MMR_TCHANRT, + MMR_RCHAN, + MMR_TCHAN, + MMR_RFLOW, MMR_LAST, }; @@ -56,9 +59,13 @@ static const char * const mmr_names[] = { [MMR_BCHANRT] = "bchanrt", [MMR_RCHANRT] = "rchanrt", [MMR_TCHANRT] = "tchanrt", + [MMR_RCHAN] = "rchan", + [MMR_TCHAN] = "tchan", + [MMR_RFLOW] = "rflow", }; struct udma_tchan { + void __iomem *reg_chan; void __iomem *reg_rt; int id; @@ -71,12 +78,14 @@ struct udma_tchan { #define udma_bchan udma_tchan struct udma_rflow { + void __iomem *reg_rflow; int id; struct k3_nav_ring *fd_ring; /* Free Descriptor ring */ struct k3_nav_ring *r_ring; /* Receive ring */ }; struct udma_rchan { + void __iomem *reg_chan; void __iomem *reg_rt; int id; @@ -335,6 +344,8 @@ static inline char *udma_get_dir_text(enum dma_direction dir) return "invalid"; } +#include "k3-udma-u-boot.c" + static void udma_reset_uchan(struct udma_chan *uc) { memset(&uc->config, 0, sizeof(uc->config)); @@ -1014,10 +1025,20 @@ static int udma_alloc_tchan_sci_req(struct udma_chan *uc) req.txcq_qnum = tc_ring; ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req); - if (ret) + if (ret) { dev_err(ud->dev, "tisci tx alloc failed %d\n", ret); + return ret; + } - return ret; + /* + * Above TI SCI call handles firewall configuration, cfg + * register configuration still has to be done locally in + * absence of RM services. + */ + if (IS_ENABLED(CONFIG_K3_DM_FW)) + udma_alloc_tchan_raw(uc); + + return 0; } static int udma_alloc_rchan_sci_req(struct udma_chan *uc) @@ -1114,11 +1135,21 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc) ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req); - if (ret) + if (ret) { dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n", uc->rchan->id, uc->rflow->id, ret); + return ret; + } - return ret; + /* + * Above TI SCI call handles firewall configuration, cfg + * register configuration still has to be done locally in + * absence of RM services. + */ + if (IS_ENABLED(CONFIG_K3_DM_FW)) + udma_alloc_rchan_raw(uc); + + return 0; } static int udma_alloc_chan_resources(struct udma_chan *uc) @@ -1751,6 +1782,7 @@ static int udma_probe(struct udevice *dev) struct udma_tchan *tchan = &ud->tchans[i]; tchan->id = i; + tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i); tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i); } @@ -1758,6 +1790,7 @@ static int udma_probe(struct udevice *dev) struct udma_rchan *rchan = &ud->rchans[i]; rchan->id = i; + rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i); rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i); } @@ -1765,6 +1798,7 @@ static int udma_probe(struct udevice *dev) struct udma_rflow *rflow = &ud->rflows[i]; rflow->id = i; + rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i); } for (i = 0; i < ud->ch_count; i++) {