From patchwork Mon May 3 06:23:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Green Wan X-Patchwork-Id: 1473043 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FYXxV1BBLz9sW4 for ; Mon, 3 May 2021 16:24:14 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4FA7A824AD; Mon, 3 May 2021 08:24:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 689D3828B3; Mon, 3 May 2021 08:24:07 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from transporter.internal.sifive.com (unknown [64.62.193.209]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 58CCB82054 for ; Mon, 3 May 2021 08:24:04 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=green.wan@sifive.com Received: from gamma15.internal.sifive.com (gamma15.internal.sifive.com [10.14.21.64]) by transporter.internal.sifive.com (Postfix) with ESMTPS id A668120088; Sun, 2 May 2021 23:24:02 -0700 (PDT) Received: from localhost (gamma15.internal.sifive.com [local]) by gamma15.internal.sifive.com (OpenSMTPD) with ESMTPA id c57f3e4f; Mon, 3 May 2021 06:24:02 +0000 (UTC) From: Green Wan To: Cc: Green Wan , Rick Chen , Bin Meng , Sean Anderson , Bin Meng , Simon Glass , Pragnesh Patel , Jagan Teki , Leo Yu-Chi Liang , Brad Kim , u-boot@lists.denx.de Subject: [PATCH 1/2] riscv: cpu: Add callback to init each core Date: Sun, 2 May 2021 23:23:04 -0700 Message-Id: <20210503062306.349882-1-green.wan@sifive.com> X-Mailer: git-send-email 2.31.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan Reviewed-by: Rick Chen Reviewed-by: Bin Meng --- arch/riscv/cpu/cpu.c | 11 +++++++++++ arch/riscv/cpu/start.S | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 85592f5bee..296e458db4 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -140,3 +140,14 @@ int arch_early_init_r(void) { return riscv_cpu_probe(); } + +/** + * harts_early_init() - A callback function called by start.S to configure + * feature settings of each hart. + * + * In a multi-core system, memory access shall be careful here, it shall + * take care of race conditions. + */ +__weak void harts_early_init(void) +{ +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8589509e01..308b0a97a5 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -117,6 +117,10 @@ call_board_init_f_0: mv sp, a0 #endif + /* Configure proprietary settings and customized CSRs of harts */ +call_harts_early_init: + jal harts_early_init + #ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts From patchwork Mon May 3 06:23:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Green Wan X-Patchwork-Id: 1473044 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FYXxj0yz2z9sW5 for ; Mon, 3 May 2021 16:24:25 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 75B8282AC4; Mon, 3 May 2021 08:24:21 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id ECAB282AC4; Mon, 3 May 2021 08:24:18 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from transporter.internal.sifive.com (unknown [64.62.193.209]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B9E7E82AA3 for ; Mon, 3 May 2021 08:24:14 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=green.wan@sifive.com Received: from gamma15.internal.sifive.com (gamma15.internal.sifive.com [10.14.21.64]) by transporter.internal.sifive.com (Postfix) with ESMTPS id 81C9320088; Sun, 2 May 2021 23:24:13 -0700 (PDT) Received: from localhost (gamma15.internal.sifive.com [local]) by gamma15.internal.sifive.com (OpenSMTPD) with ESMTPA id 226e62c7; Mon, 3 May 2021 06:24:13 +0000 (UTC) From: Green Wan To: Cc: Green Wan , Sean Anderson , Bin Meng , Rick Chen , Bin Meng , Simon Glass , Pragnesh Patel , Jagan Teki , Leo Yu-Chi Liang , Brad Kim , u-boot@lists.denx.de Subject: [PATCH 2/2] riscv: cpu: fu740: clear feature disable CSR Date: Sun, 2 May 2021 23:23:05 -0700 Message-Id: <20210503062306.349882-2-green.wan@sifive.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20210503062306.349882-1-green.wan@sifive.com> References: <20210503062306.349882-1-green.wan@sifive.com> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan Reviewed-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c index ea0b2283a2..55e30346ff 100644 --- a/arch/riscv/cpu/fu740/spl.c +++ b/arch/riscv/cpu/fu740/spl.c @@ -6,6 +6,9 @@ #include #include +#include + +#define CSR_U74_FEATURE_DISABLE 0x7c1 int spl_soc_init(void) { @@ -21,3 +24,15 @@ int spl_soc_init(void) return 0; } + +void harts_early_init(void) +{ + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); +}