From patchwork Tue Apr 13 08:07:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1465589 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; envelope-from=openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20161025 header.b=se7XjXRY; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FKJCG0kMpz9sVw for ; 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When there are no callers it is removed from the final u-boot binary. Instead of relying on the linker to do this, only add it to the build system if enabled. Signed-off-by: Joel Stanley Reviewed-by: Klaus Heinrich Kiwi --- arch/arm/mach-aspeed/ast2600/Makefile | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-aspeed/ast2600/Makefile b/arch/arm/mach-aspeed/ast2600/Makefile index 0abac4c233e4..aafc4b2fe37f 100644 --- a/arch/arm/mach-aspeed/ast2600/Makefile +++ b/arch/arm/mach-aspeed/ast2600/Makefile @@ -1,2 +1,3 @@ -obj-y += platform.o board_common.o scu_info.o utils.o cache.o crypto.o aspeed_verify.o +obj-y += platform.o board_common.o scu_info.o utils.o cache.o +obj-$(CONFIG_ASPEED_SECURE_BOOT) += crypto.o aspeed_verify.o obj-$(CONFIG_SPL_BUILD) += spl.o spl_boot.o From patchwork Tue Apr 13 08:07:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1465592 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; 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Tue, 13 Apr 2021 01:08:12 -0700 (PDT) Received: from voyager.lan ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id nh24sm1443507pjb.38.2021.04.13.01.08.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 01:08:12 -0700 (PDT) From: Joel Stanley To: openbmc@lists.ozlabs.org, Klaus Heinrich Kiwi , Andrew Jeffery Subject: [PATCH u-boot v2019.04-aspeed-openbmc 02/11] ast2600: Specify boot order Date: Tue, 13 Apr 2021 17:37:46 +0930 Message-Id: <20210413080755.73572-3-joel@jms.id.au> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210413080755.73572-1-joel@jms.id.au> References: <20210413080755.73572-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Try to boot from the strapped device, but fall back to the UART. Signed-off-by: Joel Stanley Reviewed-by: Klaus Heinrich Kiwi --- arch/arm/mach-aspeed/ast2600/spl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 54f89b0e8431..d794421b4070 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -51,6 +51,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NONE; } +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + spl_boot_list[1] = ASPEED_BOOT_DEVICE_UART; +} + #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { From patchwork Tue Apr 13 08:07:47 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1465594 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; 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Tue, 13 Apr 2021 01:08:16 -0700 (PDT) Received: from voyager.lan ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id nh24sm1443507pjb.38.2021.04.13.01.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 01:08:15 -0700 (PDT) From: Joel Stanley To: openbmc@lists.ozlabs.org, Klaus Heinrich Kiwi , Andrew Jeffery Subject: [PATCH u-boot v2019.04-aspeed-openbmc 03/11] ast2600: Configure emmc boot options Date: Tue, 13 Apr 2021 17:37:47 +0930 Message-Id: <20210413080755.73572-4-joel@jms.id.au> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210413080755.73572-1-joel@jms.id.au> References: <20210413080755.73572-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Assume a u-boot that is 1MB, minus 64KB for the SPL, that is linked and loaded to an address in DRAM. Signed-off-by: Joel Stanley --- include/configs/aspeed-common.h | 2 +- include/configs/evb_ast2600a1_spl.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h index 876958735b75..093c59c0eadc 100755 --- a/include/configs/aspeed-common.h +++ b/include/configs/aspeed-common.h @@ -82,6 +82,6 @@ #define PHY_ANEG_TIMEOUT 800 /* Uboot size */ -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN ((1024 - 64) * 1024) #endif /* __ASPEED_COMMON_CONFIG_H */ diff --git a/include/configs/evb_ast2600a1_spl.h b/include/configs/evb_ast2600a1_spl.h index a39988820add..4d8405e9dbc0 100644 --- a/include/configs/evb_ast2600a1_spl.h +++ b/include/configs/evb_ast2600a1_spl.h @@ -13,6 +13,7 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000) #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_UBOOT_START 0x81000000 /* Memory Info */ #define CONFIG_SYS_LOAD_ADDR 0x83000000 @@ -32,4 +33,7 @@ #define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0xf0000 /* 960KiB (1M - 64K) */ + #endif /* __CONFIG_H */ From patchwork Tue Apr 13 08:07:48 2021 Content-Type: text/plain; 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There's also the common SPL code for loading boot images from various devices that the system can be configured to use. This will use the Aspeed device types first and then fall back to the generic ones. Signed-off-by: Joel Stanley Reviewed-by: Klaus Heinrich Kiwi --- arch/arm/mach-aspeed/ast2600/spl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index d794421b4070..527e14f8e3b6 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -34,6 +34,7 @@ void board_init_f(ulong dummy) u32 spl_boot_device(void) { +#if IS_ENABLED(CONFIG_ASPEED_SECURE_BOOT) switch (aspeed_bootmode()) { case AST_BOOTMODE_EMMC: return (IS_ENABLED(CONFIG_ASPEED_SECURE_BOOT))? @@ -47,6 +48,15 @@ u32 spl_boot_device(void) default: break; } +#endif + switch (aspeed_bootmode()) { + case AST_BOOTMODE_EMMC: + return BOOT_DEVICE_MMC1; + case AST_BOOTMODE_SPI: + return BOOT_DEVICE_SPI; + case AST_BOOTMODE_UART: + return BOOT_DEVICE_UART; + } return BOOT_DEVICE_NONE; } From patchwork Tue Apr 13 08:07:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1465596 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Tue, 13 Apr 2021 01:08:22 -0700 (PDT) Received: from voyager.lan ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id nh24sm1443507pjb.38.2021.04.13.01.08.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 01:08:21 -0700 (PDT) From: Joel Stanley To: openbmc@lists.ozlabs.org, Klaus Heinrich Kiwi , Andrew Jeffery Subject: [PATCH u-boot v2019.04-aspeed-openbmc 05/11] config: ast2600: Enable common eMMC SPL loader Date: Tue, 13 Apr 2021 17:37:49 +0930 Message-Id: <20210413080755.73572-6-joel@jms.id.au> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210413080755.73572-1-joel@jms.id.au> References: <20210413080755.73572-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Notabily the link address changes, as this is used as the load address by the loader. Given the Aspeed loaders are linking u-boot at 0x10000 but running it from RAM, the u-boot relocation code must be fine with this setup. Signed-off-by: Joel Stanley --- configs/ast2600_openbmc_spl_emmc_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/ast2600_openbmc_spl_emmc_defconfig b/configs/ast2600_openbmc_spl_emmc_defconfig index 6daf6343478b..e59d3595ebf0 100644 --- a/configs/ast2600_openbmc_spl_emmc_defconfig +++ b/configs/ast2600_openbmc_spl_emmc_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/mach-aspeed/ast2600/u-boot-spl.lds" CONFIG_ARCH_ASPEED=y -CONFIG_SYS_TEXT_BASE=0x10000 +CONFIG_SYS_TEXT_BASE=0x81000000 CONFIG_ASPEED_AST2600=y CONFIG_ASPEED_UBOOT_SPI_BASE=0x10000 CONFIG_ASPEED_UBOOT_SPI_SIZE=0xd0000 @@ -47,11 +47,12 @@ CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_ARCH_EARLY_INIT_R=y CONFIG_BOARD_EARLY_INIT_F=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_RAM_SUPPORT=y From patchwork Tue Apr 13 08:07:50 2021 Content-Type: text/plain; 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+ + if (hash_lookup_algo(algo_name, &algo)) { + debug("Unsupported hash alogrithm\n"); + return -1; + } + + algo->hash_func_ws(data, data_len, value, algo->chunk_size); + *value_len = algo->digest_size; + + return 0; + +#if 0 if (IMAGE_ENABLE_CRC32 && strcmp(algo, "crc32") == 0) { *((uint32_t *)value) = crc32_wd(0, data, data_len, CHUNKSZ_CRC32); @@ -1167,6 +1180,7 @@ int calculate_hash(const void *data, int data_len, const char *algo, return -1; } return 0; +#endif } static int fit_image_check_hash(const void *fit, int noffset, const void *data, From patchwork Tue Apr 13 08:07:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1465599 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; 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Tue, 13 Apr 2021 01:08:29 -0700 (PDT) Received: from voyager.lan ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id nh24sm1443507pjb.38.2021.04.13.01.08.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 01:08:28 -0700 (PDT) From: Joel Stanley To: openbmc@lists.ozlabs.org, Klaus Heinrich Kiwi , Andrew Jeffery Subject: [PATCH u-boot v2019.04-aspeed-openbmc 07/11] hash: Allow for SHA512 hardware implementations Date: Tue, 13 Apr 2021 17:37:51 +0930 Message-Id: <20210413080755.73572-8-joel@jms.id.au> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210413080755.73572-1-joel@jms.id.au> References: <20210413080755.73572-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Similar to support for SHA1 and SHA256, allow the use of hardware hashing engine by enabling the algorithm and setting CONFIG_SHA_HW_ACCEL / CONFIG_SHA_PROG_HW_ACCEL. Signed-off-by: Joel Stanley Reviewed-by: Klaus Heinrich Kiwi --- common/hash.c | 24 ++++++++++++++++++++++-- include/hw_sha.h | 26 ++++++++++++++++++++++++++ lib/Kconfig | 15 +++++++-------- 3 files changed, 55 insertions(+), 10 deletions(-) diff --git a/common/hash.c b/common/hash.c index c00ec4d36c41..a19cba07d779 100644 --- a/common/hash.c +++ b/common/hash.c @@ -86,7 +86,7 @@ static int hash_finish_sha256(struct hash_algo *algo, void *ctx, void } #endif -#if defined(CONFIG_SHA384) +#if defined(CONFIG_SHA384) && !defined(CONFIG_SHA_PROG_HW_ACCEL) static int hash_init_sha384(struct hash_algo *algo, void **ctxp) { sha512_context *ctx = malloc(sizeof(sha512_context)); @@ -114,7 +114,7 @@ static int hash_finish_sha384(struct hash_algo *algo, void *ctx, void } #endif -#if defined(CONFIG_SHA512) +#if defined(CONFIG_SHA512) && !defined(CONFIG_SHA_PROG_HW_ACCEL) static int hash_init_sha512(struct hash_algo *algo, void **ctxp) { sha512_context *ctx = malloc(sizeof(sha512_context)); @@ -249,10 +249,20 @@ static struct hash_algo hash_algo[] = { .name = "sha384", .digest_size = SHA384_SUM_LEN, .chunk_size = CHUNKSZ_SHA384, +#ifdef CONFIG_SHA_HW_ACCEL + .hash_func_ws = hw_sha384, +#else .hash_func_ws = sha384_csum_wd, +#endif +#ifdef CONFIG_SHA_PROG_HW_ACCEL + .hash_init = hw_sha_init, + .hash_update = hw_sha_update, + .hash_finish = hw_sha_finish, +#else .hash_init = hash_init_sha384, .hash_update = hash_update_sha384, .hash_finish = hash_finish_sha384, +#endif }, #endif #ifdef CONFIG_SHA512 @@ -260,10 +270,20 @@ static struct hash_algo hash_algo[] = { .name = "sha512", .digest_size = SHA512_SUM_LEN, .chunk_size = CHUNKSZ_SHA512, +#ifdef CONFIG_SHA_HW_ACCEL + .hash_func_ws = hw_sha512, +#else .hash_func_ws = sha512_csum_wd, +#endif +#ifdef CONFIG_SHA_PROG_HW_ACCEL + .hash_init = hw_sha_init, + .hash_update = hw_sha_update, + .hash_finish = hw_sha_finish, +#else .hash_init = hash_init_sha512, .hash_update = hash_update_sha512, .hash_finish = hash_finish_sha512, +#endif }, #endif { diff --git a/include/hw_sha.h b/include/hw_sha.h index 991e496a3cb2..8cdf821218a0 100644 --- a/include/hw_sha.h +++ b/include/hw_sha.h @@ -8,6 +8,32 @@ #define __HW_SHA_H #include +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 64 bytes are copied to pout[0]...pout[63]. Thus, a user + * should allocate at least 64 bytes at pOut in advance. + * @param chunk_size chunk size for sha512 + */ +void hw_sha512(const uchar * in_addr, uint buflen, + uchar * out_addr, uint chunk_size); + +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 48 bytes are copied to pout[0]...pout[47]. Thus, a user + * should allocate at least 48 bytes at pOut in advance. + * @param chunk_size chunk size for sha384 + */ +void hw_sha384(const uchar * in_addr, uint buflen, + uchar * out_addr, uint chunk_size); + /** * Computes hash value of input pbuf using h/w acceleration * diff --git a/lib/Kconfig b/lib/Kconfig index 984a783fd16f..f77272d0a94a 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -273,19 +273,18 @@ config SHA384 config SHA_HW_ACCEL bool "Enable hashing using hardware" help - This option enables hardware acceleration - for SHA1/SHA256 hashing. - This affects the 'hash' command and also the - hash_lookup_algo() function. + This option enables hardware acceleration for SHA hashing. + This affects the 'hash' command and also the hash_lookup_algo() + function. config SHA_PROG_HW_ACCEL bool "Enable Progressive hashing support using hardware" depends on SHA_HW_ACCEL help - This option enables hardware-acceleration for - SHA1/SHA256 progressive hashing. - Data can be streamed in a block at a time and the hashing - is performed in hardware. + This option enables hardware-acceleration for SHA progressive + hashing. + Data can be streamed in a block at a time and the hashing is + performed in hardware. config MD5 bool From patchwork Tue Apr 13 08:07:52 2021 Content-Type: text/plain; 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Signed-off-by: Joel Stanley Reviewed-by: Klaus Heinrich Kiwi --- arch/arm/dts/ast2600-rainier.dts | 5 +++++ arch/arm/dts/ast2600-tacoma.dts | 5 +++++ arch/arm/dts/ast2600.dtsi | 9 +++++++++ arch/arm/dts/ast2600a1-evb.dts | 4 ++++ 4 files changed, 23 insertions(+) diff --git a/arch/arm/dts/ast2600-rainier.dts b/arch/arm/dts/ast2600-rainier.dts index 67e177baf1bd..aae507b4c23d 100755 --- a/arch/arm/dts/ast2600-rainier.dts +++ b/arch/arm/dts/ast2600-rainier.dts @@ -103,3 +103,8 @@ pinctrl-0 = <&pinctrl_emmc_default>; sdhci-drive-type = <1>; }; + +&hace { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/ast2600-tacoma.dts b/arch/arm/dts/ast2600-tacoma.dts index 85d1e3902b11..c8ed5e35a74c 100755 --- a/arch/arm/dts/ast2600-tacoma.dts +++ b/arch/arm/dts/ast2600-tacoma.dts @@ -94,3 +94,8 @@ pinctrl-0 = <&pinctrl_emmc_default>; sdhci-drive-type = <1>; }; + +&hace { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index e619f7118886..57ea98a47b67 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -304,6 +304,15 @@ }; + hace: hace@1e6d0000 { + compatible = "aspeed,ast2600-hace"; + reg = <0x1e6d0000 0x200>; + interrupts = ; + clocks = <&scu ASPEED_CLK_GATE_YCLK>; + clock-names = "yclk"; + status = "disabled"; + }; + smp-memram@0 { compatible = "aspeed,ast2600-smpmem", "syscon"; reg = <0x1e6e2180 0x40>; diff --git a/arch/arm/dts/ast2600a1-evb.dts b/arch/arm/dts/ast2600a1-evb.dts index 2827e00c0eb4..2ae6e3bdf192 100644 --- a/arch/arm/dts/ast2600a1-evb.dts +++ b/arch/arm/dts/ast2600a1-evb.dts @@ -301,3 +301,7 @@ &display_port { status = "okay"; }; + +&hace { + status = "okay"; +}; From patchwork Tue Apr 13 08:07:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1465602 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=112.213.38.117; helo=lists.ozlabs.org; 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Tue, 13 Apr 2021 01:08:35 -0700 (PDT) Received: from voyager.lan ([45.124.203.14]) by smtp.gmail.com with ESMTPSA id nh24sm1443507pjb.38.2021.04.13.01.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Apr 2021 01:08:35 -0700 (PDT) From: Joel Stanley To: openbmc@lists.ozlabs.org, Klaus Heinrich Kiwi , Andrew Jeffery Subject: [PATCH u-boot v2019.04-aspeed-openbmc 09/11] clk: aspeed: Add HACE yclk to ast2600 Date: Tue, 13 Apr 2021 17:37:53 +0930 Message-Id: <20210413080755.73572-10-joel@jms.id.au> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210413080755.73572-1-joel@jms.id.au> References: <20210413080755.73572-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Signed-off-by: Joel Stanley Reviewed-by: Klaus Heinrich Kiwi --- drivers/clk/aspeed/clk_ast2600.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index 4c00008a5dfd..ba9a0a0a9a5a 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -1066,6 +1066,25 @@ static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu) return 0; } +/* also known as yclk */ +static ulong ast2600_enable_haceclk(struct ast2600_scu *scu) +{ + u32 reset_bit; + u32 clkstop_bit; + + reset_bit = BIT(ASPEED_RESET_HACE); + clkstop_bit = BIT(13); + + writel(reset_bit, &scu->sysreset_ctrl1); + udelay(100); + writel(clkstop_bit, &scu->clk_stop_clr_ctrl1); + mdelay(20); + + writel(reset_bit, &scu->sysreset_clr_ctrl1); + + return 0; +} + static int ast2600_clk_enable(struct clk *clk) { struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); @@ -1104,6 +1123,9 @@ static int ast2600_clk_enable(struct clk *clk) case ASPEED_CLK_GATE_USBPORT2CLK: ast2600_enable_usbbhclk(priv->scu); break; + case ASPEED_CLK_GATE_YCLK: + ast2600_enable_haceclk(priv->scu); + break; default: pr_debug("can't enable clk \n"); return -ENOENT; From patchwork Tue Apr 13 08:07:54 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1465603 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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This driver uses it in a polling mode to perform hash calculations over buffers placed in DRAM. Co-developed-by: Klaus Heinrich Kiwi Signed-off-by: Joel Stanley Signed-off-by: Klaus Heinrich Kiwi Signed-off-by: Klaus Heinrich Kiwi --- drivers/crypto/Kconfig | 16 +++ drivers/crypto/Makefile | 1 + drivers/crypto/aspeed_hace.c | 250 +++++++++++++++++++++++++++++++++++ 3 files changed, 267 insertions(+) create mode 100644 drivers/crypto/aspeed_hace.c diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 1ea116be7503..f78e41e0e9e7 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -2,4 +2,20 @@ menu "Hardware crypto devices" source drivers/crypto/fsl/Kconfig +config ASPEED_HACE + bool "ASPEED Hash and Crypto Engine" + select SHA_HW_ACCEL + select SHA_PROG_HW_ACCEL + depends on ASPEED_AST2600 + help + Select this option to enable a driver for using the SHA engine in + the ASPEED BMC SoCs. + + Enabling this allows the use of SHA operations in hardware without requiring the + SHA software implementations, saving code size. + + Due to hardware limitations it cannot be used with a FIT placed in SPI + FLASH. Data can only be hashed if it is in SDRAM, making this relevant + for MMC and network boot only. + endmenu diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index efbd1d3fca05..ac93b1295954 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -4,5 +4,6 @@ # http://www.samsung.com obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o +obj-$(CONFIG_ASPEED_HACE) += aspeed_hace.o obj-y += rsa_mod_exp/ obj-y += fsl/ diff --git a/drivers/crypto/aspeed_hace.c b/drivers/crypto/aspeed_hace.c new file mode 100644 index 000000000000..473d4d7391b7 --- /dev/null +++ b/drivers/crypto/aspeed_hace.c @@ -0,0 +1,250 @@ +/* + * (C) Copyright ASPEED Technology Inc. + * Copyright 2021 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +#define ASPEED_HACE_STS 0x1C +#define HACE_RSA_ISR BIT(13) +#define HACE_CRYPTO_ISR BIT(12) +#define HACE_HASH_ISR BIT(9) +#define HACE_RSA_BUSY BIT(2) +#define HACE_CRYPTO_BUSY BIT(1) +#define HACE_HASH_BUSY BIT(0) +#define ASPEED_HACE_HASH_SRC 0x20 +#define ASPEED_HACE_HASH_DIGEST_BUFF 0x24 +#define ASPEED_HACE_HASH_KEY_BUFF 0x28 +#define ASPEED_HACE_HASH_DATA_LEN 0x2C +#define HACE_SG_LAST BIT(31) +#define ASPEED_HACE_HASH_CMD 0x30 +#define HACE_SHA_BE_EN BIT(3) +#define HACE_MD5_LE_EN BIT(2) +#define HACE_ALGO_MD5 0 +#define HACE_ALGO_SHA1 BIT(5) +#define HACE_ALGO_SHA224 BIT(6) +#define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) +#define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) +#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) +#define HACE_SG_EN BIT(18) + +#define ASPEED_MAX_SG 32 + +struct aspeed_sg { + u32 len; + u32 addr; +}; + +struct aspeed_hash_ctx { + u32 method; + u32 digest_size; + u32 len; + u32 count; + struct aspeed_sg list[ASPEED_MAX_SG] __attribute__((aligned(8))); +}; + +struct aspeed_hace { + struct clk clk; +}; + +static phys_addr_t base; + +static int aspeed_hace_wait_completion(u32 reg, u32 flag, int timeout_us) +{ + u32 val; + + return readl_poll_timeout(reg, val, (val & flag) == flag, timeout_us); +} + +static int digest_object(const void *src, unsigned int length, void *digest, + u32 method) +{ + if (!((u32)src & BIT(31))) { + debug("HACE src out of bounds: can only copy from SDRAM\n"); + return -EINVAL; + } + + if ((u32)digest & 0x7) { + debug("HACE dest alignment incorrect: %p\n", digest); + return -EINVAL; + } + + writel((u32)src, base + ASPEED_HACE_HASH_SRC); + writel((u32)digest, base + ASPEED_HACE_HASH_DIGEST_BUFF); + writel(length, base + ASPEED_HACE_HASH_DATA_LEN); + writel(HACE_SHA_BE_EN | method, base + ASPEED_HACE_HASH_CMD); + + /* SHA512 hashing appears to have a througput of about 12MB/s */ + return aspeed_hace_wait_completion(base + ASPEED_HACE_STS, + HACE_HASH_ISR, + 1000 + (length >> 3)); +} + +void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + int rc; + + rc = digest_object(pbuf, buf_len, pout, HACE_ALGO_SHA1); + if (rc) + debug("HACE failure: %d\n", rc); +} + +void hw_sha256(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + int rc; + + rc = digest_object(pbuf, buf_len, pout, HACE_ALGO_SHA256); + if (rc) + debug("HACE failure: %d\n", rc); +} + +void hw_sha512(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + int rc; + + rc = digest_object(pbuf, buf_len, pout, HACE_ALGO_SHA512); + if (rc) + debug("HACE failure: %d\n", rc); +} + +#if IS_ENABLED(CONFIG_SHA_PROG_HW_ACCEL) +int hw_sha_init(struct hash_algo *algo, void **ctxp) +{ + struct aspeed_hash_ctx *ctx; + u32 method; + + if (!strcmp(algo->name, "sha1")) { + method = HACE_ALGO_SHA1; + } + else if (!strcmp(algo->name, "sha256")) { + method = HACE_ALGO_SHA256; + } + else if (!strcmp(algo->name, "sha512")) { + method = HACE_ALGO_SHA512; + } + else { + return -ENOTSUPP; + } + + ctx = calloc(1, sizeof(*ctx)); + + if (ctx == NULL) { + debug("Cannot allocate memory for context\n"); + return -ENOMEM; + } + ctx->method = method | HACE_SG_EN; + ctx->digest_size = algo->digest_size; + *ctxp = ctx; + + return 0; +} + +int hw_sha_update(struct hash_algo *algo, void *hash_ctx, const void *buf, + unsigned int size, int is_last) +{ + struct aspeed_hash_ctx *ctx = hash_ctx; + struct aspeed_sg *sg = &ctx->list[ctx->count]; + + if (ctx->count >= ARRAY_SIZE(ctx->list)) { + debug("HACE error: Reached maximum number of hash segments\n"); + free(ctx); + return -EINVAL; + } + + sg->addr = (u32)buf; + sg->len = size; + if (is_last) + sg->len |= HACE_SG_LAST; + + ctx->count++; + ctx->len += size; + + return 0; +} + +int hw_sha_finish(struct hash_algo *algo, void *hash_ctx, void *dest_buf, int size) +{ + struct aspeed_hash_ctx *ctx = hash_ctx; + int rc; + + if (size < ctx->digest_size) { + debug("HACE error: insufficient size on destination buffer\n"); + free(ctx); + return -EINVAL; + } + + rc = digest_object(ctx->list, ctx->len, dest_buf, ctx->method); + if (rc) + debug("HACE Scatter-Gather failure\n"); + + free(ctx); + + return rc; +} +#endif + +static int aspeed_hace_probe(struct udevice *dev) +{ + struct aspeed_hace *hace = dev_get_priv(dev); + int ret; + + ret = clk_get_by_index(dev, 0, &hace->clk); + if (ret < 0) { + debug("Can't get clock for %s: %d\n", dev->name, ret); + return ret; + } + + ret = clk_enable(&hace->clk); + if (ret) { + debug("Failed to enable fsi clock (%d)\n", ret); + return ret; + } + + /* As the crypto code does not pass us any driver state */ + base = devfdt_get_addr(dev); + + return ret; +} + +static int aspeed_hace_remove(struct udevice *dev) +{ + struct aspeed_hace *hace = dev_get_priv(dev); + + clk_disable(&hace->clk); + + return 0; +} + +static const struct udevice_id aspeed_hace_ids[] = { + { .compatible = "aspeed,ast2600-hace" }, + { } +}; + +U_BOOT_DRIVER(aspeed_hace) = { + .name = "aspeed_hace", + .id = UCLASS_MISC, + .of_match = aspeed_hace_ids, + .probe = aspeed_hace_probe, + .remove = aspeed_hace_remove, + .priv_auto_alloc_size = sizeof(struct aspeed_hace), + .flags = DM_FLAG_PRE_RELOC, +}; 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The hash command is useful, and adds only a small amount of binary size given the algorithms are already included in the image. Using hardware acceleration instead of a software implementation saves a significant amount of binary size (approx. 12KB for the SPL). Note that the hardware implementation is only useful when booting from a payload in memory, as is the case with MMC or network boot. It cannot be used when booting from SPI NOR. Signed-off-by: Joel Stanley Reviewed-by: Klaus Heinrich Kiwi --- configs/ast2600_openbmc_spl_emmc_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/ast2600_openbmc_spl_emmc_defconfig b/configs/ast2600_openbmc_spl_emmc_defconfig index e59d3595ebf0..05069084cbc5 100644 --- a/configs/ast2600_openbmc_spl_emmc_defconfig +++ b/configs/ast2600_openbmc_spl_emmc_defconfig @@ -36,6 +36,7 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_ARMV7_PSCI_NR_CPUS=2 CONFIG_NR_DRAM_BANKS=1 CONFIG_FIT=y +CONFIG_FIT_ENABLE_SHA512_SUPPORT=y CONFIG_FIT_SIGNATURE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y @@ -53,6 +54,8 @@ CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x80 +CONFIG_SPL_SHA256_SUPPORT=y +CONFIG_SPL_SHA512_SUPPORT=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_RAM_SUPPORT=y @@ -80,6 +83,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_NCSI=y +CONFIG_CMD_HASH=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -97,6 +101,7 @@ CONFIG_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y +CONFIG_ASPEED_HACE=y CONFIG_DM_GPIO=y CONFIG_ASPEED_GPIO=y CONFIG_DM_I2C=y @@ -135,4 +140,6 @@ CONFIG_USE_TINY_PRINTF=y CONFIG_SPL_TINY_MEMSET=y CONFIG_TPM=y CONFIG_SPL_TPM=y +CONFIG_SHA_HW_ACCEL=y +CONFIG_SHA_PROG_HW_ACCEL=y # CONFIG_EFI_LOADER is not set