From patchwork Sun Sep 10 07:33:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812048 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjVh4gQlz9sQl for ; Sun, 10 Sep 2017 17:34:20 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjVh3WvKzDrch for ; Sun, 10 Sep 2017 17:34:20 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVD0zrYzDrcj for ; Sun, 10 Sep 2017 17:33:55 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVah032370; Sun, 10 Sep 2017 02:33:32 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:17 +1000 Message-Id: <20170910073330.25824-1-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 Subject: [Skiboot] [PATCH v2 01/14] xive: Remove useless memory barriers in VP/EQ inits X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We no longer update "live" memory structures, we use a temporary copy on the stack and update the actual memory structure using the cache watch, so those barriers are pointless. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index e478efc1..fb9257e3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -887,7 +887,6 @@ static void xive_init_default_vp(struct xive_vp *vp, */ vp->w1 = (eq_blk << 28) | eq_idx; vp->w5 = 0xff000000; - lwsync(); vp->w0 = VP_W0_VALID; } @@ -903,7 +902,6 @@ static void xive_init_emu_eq(uint32_t vp_blk, uint32_t vp_idx, eq->w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx); eq->w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio); - eieio(); eq->w0 = EQ_W0_VALID | EQ_W0_ENQUEUE | SETFIELD(EQ_W0_QSIZE, 0ul, EQ_QSIZE_64K) | EQ_W0_FIRMWARE; From patchwork Sun Sep 10 07:33:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjVN5vvgz9sRV for ; Sun, 10 Sep 2017 17:34:04 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjVN3xPKzDrcv for ; Sun, 10 Sep 2017 17:34:04 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVD0dHRzDrch for ; Sun, 10 Sep 2017 17:33:55 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVai032370; Sun, 10 Sep 2017 02:33:34 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:18 +1000 Message-Id: <20170910073330.25824-2-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 02/14] xive: Don't try setting the reserved ACK# field in VPs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" That doesn't work, the HW doesn't implement it in the cache watch facility anyway. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index fb9257e3..9148c5f6 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -882,11 +882,8 @@ static void xive_init_default_vp(struct xive_vp *vp, { memset(vp, 0, sizeof(struct xive_vp)); - /* Stash the EQ base in the pressure relief interrupt field - * and set the ACK# to 0xff to disable pressure relief interrupts - */ + /* Stash the EQ base in the pressure relief interrupt field */ vp->w1 = (eq_blk << 28) | eq_idx; - vp->w5 = 0xff000000; vp->w0 = VP_W0_VALID; } From patchwork Sun Sep 10 07:33:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812055 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjX71B7bz9sQl for ; Sun, 10 Sep 2017 17:35:35 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjX673y5zDrnc for ; Sun, 10 Sep 2017 17:35:34 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVS19LnzDrcx for ; Sun, 10 Sep 2017 17:34:07 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVaj032370; Sun, 10 Sep 2017 02:33:36 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:19 +1000 Message-Id: <20170910073330.25824-3-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 03/14] xive: Ensure pressure relief interrupts are disabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We don't use them and we hijack the VP field with their configuration to store the EQ reference, so make sure the kernel or guest can't turn them back on by doing MMIO writes to ACK# Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 2 ++ include/xive.h | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 9148c5f6..d6628a09 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1623,6 +1623,8 @@ static bool xive_config_init(struct xive *x) #endif val |= PC_TCTXT_CHIPID_OVERRIDE; val |= PC_TCTXT_CFG_TARGET_EN; + /* Disable pressure relief as we hijack the field in the VPs */ + val &= ~PC_TCTXT_CFG_STORE_ACK; val = SETFIELD(PC_TCTXT_CHIPID, val, x->block_id); xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); diff --git a/include/xive.h b/include/xive.h index 860373c9..70f6499f 100644 --- a/include/xive.h +++ b/include/xive.h @@ -75,6 +75,7 @@ #define PC_TCTXT_CFG 0x400 #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) +#define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) From patchwork Sun Sep 10 07:33:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812052 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjWW2sKFz9sQl for ; Sun, 10 Sep 2017 17:35:03 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjWW1LWhzDrKk for ; Sun, 10 Sep 2017 17:35:03 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVH26jlzDrcr for ; Sun, 10 Sep 2017 17:33:58 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVak032370; Sun, 10 Sep 2017 02:33:38 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:20 +1000 Message-Id: <20170910073330.25824-4-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 04/14] xive: Add debug code to check initial cache updates X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This adds debug code to check that the initial updates of in-memory VPs and EQs via the cache watch and cache scrub facilities has worked properly. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index d6628a09..71280002 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -43,9 +43,11 @@ #ifdef DEBUG #define XIVE_DEBUG_DUPLICATES #define XIVE_PERCPU_LOG +#define XIVE_DEBUG_INIT_CACHE_UPDATES #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG +#undef XIVE_DEBUG_INIT_CACHE_UPDATES #endif /* @@ -2892,12 +2894,57 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + if (1) { + struct xive_eq *eq_p = xive_get_eq(x_eq, + xs->eq_idx + + XIVE_EMULATION_PRIO); + struct xive_eq eq2; + + assert(eq_p); + eq2 = *eq_p; + if (memcmp(&eq, &eq2, sizeof(eq)) != 0) { + xive_err(x_eq, "EQ update mismatch idx %d\n", + xs->eq_idx); + xive_err(x_eq, "want: %08x %08x %08x %08x\n", + eq.w0, eq.w1, eq.w2, eq.w3); + xive_err(x_eq, " %08x %08x %08x %08x\n", + eq.w4, eq.w5, eq.w6, eq.w7); + xive_err(x_eq, "got : %08x %08x %08x %08x\n", + eq2.w0, eq2.w1, eq2.w2, eq2.w3); + xive_err(x_eq, " %08x %08x %08x %08x\n", + eq2.w4, eq2.w5, eq2.w6, eq2.w7); + } + } +#endif /* Initialize/enable the VP */ xive_init_default_vp(&vp, xs->eq_blk, xs->eq_idx); /* Use the cache watch to write it out */ xive_vpc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, 0, 8, &vp, false, true); + + /* Debug code */ +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + if (1) { + struct xive_vp *vp_p = xive_get_vp(x_vp, xs->vp_idx); + struct xive_vp vp2; + + assert(vp_p); + vp2 = *vp_p; + if (memcmp(&vp, &vp2, sizeof(vp)) != 0) { + xive_err(x_vp, "VP update mismatch idx %d\n", xs->vp_idx); + xive_err(x_vp, "want: %08x %08x %08x %08x\n", + vp.w0, vp.w1, vp.w2, vp.w3); + xive_err(x_vp, " %08x %08x %08x %08x\n", + vp.w4, vp.w5, vp.w6, vp.w7); + xive_err(x_vp, "got : %08x %08x %08x %08x\n", + vp2.w0, vp2.w1, vp2.w2, vp2.w3); + xive_err(x_vp, " %08x %08x %08x %08x\n", + vp2.w4, vp2.w5, vp2.w6, vp2.w7); + } + } +#endif } static void xive_init_cpu_emulation(struct xive_cpu_state *xs, From patchwork Sun Sep 10 07:33:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjWM57kxz9sQl for ; Sun, 10 Sep 2017 17:34:55 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjWM3DDtzDrnd for ; Sun, 10 Sep 2017 17:34:55 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVG4z4bzDrch for ; Sun, 10 Sep 2017 17:33:58 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVal032370; Sun, 10 Sep 2017 02:33:40 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:21 +1000 Message-Id: <20170910073330.25824-5-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 05/14] xive: Make assertion in xive_eq_for_target() more informative X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" If this fails, print a bit more info about it. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index 71280002..4f08e655 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2226,7 +2226,11 @@ static inline bool xive_eq_for_target(uint32_t target, uint8_t prio, eq_idx = vp->w1 & 0x0fffffff; /* Currently the EQ block and VP block should be the same */ - assert(eq_blk == vp_blk); + if (eq_blk != vp_blk) { + xive_err(x, "eq_blk != vp_blk (%d vs. %d) for target 0x%08x/%d\n", + eq_blk, vp_blk, target, prio); + assert(false); + } if (out_eq_blk) *out_eq_blk = eq_blk; From patchwork Sun Sep 10 07:33:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812054 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjWw59CKz9sQl for ; Sun, 10 Sep 2017 17:35:24 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjWw3v4HzDrpj for ; Sun, 10 Sep 2017 17:35:24 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVK2XNWzDrcr for ; Sun, 10 Sep 2017 17:34:01 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVam032370; Sun, 10 Sep 2017 02:33:42 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:22 +1000 Message-Id: <20170910073330.25824-6-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 06/14] xive: Add exerciser for cache watch/scrub facility in DEBUG builds X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This runs 1000 iterations exercising the cache watch and scrub facilities on VPs and ENDs at boot. This exposes a HW bug with the scrub which will be worked around in a subsequent patch. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 141 ++++++++++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 96 insertions(+), 45 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 4f08e655..d8d51dee 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -44,10 +44,12 @@ #define XIVE_DEBUG_DUPLICATES #define XIVE_PERCPU_LOG #define XIVE_DEBUG_INIT_CACHE_UPDATES +#define XIVE_EXTRA_CHECK_INIT_CACHE #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG #undef XIVE_DEBUG_INIT_CACHE_UPDATES +#undef XIVE_EXTRA_CHECK_INIT_CACHE #endif /* @@ -2870,6 +2872,95 @@ void xive_cpu_callin(struct cpu_thread *cpu) in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS)); } +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES +static bool xive_check_eq_update(struct xive *x, uint32_t idx, struct xive_eq *eq) +{ + struct xive_eq *eq_p = xive_get_eq(x, idx); + struct xive_eq eq2; + + assert(eq_p); + eq2 = *eq_p; + if (memcmp(eq, &eq2, sizeof(eq)) != 0) { + xive_err(x, "EQ update mismatch idx %d\n", idx); + xive_err(x, "want: %08x %08x %08x %08x\n", + eq->w0, eq->w1, eq->w2, eq->w3); + xive_err(x, " %08x %08x %08x %08x\n", + eq->w4, eq->w5, eq->w6, eq->w7); + xive_err(x, "got : %08x %08x %08x %08x\n", + eq2.w0, eq2.w1, eq2.w2, eq2.w3); + xive_err(x, " %08x %08x %08x %08x\n", + eq2.w4, eq2.w5, eq2.w6, eq2.w7); + return false; + } + return true; +} + +static bool xive_check_vpc_update(struct xive *x, uint32_t idx, struct xive_vp *vp) +{ + struct xive_vp *vp_p = xive_get_vp(x, idx); + struct xive_vp vp2; + + assert(vp_p); + vp2 = *vp_p; + if (memcmp(vp, &vp2, sizeof(vp)) != 0) { + xive_err(x, "VP update mismatch idx %d\n", idx); + xive_err(x, "want: %08x %08x %08x %08x\n", + vp->w0, vp->w1, vp->w2, vp->w3); + xive_err(x, " %08x %08x %08x %08x\n", + vp->w4, vp->w5, vp->w6, vp->w7); + xive_err(x, "got : %08x %08x %08x %08x\n", + vp2.w0, vp2.w1, vp2.w2, vp2.w3); + xive_err(x, " %08x %08x %08x %08x\n", + vp2.w4, vp2.w5, vp2.w6, vp2.w7); + return false; + } + return true; +} +#else +static inline bool xive_check_eq_update(struct xive *x __unused, + uint32_t idx __unused, + struct xive_eq *eq __unused) +{ + return true; +} + +static inline bool xive_check_vpc_update(struct xive *x __unused, + uint32_t idx __unused, + struct xive_vp *vp __unused) +{ + return true; +} +#endif + +#ifdef XIVE_EXTRA_CHECK_INIT_CACHE +static void xive_special_cache_check(struct xive *x, uint32_t blk, uint32_t idx) +{ + struct xive_vp vp = {}; + uint32_t i; + + for (i = 0; i < 1000; i++) { + struct xive_vp *vp_m = xive_get_vp(x, idx); + + memset(vp_m, (~i) & 0xff, sizeof(*vp_m)); + sync(); + vp.w1 = (i << 16) | i; + xive_vpc_cache_update(x, blk, idx, + 0, 8, &vp, false, true); + if (!xive_check_vpc_update(x, idx, &vp)) { + xive_dbg(x, "Test failed at %d iterations\n", i); + return; + } + } + xive_dbg(x, "1000 iterations test success at %d/0x%x\n", blk, idx); +} +#else +static inline void xive_special_cache_check(struct xive *x __unused, + uint32_t blk __unused, + uint32_t idx __unused) +{ +} +#endif + static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) { struct xive_eq eq; @@ -2897,58 +2988,18 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) xive_eqc_cache_update(x_eq, xs->eq_blk, xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); + xive_check_eq_update(x_eq, xs->eq_idx + XIVE_EMULATION_PRIO, &eq); + + /* Extra testing of cache watch & scrub facilities */ + xive_special_cache_check(x_vp, xs->vp_blk, xs->vp_idx); -#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES - if (1) { - struct xive_eq *eq_p = xive_get_eq(x_eq, - xs->eq_idx + - XIVE_EMULATION_PRIO); - struct xive_eq eq2; - - assert(eq_p); - eq2 = *eq_p; - if (memcmp(&eq, &eq2, sizeof(eq)) != 0) { - xive_err(x_eq, "EQ update mismatch idx %d\n", - xs->eq_idx); - xive_err(x_eq, "want: %08x %08x %08x %08x\n", - eq.w0, eq.w1, eq.w2, eq.w3); - xive_err(x_eq, " %08x %08x %08x %08x\n", - eq.w4, eq.w5, eq.w6, eq.w7); - xive_err(x_eq, "got : %08x %08x %08x %08x\n", - eq2.w0, eq2.w1, eq2.w2, eq2.w3); - xive_err(x_eq, " %08x %08x %08x %08x\n", - eq2.w4, eq2.w5, eq2.w6, eq2.w7); - } - } -#endif /* Initialize/enable the VP */ xive_init_default_vp(&vp, xs->eq_blk, xs->eq_idx); /* Use the cache watch to write it out */ xive_vpc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, 0, 8, &vp, false, true); - - /* Debug code */ -#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES - if (1) { - struct xive_vp *vp_p = xive_get_vp(x_vp, xs->vp_idx); - struct xive_vp vp2; - - assert(vp_p); - vp2 = *vp_p; - if (memcmp(&vp, &vp2, sizeof(vp)) != 0) { - xive_err(x_vp, "VP update mismatch idx %d\n", xs->vp_idx); - xive_err(x_vp, "want: %08x %08x %08x %08x\n", - vp.w0, vp.w1, vp.w2, vp.w3); - xive_err(x_vp, " %08x %08x %08x %08x\n", - vp.w4, vp.w5, vp.w6, vp.w7); - xive_err(x_vp, "got : %08x %08x %08x %08x\n", - vp2.w0, vp2.w1, vp2.w2, vp2.w3); - xive_err(x_vp, " %08x %08x %08x %08x\n", - vp2.w4, vp2.w5, vp2.w6, vp2.w7); - } - } -#endif + xive_check_vpc_update(x_vp, xs->vp_idx, &vp); } static void xive_init_cpu_emulation(struct xive_cpu_state *xs, From patchwork Sun Sep 10 07:33:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812050 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjWC4Mh5z9sQl for ; Sun, 10 Sep 2017 17:34:47 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjWC3Vn9zDrnP for ; Sun, 10 Sep 2017 17:34:47 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVG59fjzDrcj for ; Sun, 10 Sep 2017 17:33:58 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVan032370; Sun, 10 Sep 2017 02:33:44 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:23 +1000 Message-Id: <20170910073330.25824-7-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 07/14] xive: Workaround HW issue with scrub facility X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Without this, we sometimes don't observe from a CPU the values written to the ENDs or NVTs via the cache watch. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index d8d51dee..98839219 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1232,6 +1232,12 @@ enum xive_cache_type { xive_cache_vpc, }; +static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, + uint64_t block, uint64_t idx, + uint32_t start_dword, uint32_t dword_count, + void *new_data, bool light_watch, + bool synchronous); + static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, uint64_t block, uint64_t idx, bool want_inval, bool want_disable) @@ -1239,6 +1245,17 @@ static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, uint64_t sreg, sregx, mreg, mregx; uint64_t mval, sval; + /* Workaround a HW bug in XIVE where the scrub completion + * isn't ordered by loads, thus the data might still be + * in a queue and may not have reached coherency. + * + * The workaround is two folds: We force the scrub to also + * invalidate, then after the scrub, we do a dummy cache + * watch which will make the HW read the data back, which + * should be ordered behind all the preceding stores. + */ + want_inval = true; + switch (ctype) { case xive_cache_ivc: sreg = VC_IVC_SCRUB_TRIG; @@ -1293,6 +1310,13 @@ static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, time_wait(100); } sync(); + + /* Workaround for HW bug described above (only applies to + * EQC and VPC + */ + if (ctype == xive_cache_eqc || ctype == xive_cache_vpc) + __xive_cache_watch(x, ctype, block, idx, 0, 0, NULL, + true, false); return 0; } @@ -1304,7 +1328,6 @@ static int64_t xive_ivc_scrub(struct xive *x, uint64_t block, uint64_t idx) static int64_t xive_vpc_scrub_clean(struct xive *x, uint64_t block, uint64_t idx) { - /* IVC has no "want_inval" bit, it always invalidates */ return __xive_cache_scrub(x, xive_cache_vpc, block, idx, true, false); } @@ -1348,6 +1371,14 @@ static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, /* Load data0 register to populate the watch */ dval0 = __xive_regr(x, dreg0, dreg0x, NULL); + /* If new_data is NULL, this is a dummy watch used as a + * workaround for a HW bug + */ + if (!new_data) { + __xive_regw(x, dreg0, dreg0x, dval0, NULL); + return 0; + } + /* Write the words into the watch facility. We write in reverse * order in case word 0 is part of it as it must be the last * one written. From patchwork Sun Sep 10 07:33:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812049 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjW81rY0z9sQl for ; Sun, 10 Sep 2017 17:34:44 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjW80fBFzDrn8 for ; Sun, 10 Sep 2017 17:34:44 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVF0MNWzDrch for ; Sun, 10 Sep 2017 17:33:56 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVao032370; Sun, 10 Sep 2017 02:33:45 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:24 +1000 Message-Id: <20170910073330.25824-8-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 08/14] xive: Use symbolic constant X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Cosmetic fix. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index 98839219..1d306b93 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2893,7 +2893,7 @@ void xive_cpu_callin(struct cpu_thread *cpu) in_be32(xs->tm_ring1 + TM_SPC_PULL_POOL_CTX); /* Clear VT and LSI bit */ - out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + 8, 0); + out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2, 0); /* Set VT to 1 */ out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2, 0x80); From patchwork Sun Sep 10 07:33:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812053 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjWs1zHpz9sQl for ; Sun, 10 Sep 2017 17:35:21 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjWs18cCzDrpJ for ; Sun, 10 Sep 2017 17:35:21 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVH6rHRzDrch for ; Sun, 10 Sep 2017 17:33:59 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVap032370; Sun, 10 Sep 2017 02:33:47 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:25 +1000 Message-Id: <20170910073330.25824-9-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 09/14] xive: Fix locking around cache scrub & watch X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Thankfully the missing locking only affects debug code and init code that doesn't run concurrently. Also adds a DEBUG option that checks the lock is properly held. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 1d306b93..c2360550 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -45,11 +45,13 @@ #define XIVE_PERCPU_LOG #define XIVE_DEBUG_INIT_CACHE_UPDATES #define XIVE_EXTRA_CHECK_INIT_CACHE +#define XIVE_CHECK_LOCKS #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG #undef XIVE_DEBUG_INIT_CACHE_UPDATES #undef XIVE_EXTRA_CHECK_INIT_CACHE +#undef XIVE_CHECK_LOCKS #endif /* @@ -1245,6 +1247,10 @@ static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, uint64_t sreg, sregx, mreg, mregx; uint64_t mval, sval; +#ifdef XIVE_CHECK_LOCKS + assert(lock_held_by_me(&x->lock)); +#endif + /* Workaround a HW bug in XIVE where the scrub completion * isn't ordered by loads, thus the data might still be * in a queue and may not have reached coherency. @@ -1341,6 +1347,9 @@ static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, uint64_t dval0, sval, status; int64_t i; +#ifdef XIVE_CHECK_LOCKS + assert(lock_held_by_me(&x->lock)); +#endif switch (ctype) { case xive_cache_eqc: sreg = VC_EQC_CWATCH_SPEC; @@ -3016,6 +3025,7 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) xs->eq_page, XIVE_EMULATION_PRIO); /* Use the cache watch to write it out */ + lock(&x_eq->lock); xive_eqc_cache_update(x_eq, xs->eq_blk, xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); @@ -3023,14 +3033,17 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) /* Extra testing of cache watch & scrub facilities */ xive_special_cache_check(x_vp, xs->vp_blk, xs->vp_idx); + unlock(&x_eq->lock); /* Initialize/enable the VP */ xive_init_default_vp(&vp, xs->eq_blk, xs->eq_idx); /* Use the cache watch to write it out */ + lock(&x_vp->lock); xive_vpc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, 0, 8, &vp, false, true); xive_check_vpc_update(x_vp, xs->vp_idx, &vp); + unlock(&x_vp->lock); } static void xive_init_cpu_emulation(struct xive_cpu_state *xs, @@ -3075,8 +3088,10 @@ static void xive_init_cpu_exploitation(struct xive_cpu_state *xs) xive_init_default_vp(&vp, xs->eq_blk, xs->eq_idx); /* Use the cache watch to write it out */ + lock(&x_vp->lock); xive_vpc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, 0, 8, &vp, false, true); + unlock(&x_vp->lock); /* Clenaup remaining state */ xs->cppr = 0; @@ -3263,9 +3278,11 @@ static uint32_t xive_read_eq(struct xive_cpu_state *xs, bool just_peek) xs->eqbuf[(xs->eqptr + 2) & xs->eqmsk], xs->eqbuf[(xs->eqptr + 3) & xs->eqmsk], xs->eqgen, xs->eqptr, just_peek); + lock(&xs->xive->lock); __xive_cache_scrub(xs->xive, xive_cache_eqc, xs->eq_blk, xs->eq_idx + XIVE_EMULATION_PRIO, false, false); + unlock(&xs->xive->lock); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); prerror("EQ @%p W0=%08x W1=%08x qbuf @%p\n", eq, eq->w0, eq->w1, xs->eqbuf); @@ -3503,9 +3520,11 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) #ifdef XIVE_PERCPU_LOG { struct xive_eq *eq; + lock(&xs->xive->lock); __xive_cache_scrub(xs->xive, xive_cache_eqc, xs->eq_blk, xs->eq_idx + XIVE_EMULATION_PRIO, false, false); + unlock(&xs->xive->lock); eq = xive_get_eq(xs->xive, xs->eq_idx + XIVE_EMULATION_PRIO); log_add(xs, LOG_TYPE_EQD, 2, eq->w0, eq->w1); } From patchwork Sun Sep 10 07:33:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812056 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjXJ4Fqxz9sQl for ; Sun, 10 Sep 2017 17:35:44 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjXJ3Rw1zDrWF for ; Sun, 10 Sep 2017 17:35:44 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVT6jmRzDrd8 for ; Sun, 10 Sep 2017 17:34:09 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVaq032370; Sun, 10 Sep 2017 02:33:49 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:26 +1000 Message-Id: <20170910073330.25824-10-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 10/14] xive: Increase the interrupt "gap" on debug builds X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We normally allocate IPIs from 0x10. Make that 0x1000 on debug builds to limit the chances of overlapping with Linux interrupt numbers which makes debugging code that confuses them easier. Also add a warning in emulation if we get an interrupt in the queue whose number is below the gap. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index c2360550..0d3b24fd 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -46,12 +46,14 @@ #define XIVE_DEBUG_INIT_CACHE_UPDATES #define XIVE_EXTRA_CHECK_INIT_CACHE #define XIVE_CHECK_LOCKS +#define XIVE_INT_SAFETY_GAP 0x1000 #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG #undef XIVE_DEBUG_INIT_CACHE_UPDATES #undef XIVE_EXTRA_CHECK_INIT_CACHE #undef XIVE_CHECK_LOCKS +#define XIVE_INT_SAFETY_GAP 0x10 #endif /* @@ -2756,8 +2758,8 @@ static struct xive *init_one_xive(struct dt_node *np) /* Make sure we never hand out "2" as it's reserved for XICS emulation * IPI returns. Generally start handing out at 0x10 */ - if (x->int_ipi_top < 0x10) - x->int_ipi_top = 0x10; + if (x->int_ipi_top < XIVE_INT_SAFETY_GAP) + x->int_ipi_top = XIVE_INT_SAFETY_GAP; /* Allocate a few bitmaps */ x->eq_map = zalloc(BITMAP_BYTES(MAX_EQ_COUNT >> 3)); @@ -3540,6 +3542,9 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) /* XXX Use "p" to select queue */ val = xive_read_eq(xs, just_poll); + if (val && val < XIVE_INT_SAFETY_GAP) + xive_cpu_err(c, "Bogus interrupt 0x%x received !\n", val); + /* Convert to magic IPI if needed */ if (val == xs->ipi_irq) val = 2; From patchwork Sun Sep 10 07:33:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812057 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjXs25MQz9s8J for ; Sun, 10 Sep 2017 17:36:13 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjXs0pLmzDrnY for ; Sun, 10 Sep 2017 17:36:13 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVY1lbrzDrd3 for ; Sun, 10 Sep 2017 17:34:12 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVar032370; Sun, 10 Sep 2017 02:33:52 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:27 +1000 Message-Id: <20170910073330.25824-11-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 11/14] xive: Add debug option for detecting misrouted IPI in emulation X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This is high overhead so we don't enable it by default even in debug builds, it's also a bit messy, but it allowed me to detect and debug a locking issue earlier so it can be useful. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 137 +++++++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 122 insertions(+), 15 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 0d3b24fd..ea81b2b3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -45,6 +45,7 @@ #define XIVE_PERCPU_LOG #define XIVE_DEBUG_INIT_CACHE_UPDATES #define XIVE_EXTRA_CHECK_INIT_CACHE +#undef XIVE_CHECK_MISROUTED_IPI #define XIVE_CHECK_LOCKS #define XIVE_INT_SAFETY_GAP 0x1000 #else @@ -52,6 +53,7 @@ #undef XIVE_PERCPU_LOG #undef XIVE_DEBUG_INIT_CACHE_UPDATES #undef XIVE_EXTRA_CHECK_INIT_CACHE +#undef XIVE_CHECK_MISROUTED_IPI #undef XIVE_CHECK_LOCKS #define XIVE_INT_SAFETY_GAP 0x10 #endif @@ -3444,6 +3446,103 @@ static int64_t opal_xive_eoi(uint32_t xirr) return opal_xive_check_pending(xs, cppr) ? 1 : 0; } +#ifdef XIVE_CHECK_MISROUTED_IPI +static void xive_dump_eq(uint32_t eq_blk, uint32_t eq_idx) +{ + struct cpu_thread *me = this_cpu(); + struct xive *x; + struct xive_eq *eq; + + x = xive_from_vc_blk(eq_blk); + if (!x) + return; + eq = xive_get_eq(x, eq_idx); + if (!eq) + return; + xive_cpu_err(me, "EQ: %08x %08x %08x %08x (@%p)\n", + eq->w0, eq->w1, eq->w2, eq->w3, eq); + xive_cpu_err(me, " %08x %08x %08x %08x\n", + eq->w4, eq->w5, eq->w6, eq->w7); +} +static int64_t __opal_xive_dump_emu(struct xive_cpu_state *xs, uint32_t pir); +static void checkstop(void) +{ + xscom_writeme(0x05011c02, PPC_BIT(0)); + for (;;) ; +} + +static bool check_misrouted_ipi(struct cpu_thread *me, uint32_t irq) +{ + struct cpu_thread *c; + + for_each_present_cpu(c) { + struct xive_cpu_state *xs = c->xstate; + struct xive_ive *ive; + uint32_t ipi_target, i, eq_blk, eq_idx; + struct proc_chip *chip; + struct xive *x; + + if (!xs) + continue; + if (irq == xs->ipi_irq) { + xive_cpu_err(me, "misrouted IPI 0x%x, should" + " be aimed at CPU 0x%x\n", + irq, c->pir); + xive_cpu_err(me, " my eq_page=%p eqbuff=%p eq=0x%x/%x\n", + me->xstate->eq_page, me->xstate->eqbuf, + me->xstate->eq_blk, me->xstate->eq_idx + XIVE_EMULATION_PRIO); + xive_cpu_err(me, "tgt eq_page=%p eqbuff=%p eq=0x%x/%x\n", + c->xstate->eq_page, c->xstate->eqbuf, + c->xstate->eq_blk, c->xstate->eq_idx + XIVE_EMULATION_PRIO); + __opal_xive_dump_emu(me->xstate, me->pir); + __opal_xive_dump_emu(c->xstate, c->pir); + checkstop(); + if (xive_get_irq_targetting(xs->ipi_irq, &ipi_target, NULL, NULL)) + xive_cpu_err(me, "target=%08x\n", ipi_target); + else + xive_cpu_err(me, "target=???\n"); + /* Find XIVE on which the IVE resides */ + x = xive_from_isn(irq); + if (!x) { + xive_cpu_err(me, "no xive attached\n"); + return true; + } + ive = xive_get_ive(x, irq); + if (!ive) { + xive_cpu_err(me, "no ive attached\n"); + return true; + } + xive_cpu_err(me, "ive=%016llx\n", ive->w); + for_each_chip(chip) { + x = chip->xive; + if (!x) + continue; + ive = x->ivt_base; + for (i = 0; i < MAX_INT_ENTRIES; i++) { + if ((ive[i].w & IVE_EQ_DATA) == irq) { + eq_blk = GETFIELD(IVE_EQ_BLOCK, ive[i].w); + eq_idx = GETFIELD(IVE_EQ_INDEX, ive[i].w); + xive_cpu_err(me, "Found source: 0x%x ive=%016llx\n" + " eq 0x%x/%x", + BLKIDX_TO_GIRQ(x->block_id, i), + ive[i].w, eq_blk, eq_idx); + xive_dump_eq(eq_blk, eq_idx); + } + } + } + return true; + } + } + return false; +} +#else +static inline bool check_misrouted_ipi(struct cpu_thread *c __unused, + uint32_t irq __unused) +{ + return false; +} +#endif + static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) { struct cpu_thread *c = this_cpu(); @@ -3548,6 +3647,8 @@ static int64_t opal_xive_get_xirr(uint32_t *out_xirr, bool just_poll) /* Convert to magic IPI if needed */ if (val == xs->ipi_irq) val = 2; + if (check_misrouted_ipi(c, val)) + val = 2; *out_xirr = (old_cppr << 24) | val; @@ -4668,26 +4769,14 @@ static int64_t opal_xive_dump_vp(uint32_t vp_id) return OPAL_SUCCESS; } -static int64_t opal_xive_dump_emu(uint32_t pir) +static int64_t __opal_xive_dump_emu(struct xive_cpu_state *xs, uint32_t pir) { - struct cpu_thread *c = find_cpu_by_pir(pir); - struct xive_cpu_state *xs; struct xive_eq *eq; uint32_t ipi_target; uint8_t *mm, pq; - if (!c) - return OPAL_PARAMETER; - prlog(PR_INFO, "CPU[%04x]: XIVE emulation state\n", pir); - xs = c->xstate; - if (!xs) { - prlog(PR_INFO, " \n"); - return OPAL_SUCCESS; - } - lock(&xs->lock); - prlog(PR_INFO, "CPU[%04x]: cppr=%02x mfrr=%02x pend=%02x" " prev_cppr=%02x total_irqs=%llx\n", pir, xs->cppr, xs->mfrr, xs->pending, xs->prev_cppr, xs->total_irqs); @@ -4720,11 +4809,29 @@ static int64_t opal_xive_dump_emu(uint32_t pir) prlog(PR_INFO, "CPU[%04x]: EQ @%p W0=%08x W1=%08x qbuf @%p\n", pir, eq, eq->w0, eq->w1, xs->eqbuf); - log_print(xs); + return OPAL_SUCCESS; +} + +static int64_t opal_xive_dump_emu(uint32_t pir) +{ + struct cpu_thread *c = find_cpu_by_pir(pir); + struct xive_cpu_state *xs; + int64_t rc; + if (!c) + return OPAL_PARAMETER; + + xs = c->xstate; + if (!xs) { + prlog(PR_INFO, " \n"); + return OPAL_SUCCESS; + } + lock(&xs->lock); + rc = __opal_xive_dump_emu(xs, pir); + log_print(xs); unlock(&xs->lock); - return OPAL_SUCCESS; + return rc; } static int64_t opal_xive_sync_irq_src(uint32_t girq) From patchwork Sun Sep 10 07:33:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812058 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjY06JMsz9s8J for ; Sun, 10 Sep 2017 17:36:20 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjY05HFgzDrWS for ; Sun, 10 Sep 2017 17:36:20 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVZ4t7wzDrd1 for ; Sun, 10 Sep 2017 17:34:14 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVas032370; Sun, 10 Sep 2017 02:33:55 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:28 +1000 Message-Id: <20170910073330.25824-12-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 12/14] xive: Fix initialization & cleanup of HW thread contexts X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Instead of trying to "pull" everything and clear VT (which didn't work and caused some FIRs to be set), instead just clear and then set the PTER thread enable bit. This has the side effect of completely resetting the corresponding thread context. This fixes the spurrious XIVE FIRs reported by PRD and fircheck Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 74 ++++++++++++++++++++++++++++++++------------------------------- 1 file changed, 38 insertions(+), 36 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index ea81b2b3..d8b452e2 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2872,48 +2872,48 @@ static void xive_ipi_trigger(struct xive *x, uint32_t idx) } -void xive_cpu_callin(struct cpu_thread *cpu) +static void xive_reset_enable_thread(struct cpu_thread *c) { - struct xive_cpu_state *xs = cpu->xstate; - struct proc_chip *chip = get_chip(cpu->chip_id); + struct proc_chip *chip = get_chip(c->chip_id); struct xive *x = chip->xive; uint32_t fc, bit; - if (!xs) - return; - - /* First enable us in PTER. We currently assume that the - * PIR bits can be directly used to index in PTER. That might - * need to be verified - */ - /* Get fused core number */ - fc = (cpu->pir >> 3) & 0xf; + fc = (c->pir >> 3) & 0xf; + /* Get bit in register */ - bit = cpu->pir & 0x3f; + bit = c->pir & 0x3f; + /* Get which register to access */ - if (fc < 8) + if (fc < 8) { + xive_regw(x, PC_THREAD_EN_REG0_CLR, PPC_BIT(bit)); xive_regw(x, PC_THREAD_EN_REG0_SET, PPC_BIT(bit)); - else + } else { + xive_regw(x, PC_THREAD_EN_REG1_CLR, PPC_BIT(bit)); xive_regw(x, PC_THREAD_EN_REG1_SET, PPC_BIT(bit)); + } +} - /* Set CPPR to 0 */ - out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_CPPR, 0); +void xive_cpu_callin(struct cpu_thread *cpu) +{ + struct xive_cpu_state *xs = cpu->xstate; + uint8_t old_w2, w2; - /* Pull everything */ - in_be32(xs->tm_ring1 + TM_SPC_PULL_USR_CTX); - in_be32(xs->tm_ring1 + TM_SPC_PULL_OS_CTX); - in_be32(xs->tm_ring1 + TM_SPC_PULL_POOL_CTX); + if (!xs) + return; - /* Clear VT and LSI bit */ - out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2, 0); + /* Reset the HW thread context and enable it */ + xive_reset_enable_thread(cpu); /* Set VT to 1 */ + old_w2 = in_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2); out_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2, 0x80); + w2 = in_8(xs->tm_ring1 + TM_QW3_HV_PHYS + TM_WORD2); - xive_cpu_dbg(cpu, "Initialized TMA (VP: %x/%x W01=%016llx)\n", + xive_cpu_dbg(cpu, "Initialized TIMA VP=%x/%x W01=%016llx W2=%02x->%02x\n", xs->vp_blk, xs->vp_idx, - in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS)); + in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS), + old_w2, w2); } #ifdef XIVE_DEBUG_INIT_CACHE_UPDATES @@ -4141,11 +4141,15 @@ static int64_t opal_xive_set_vp_info(uint64_t vp_id, return OPAL_SUCCESS; } -static void xive_cleanup_cpu_tma(struct cpu_thread *c) +static void xive_cleanup_cpu_tima(struct cpu_thread *c) { struct xive_cpu_state *xs = c->xstate; struct xive *x = xs->xive; void *ind_tm_base = x->ic_base + (4 << x->ic_shift); + uint8_t old_w2, w2; + + /* Reset the HW context */ + xive_reset_enable_thread(c); /* Setup indirect access to the corresponding thread */ xive_regw(x, PC_TCTXT_INDIR0, @@ -4157,18 +4161,16 @@ static void xive_cleanup_cpu_tma(struct cpu_thread *c) */ xive_regr(x, PC_TCTXT_INDIR0); - /* Pull user context, OS context and Pool context if any */ - in_be32(ind_tm_base + TM_SPC_PULL_USR_CTX); - in_be32(ind_tm_base + TM_SPC_PULL_OS_CTX); - in_be32(ind_tm_base + TM_SPC_PULL_POOL_CTX); - - /* Set HV CPPR to 0 */ - out_8(ind_tm_base + TM_QW3_HV_PHYS + TM_CPPR, 0); + /* Set VT to 1 */ + old_w2 = in_8(ind_tm_base + TM_QW3_HV_PHYS + TM_WORD2); + out_8(ind_tm_base + TM_QW3_HV_PHYS + TM_WORD2, 0x80); + w2 = in_8(ind_tm_base + TM_QW3_HV_PHYS + TM_WORD2); /* Dump HV state */ - xive_cpu_dbg(c, "[reset] VP %x/%x W01 state: %016llx\n", + xive_cpu_dbg(c, "[reset] VP TIMA VP=%x/%x W01=%016llx W2=%02x->%02x\n", xs->vp_blk, xs->vp_idx, - in_be64(ind_tm_base + TM_QW3_HV_PHYS)); + in_be64(ind_tm_base + TM_QW3_HV_PHYS), + old_w2, w2); /* Reset indirect access */ xive_regw(x, PC_TCTXT_INDIR0, 0); @@ -4315,7 +4317,7 @@ static void xive_reset_one(struct xive *x) continue; if (!c->xstate) continue; - xive_cleanup_cpu_tma(c); + xive_cleanup_cpu_tima(c); } /* Reset all user-allocated VPs. This is inefficient, we should From patchwork Sun Sep 10 07:33:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812059 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjYC4d0Zz9s8J for ; Sun, 10 Sep 2017 17:36:31 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjYC3WRczDrch for ; Sun, 10 Sep 2017 17:36:31 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVc1vp8zDrd6 for ; Sun, 10 Sep 2017 17:34:15 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVat032370; Sun, 10 Sep 2017 02:33:57 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:29 +1000 Message-Id: <20170910073330.25824-13-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 13/14] foo misrouted X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" --- hw/xive.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index d8b452e2..07363578 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3465,11 +3465,6 @@ static void xive_dump_eq(uint32_t eq_blk, uint32_t eq_idx) eq->w4, eq->w5, eq->w6, eq->w7); } static int64_t __opal_xive_dump_emu(struct xive_cpu_state *xs, uint32_t pir); -static void checkstop(void) -{ - xscom_writeme(0x05011c02, PPC_BIT(0)); - for (;;) ; -} static bool check_misrouted_ipi(struct cpu_thread *me, uint32_t irq) { @@ -3496,7 +3491,6 @@ static bool check_misrouted_ipi(struct cpu_thread *me, uint32_t irq) c->xstate->eq_blk, c->xstate->eq_idx + XIVE_EMULATION_PRIO); __opal_xive_dump_emu(me->xstate, me->pir); __opal_xive_dump_emu(c->xstate, c->pir); - checkstop(); if (xive_get_irq_targetting(xs->ipi_irq, &ipi_target, NULL, NULL)) xive_cpu_err(me, "target=%08x\n", ipi_target); else From patchwork Sun Sep 10 07:33:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 812060 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xqjYY5NzFz9sRY for ; Sun, 10 Sep 2017 17:36:49 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xqjYX4X7FzDrmw for ; Sun, 10 Sep 2017 17:36:48 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xqjVf6HyjzDrcv for ; Sun, 10 Sep 2017 17:34:18 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8A7XVau032370; Sun, 10 Sep 2017 02:33:59 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sun, 10 Sep 2017 17:33:30 +1000 Message-Id: <20170910073330.25824-14-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170910073330.25824-1-benh@kernel.crashing.org> References: <20170910073330.25824-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH v2 14/14] xive: Make opal_xive_allocate_irq() properly try all chips X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" When requested via OPAL_XIVE_ANY_CHIP, we need to try all chips. We first try the current one (on which the caller sits) and if that fails, we iterate all chips until the allocation succeeds. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 54 +++++++++++++++++++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 17 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 07363578..21dd3d95 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -4592,27 +4592,11 @@ static int64_t opal_xive_alloc_vp_block(uint32_t alloc_order) return rc; } -static int64_t opal_xive_allocate_irq(uint32_t chip_id) +static int64_t xive_try_allocate_irq(struct xive *x) { - struct proc_chip *chip; int idx, base_idx, max_count, girq; struct xive_ive *ive; - struct xive *x; - - if (xive_mode != XIVE_MODE_EXPL) - return OPAL_WRONG_STATE; - /* XXX Make this try multiple chips ... */ - if (chip_id == OPAL_XIVE_ANY_CHIP) - chip_id = this_cpu()->chip_id; - - chip = get_chip(chip_id); - if (!chip) - return OPAL_PARAMETER; - if (!chip->xive) - return OPAL_PARAMETER; - - x = chip->xive; lock(&x->lock); base_idx = x->int_ipi_top - x->int_base; @@ -4642,6 +4626,42 @@ static int64_t opal_xive_allocate_irq(uint32_t chip_id) return girq; } +static int64_t opal_xive_allocate_irq(uint32_t chip_id) +{ + struct proc_chip *chip; + bool try_all = false; + int64_t rc; + + if (xive_mode != XIVE_MODE_EXPL) + return OPAL_WRONG_STATE; + + if (chip_id == OPAL_XIVE_ANY_CHIP) { + try_all = true; + chip_id = this_cpu()->chip_id; + } + chip = get_chip(chip_id); + if (!chip) + return OPAL_PARAMETER; + + /* Try initial target chip */ + if (!chip->xive) + rc = OPAL_PARAMETER; + else + rc = xive_try_allocate_irq(chip->xive); + if (rc >= 0 || !try_all) + return rc; + + /* Failed and we try all... do so */ + for_each_chip(chip) { + if (!chip->xive) + continue; + rc = xive_try_allocate_irq(chip->xive); + if (rc >= 0) + break; + } + return rc; +} + static int64_t opal_xive_free_irq(uint32_t girq) { struct irq_source *is = irq_find_source(girq);