From patchwork Wed Mar 31 14:17:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Liebler X-Patchwork-Id: 1460557 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=libc-alpha-bounces@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.a=rsa-sha256 header.s=default header.b=s24JWxX+; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F9T0g5ZY7z9sVq for ; Thu, 1 Apr 2021 01:17:23 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A1EBA385780C; Wed, 31 Mar 2021 14:17:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A1EBA385780C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1617200240; bh=QOeKDGZWypqm+Rkw5ihJ6TM4G7tNOda9/r0V3pyH5to=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=s24JWxX+YgAMXZ3912AlUiGcQAM0cDTUG17qh2lkkxSu6GLRpa8fZBUaQkS4rED9O Lb/18ezsOpKU3BmNSp5pqXmzp2qvyD7fVN3F0kkciKXTWl6O6iteMQy2TjurG34Kq2 PWjWqpiq5j8K2OgnLyX4r2PlHV+jVIlXGM6f21wQ= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 7C98F385802E for ; Wed, 31 Mar 2021 14:17:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 7C98F385802E Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 12VE4flI037302; Wed, 31 Mar 2021 10:17:14 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0b-001b2d01.pphosted.com with ESMTP id 37mr9ywkbf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Mar 2021 10:17:13 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.43/8.16.0.43) with SMTP id 12VECg1P019752; Wed, 31 Mar 2021 14:17:11 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma03ams.nl.ibm.com with ESMTP id 37mngr082p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Mar 2021 14:17:11 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 12VEH8sa44040636 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 31 Mar 2021 14:17:08 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 50054A4067; Wed, 31 Mar 2021 14:17:08 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2169BA4062; Wed, 31 Mar 2021 14:17:08 +0000 (GMT) Received: from t35lp56.lnxne.boe (unknown [9.152.108.100]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Wed, 31 Mar 2021 14:17:08 +0000 (GMT) To: libc-alpha@sourceware.org Subject: [PATCH v2] S390: Allow "v" constraint for long double math_opt_barrier and math_force_eval with GCC 11. Date: Wed, 31 Mar 2021 16:17:01 +0200 Message-Id: <20210331141701.1339437-1-stli@linux.ibm.com> X-Mailer: git-send-email 2.29.2 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 5DvIxphMntqrXHIjKKqE7frvXunFxjek X-Proofpoint-ORIG-GUID: 5DvIxphMntqrXHIjKKqE7frvXunFxjek X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-31_03:2021-03-31, 2021-03-31 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 mlxscore=0 priorityscore=1501 adultscore=0 spamscore=0 impostorscore=0 mlxlogscore=910 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2103300000 definitions=main-2103310103 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Stefan Liebler via Libc-alpha From: Stefan Liebler Reply-To: Stefan Liebler Cc: Stefan Liebler , fw@deneb.enyo.de Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" Starting with GCC 11, long double values can also be processed in vector registers if build with -march >= z14. Then GCC defines the __LONG_DOUBLE_VX__ macro. FYI: GCC commit "IBM Z: Introduce __LONG_DOUBLE_VX__ macro" https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=f47df2af313d2ce7f9149149010a142c2237beda --- sysdeps/s390/fpu/math-barriers.h | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/sysdeps/s390/fpu/math-barriers.h b/sysdeps/s390/fpu/math-barriers.h index 68a3e55098..13fd30017f 100644 --- a/sysdeps/s390/fpu/math-barriers.h +++ b/sysdeps/s390/fpu/math-barriers.h @@ -21,13 +21,26 @@ #ifdef HAVE_S390_VX_GCC_SUPPORT # define ASM_CONSTRAINT_VR "v" +# ifdef __LONG_DOUBLE_VX__ +/* Starting with gcc 11, long double values can also be processed in vector + registers if build with -march >= z14. Then GCC defines the + __LONG_DOUBLE_VX__ macro. */ +# define ASM_LONG_DOUBLE_IN_VR 1 +# else +# define ASM_LONG_DOUBLE_IN_VR 0 +# endif #else # define ASM_CONSTRAINT_VR +# define ASM_LONG_DOUBLE_IN_VR 0 #endif #define math_opt_barrier(x) \ ({ __typeof (x) __x = (x); \ - if (__builtin_types_compatible_p (__typeof (x), _Float128)) \ + if (! ASM_LONG_DOUBLE_IN_VR \ + && (__builtin_types_compatible_p (__typeof (x), _Float128) \ + || __builtin_types_compatible_p (__typeof (x), long double) \ + ) \ + ) \ __asm__ ("# math_opt_barrier_f128 %0" : "+fm" (__x)); \ else \ __asm__ ("# math_opt_barrier %0" \ @@ -35,7 +48,11 @@ __x; }) #define math_force_eval(x) \ ({ __typeof (x) __x = (x); \ - if (__builtin_types_compatible_p (__typeof (x), _Float128)) \ + if (! ASM_LONG_DOUBLE_IN_VR \ + && (__builtin_types_compatible_p (__typeof (x), _Float128) \ + || __builtin_types_compatible_p (__typeof (x), long double) \ + ) \ + ) \ __asm__ __volatile__ ("# math_force_eval_f128 %0" \ : : "fm" (__x)); \ else \