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Tue, 30 Mar 2021 23:49:30 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 129396A047; Tue, 30 Mar 2021 23:49:29 +0000 (GMT) Received: from [9.160.64.5] (unknown [9.160.64.5]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 30 Mar 2021 23:49:29 +0000 (GMT) To: Segher Boessenkool Subject: [PATCH] rs6000: MMA test case ICEs using -O3 Message-ID: Date: Tue, 30 Mar 2021 18:49:29 -0500 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.9.0 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-GUID: yGtfUhmvXSBn_BjkRK7zXKqgidJPmROv X-Proofpoint-ORIG-GUID: yGtfUhmvXSBn_BjkRK7zXKqgidJPmROv X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369, 18.0.761 definitions=2021-03-30_13:2021-03-30, 2021-03-30 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 spamscore=0 clxscore=1015 adultscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2103300000 definitions=main-2103300171 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Peter Bergner via Gcc-patches From: Peter Bergner Reply-To: Peter Bergner Cc: GCC Patches Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" The mma_assemble_input_operand predicate does not accept reg+reg indexed addresses which can lead to ICEs. The problem is that the quad_address_p function only accepts reg+offset addresses that are valid for quad word accesses, but not reg+reg addresses which are also valid for quad word accesses when dealing with vector types. The solution used here is to call memory_operand, which uses rs6000_legitimate_address_p to ensure the address is valid. For reg+offset addresses, it uses quad_address_p like before, but for reg+reg addresses, it calls legitimate_indexed_address_p addresses which fixes this specific ICE. This passed bootstrap and regtesting on powerpc64le-linux with no regressions. I also compiled some non-trivial DGEMM and SGEMM test cases that use our MMA builtins and I don't see any generated code differences. Ok for trunk? The same bad test in mma_assemble_input_operand exists in GCC 10, but I have been unable to get it to ICE there with this test case. I assume we still want to fix it there too? If so, ok for GCC 10 after some trunk burn in? Peter gcc/ PR target/99842 * config/rs6000/predicates.md: gcc/testsuite/ PR target/99842 * g++.target/powerpc/pr99842.C: New. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 859af75dfbd..e48c6eee19e 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -1171,8 +1171,7 @@ (define_special_predicate "mma_assemble_input_operand" (match_test "(mode == V16QImode && (vsx_register_operand (op, mode) - || (MEM_P (op) - && quad_address_p (XEXP (op, 0), mode, false))))")) + || memory_operand (op, mode)))")) ;; Return 1 if this operand is valid for an MMA disassemble insn. (define_predicate "mma_disassemble_output_operand" diff --git a/gcc/testsuite/g++.target/powerpc/pr99842.C b/gcc/testsuite/g++.target/powerpc/pr99842.C new file mode 100644 index 00000000000..d84de3b4570 --- /dev/null +++ b/gcc/testsuite/g++.target/powerpc/pr99842.C @@ -0,0 +1,188 @@ +/* PR target/99842 */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-O3 -mdejagnu-cpu=power10 -w" } */ + +/* Verify we do not ICE on the following source. */ + +enum { a, b, c, d }; +template struct e; +template struct e { + typedef h f; +}; +template struct ac; +template struct ac : ac {}; +template struct l; +template class n; +template class o; +template class ag; +template class af; +template struct ad; +template struct an { + typedef n::ai, ac::aj> f; +}; +template struct am { typedef o f; }; +template ::ao, + typename = typename ac::av> +struct ak; +template struct ak { + typedef typename am::f f; +}; +template struct aq; +template struct aq { typedef ar at; }; +template ap bf(const typename ad::f *); +template ap aw(typename ad::f *ax) { return bf(ax); } +typedef __attribute__((altivec(vector__))) double au; +template <> struct ad { typedef double f; }; +template <> au bf(const double *ax) { return __builtin_vec_vsx_ld(0, ax); } +template struct az {}; +template class o : public l { +public: + typedef typename ac::ah ah; + template al &operator+=(const o &); +}; +template struct l {}; +template struct ac> { + typedef typename ba::ah ah; + enum { ai, aj }; +}; +template +class af + : public ak< + af, const n>, + n, bd>, + int, int>::f {}; +template struct be; +template void bi(bj, bg bm, g) { + typename an::f bk(bm); +} +template void bl(bj, bg bm, g bp) { + be::bn(a, bm, bp); +} +template struct bo; +class bs { +public: + bs(double *, int); + double &operator()(int, int) { return bq[br]; } + template bw bt(int i, int j) { + double &bu = operator()(i, j); + return aw(&bu); + } + double *bq; + int br; +}; +class ca : public bs { +public: + ca(double *by, int bz) : bs(by, bz) {} +}; +template class ce : public am::f { +protected: + template void cb(l) { + af, const n>, + n> + cc; + bl(0, cc, az()); + } + template void ch(long); + template void ch(l cf) { cb(cf); } +}; +template +struct ac> { + typedef cg ah; + typedef int av; +}; +template +class n : public ce> { +public: + template n(ab p) { n::template ch(p); } +}; +template struct ac> { + typedef ba ao; + typedef typename e::f ah; + typedef typename aq::av, typename ac::av, bc>::at av; +}; +template class cm; +template +class ag + : public cm::av, typename ac::av, int>::at> { +}; +template +class cm : public ak, n>>::f {}; +template +template +al &o::operator+=(const o &) { + af, const n>, + n> + co; + bi(0, co, int()); +} +enum { cp }; +template struct cq; +template struct cr { + enum { q }; + enum { ae = cq::at }; +}; +template <> struct cq { + enum { at = d }; +}; +struct t { + template static void bn(ba, bb, s) { + typedef typename bb::ah x; + x u; + bo::bn(0, 0, ca(0, 0), ca(&u, 1), 0, 0, 0); + } +}; +template ::ae> struct cu; +template +struct be, az> { + static void bn(cd, af bm, az) { + ag, const n> da; + cu::cv(c, da, bm); + } +}; +template struct cw { + template + static void + cv(bj, ag, const n>, + n bx) { + double alpha; + ag, const n> bh; + al::cx(c, bh, bx, alpha); + } +}; +template struct cu : cw> { + template static void cx(s, ba, bb bx, typename af::ah) { + ba cz; + t::bn(cz, bx, c); + } +}; +template +void db(__vector_quad *, __vector_pair &, dj); +template +void dc(ca alhs) { + typedef au dj; + typedef au dd; + ca bh(alhs); + enum { de }; + __vector_quad df, dg; + int j; + dd v; + __vector_pair dh; + __builtin_mma_assemble_pair( + &dh, (__attribute__((altivec(vector__))) char)bh.bt(0, j), + (__attribute__((altivec(vector__))) char)bh.bt(0, j)); + db(&df, dh, v); + __vector_pair di; + __builtin_mma_assemble_pair( + &di, (__attribute__((altivec(vector__))) char)bh.bt(0, j), + (__attribute__((altivec(vector__))) char)bh.bt(0, j)); + db(&dg, di, v); +} +template struct bo { + static void bn(bv, bv, w bh, cy, double, bv, double) { + dc(bh); + } +}; +void dm() { + n dk(1), y(0); + y += dk; +}