From patchwork Wed Mar 17 14:14:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 1454693 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=XMGVob80; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0sc06qlpz9sVb for ; Thu, 18 Mar 2021 01:14:40 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 52F4682884; Wed, 17 Mar 2021 15:14:32 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1615990472; bh=LG8ITKOYNu+T//yhSJe6K1VkDo06jtiIePEe7eu/FnM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=XMGVob80F8l2RkYmR+DY+ZW0AAQNDEmyJIlrqj5+/Y2QX7Fiy2+O3mzM7sfv1vW98 DPDttRj+qSjWRbfYBQZnIdftTNIsdlunXLm6MrYLWiLFWWjq1ci6miTzu5Xw3mNWCk VoVvXmjjoB51Srq2li0A3TamldYYxM2BRpkll+C7moctUXYbujkpulGDUHQo6mD2AI JJdllBxDLH6x+fIK2rRcI3dqn42Ex3iJ/m3rSakrzbH/GImyXAub2VVqGY4XmiMj3l 8tBgDI5kKIo6pFHU4rnPdkXpfu1XX2Nm9imMTTdl/odowXkWLkDyJIu++2OIFmOUQd v85duJotzrJXg== Received: by phobos.denx.de (Postfix, from userid 109) id 5C8288286B; Wed, 17 Mar 2021 15:14:26 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B937B82843 for ; Wed, 17 Mar 2021 15:14:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=lukma@denx.de Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4F0sbg39Txz1rxcC; Wed, 17 Mar 2021 15:14:23 +0100 (CET) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4F0sbg2hy3z1r1MR; Wed, 17 Mar 2021 15:14:23 +0100 (CET) Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id tOZnnL9K0u5w; Wed, 17 Mar 2021 15:14:22 +0100 (CET) X-Auth-Info: TH6zeqmTmmSNTBuLGdF/xQybGTkHy0G6hH/0J+k1DZw= Received: from localhost.localdomain (85-222-111-42.dynamic.chello.pl [85.222.111.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Wed, 17 Mar 2021 15:14:22 +0100 (CET) From: Lukasz Majewski To: u-boot@lists.denx.de Cc: Lukasz Majewski , Joe Hershberger , Ramon Fried , Simon Glass Subject: [PATCH v1 1/6] net: mv88e61xx: Add support for checking addressing mode Date: Wed, 17 Mar 2021 15:14:05 +0100 Message-Id: <20210317141410.32152-2-lukma@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210317141410.32152-1-lukma@denx.de> References: <20210317141410.32152-1-lukma@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Some Marvell switch devices are dual chip ones, like mv88e6020, which use direct MDIO addressing to access its ports' registers. Such approach allows connecting two such devices in a single MDIO bus with simple addressing scheme. Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 42 +++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 7eff37b24499..69a1dd8f1859 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -202,6 +202,7 @@ struct mv88e61xx_phy_priv { u8 phy_ctrl1_en_det_shift; /* 'EDet' bit field offset */ u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */ u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */ + u8 direct_access; /* Access switch device directly */ }; static inline int smi_cmd(int cmd, int addr, int reg) @@ -928,6 +929,40 @@ static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev) return -ENODEV; } +static int mv88e61xx_check_addressing(struct phy_device *phydev) +{ + if (!CONFIG_IS_ENABLED(OF_CONTROL)) + return 0; + + /* + * Some devices - like mv88e6020 are dual chip - i.e. two + * such devices can be directly accessed via SMI bus. + * The addressing depends on R0_LED/ADDR4 pin value duing + * bootstrap. + * + * This means that there is no need for indirect access. + */ + struct mv88e61xx_phy_priv *priv = phydev->priv; + + /* + * As this function is called very early and hence the phydev + * is not yet initialized we use aliast and DTS to asses if + * device shall be directly accessed or not. + */ + ofnode sw0; + int ret; + + sw0 = ofnode_get_aliases_node("switch0"); + if (!ofnode_valid(sw0)) + return -ENODEV; + + ret = ofnode_device_is_compatible(sw0, "marvell,mv88e6020"); + if (ret) + priv->direct_access = 1; + + return 0; +} + static int mv88e61xx_probe(struct phy_device *phydev) { struct mii_dev *smi_wrapper; @@ -982,6 +1017,8 @@ static int mv88e61xx_probe(struct phy_device *phydev) phydev->priv = priv; + mv88e61xx_check_addressing(phydev); + res = mv88e61xx_priv_reg_offs_pre_init(phydev); if (res < 0) return res; @@ -1197,6 +1234,11 @@ int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id) temp_phy.priv = &temp_priv; temp_mii.priv = &temp_phy; + mv88e61xx_check_addressing(&temp_phy); + /* For direct access the phy address equals to smi_addr */ + if (temp_priv.direct_access) + temp_phy.addr = smi_addr; + /* * get_phy_id() can be called by framework before mv88e61xx driver * probing, in this case the global register offsets are not From patchwork Wed Mar 17 14:14:06 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 1454694 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=EFSet2zr; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0scD1SpWz9sVm for ; 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Wed, 17 Mar 2021 15:14:24 +0100 (CET) Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id 6DR56DkoRfiu; Wed, 17 Mar 2021 15:14:23 +0100 (CET) X-Auth-Info: 0d4o7tK2F6tZOUivM8kKy9S9UgjjiVRo6NGedRKEbWU= Received: from localhost.localdomain (85-222-111-42.dynamic.chello.pl [85.222.111.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Wed, 17 Mar 2021 15:14:23 +0100 (CET) From: Lukasz Majewski To: u-boot@lists.denx.de Cc: Lukasz Majewski , Joe Hershberger , Ramon Fried , Simon Glass Subject: [PATCH v1 2/6] net: mv88e61xx: Configure PHY ports to also pass packets between them Date: Wed, 17 Mar 2021 15:14:06 +0100 Message-Id: <20210317141410.32152-3-lukma@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210317141410.32152-1-lukma@denx.de> References: <20210317141410.32152-1-lukma@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean After this change PHY ports are able to pass packets between them (and also to CPU port). The Kconfig variable - CONFIG_MV88E61XX_PHY_PORTS - is used to get the PHY ports of the switch and generate proper mask. Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 69a1dd8f1859..14074c0b82fb 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -873,14 +873,19 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) { + struct mv88e61xx_phy_priv *priv = phydev->priv; + u16 port_mask; int val; val = mv88e61xx_port_enable(phydev, phy); if (val < 0) return val; - val = mv88e61xx_port_set_vlan(phydev, phy, - 1 << CONFIG_MV88E61XX_CPU_PORT); + port_mask = PORT_MASK(priv->port_count) & CONFIG_MV88E61XX_PHY_PORTS; + port_mask &= ~(1 << phy); + port_mask |= (1 << CONFIG_MV88E61XX_CPU_PORT); + + val = mv88e61xx_port_set_vlan(phydev, phy, port_mask); if (val < 0) return val; From patchwork Wed Mar 17 14:14:07 2021 Content-Type: text/plain; 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Wed, 17 Mar 2021 15:14:24 +0100 (CET) From: Lukasz Majewski To: u-boot@lists.denx.de Cc: Lukasz Majewski , Joe Hershberger , Ramon Fried , Simon Glass Subject: [PATCH v1 3/6] net: mv88e61xx: Clear temporary structs before using them in get_phy_id() Date: Wed, 17 Mar 2021 15:14:07 +0100 Message-Id: <20210317141410.32152-4-lukma@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210317141410.32152-1-lukma@denx.de> References: <20210317141410.32152-1-lukma@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Those automatically created structures can have random value. However, mv88e61xx driver assumes that those are zeroed. Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 14074c0b82fb..d8116530700d 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -1230,6 +1230,10 @@ int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id) struct mii_dev temp_mii; int val; + memset(&temp_phy, 0, sizeof(temp_phy)); + memset(&temp_priv, 0, sizeof(temp_priv)); + memset(&temp_mii, 0, sizeof(temp_mii)); + /* * Buid temporary data structures that the chip reading code needs to * read the ID From patchwork Wed Mar 17 14:14:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 1454696 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Wed, 17 Mar 2021 15:14:25 +0100 (CET) From: Lukasz Majewski To: u-boot@lists.denx.de Cc: Lukasz Majewski , Joe Hershberger , Ramon Fried , Simon Glass Subject: [PATCH v1 4/6] net: mv88e61xx: Directly access the switch chip Date: Wed, 17 Mar 2021 15:14:08 +0100 Message-Id: <20210317141410.32152-5-lukma@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210317141410.32152-1-lukma@denx.de> References: <20210317141410.32152-1-lukma@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The mv88e6020 is accessed in a direct way (i.e. with direct read and write to mdio bus). The only necessary indirection is required when accessing its PHY registers. Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index d8116530700d..3d846b89fd12 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -269,8 +269,11 @@ static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg) int smi_addr = priv->smi_addr; int res; - /* In single-chip mode, the device can be addressed directly */ - if (smi_addr == 0) + /* + * In single-chip or dual-chip (like mv88e6020) mode, the device can + * be addressed directly. + */ + if (smi_addr == 0 || priv->direct_access) return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg); /* Wait for the bus to become free */ @@ -306,11 +309,13 @@ static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg, int smi_addr = priv->smi_addr; int res; - /* In single-chip mode, the device can be addressed directly */ - if (smi_addr == 0) { + /* + * In single-chip or dual-chip (like mv88e6020) mode, the device can + * be addressed directly. + */ + if (smi_addr == 0 || priv->direct_access) return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg, val); - } /* Wait for the bus to become free */ res = mv88e61xx_smi_wait(mdio_bus, smi_addr); From patchwork Wed Mar 17 14:14:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 1454697 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=Xt7irH3X; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0sd12wNRz9sVb for ; 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Wed, 17 Mar 2021 15:14:28 +0100 (CET) Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id v7V9lKpPVq9B; Wed, 17 Mar 2021 15:14:27 +0100 (CET) X-Auth-Info: 35c1VmgfqSIovW5UuLVw3eIf2CYe2k4REnjLKYu7NWA= Received: from localhost.localdomain (85-222-111-42.dynamic.chello.pl [85.222.111.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Wed, 17 Mar 2021 15:14:26 +0100 (CET) From: Lukasz Majewski To: u-boot@lists.denx.de Cc: Lukasz Majewski , Joe Hershberger , Ramon Fried , Simon Glass Subject: [PATCH v1 5/6] net: mv88e61xx: Set proper offset when R0_LED/ADDR4 is set on bootstrap Date: Wed, 17 Mar 2021 15:14:09 +0100 Message-Id: <20210317141410.32152-6-lukma@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210317141410.32152-1-lukma@denx.de> References: <20210317141410.32152-1-lukma@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The mv88e61xx driver need to be adjusted to handle situation when switch MDIO addresses are switched by offset (0x10 in this case). Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 3d846b89fd12..325d5b56135f 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -45,7 +45,6 @@ #define PORT_MASK(port_count) ((1 << (port_count)) - 1) /* Device addresses */ -#define DEVADDR_PHY(p) (p) #define DEVADDR_SERDES 0x0F /* SMI indirection registers for multichip addressing mode */ @@ -414,7 +413,7 @@ static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev, /* Wrapper function to make calls to phy_read_indirect simpler */ static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg) { - return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy), + return mv88e61xx_phy_read_indirect(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, reg); } @@ -422,7 +421,7 @@ static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg) static int mv88e61xx_phy_write(struct phy_device *phydev, int phy, int reg, u16 val) { - return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy), + return mv88e61xx_phy_write_indirect(phydev->bus, phydev->addr, MDIO_DEVAD_NONE, reg, val); } @@ -926,12 +925,21 @@ static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev) /* * Now try via port registers with device address 0x08 * (88E6020 and compatible switches). + * + * When R0_LED/ADDR4 is set during bootstrap, one needs + * to add 0x10 offset to switch addresses. + * + * The phydev->addr is set according to device tree address + * of MDIO accessible device: + * + * When on board RO_LED/ADDR4 = 1 -> 0x10 + * 0 -> 0x0 */ - priv->port_reg_base = 0x08; + priv->port_reg_base = 0x08 + phydev->addr; priv->id = mv88e61xx_get_switch_id(phydev); if (priv->id != 0xfff0) { - priv->global1 = 0x0F; - priv->global2 = 0x07; + priv->global1 = 0x0F + phydev->addr; + priv->global2 = 0x07 + phydev->addr; return 0; } @@ -1090,7 +1098,10 @@ static int mv88e61xx_phy_config(struct phy_device *phydev) for (i = 0; i < priv->port_count; i++) { if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { - phydev->addr = i; + if (phydev->addr) + phydev->addr += i; + else + phydev->addr = i; res = mv88e61xx_phy_enable(phydev, i); if (res < 0) { From patchwork Wed Mar 17 14:14:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 1454698 X-Patchwork-Delegate: rfried.dev@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=denx.de header.i=@denx.de header.a=rsa-sha256 header.s=phobos-20191101 header.b=ioIDpk/l; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0sdJ31kDz9sVb for ; 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Wed, 17 Mar 2021 15:14:29 +0100 (CET) Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id 4KiioiajIPpR; Wed, 17 Mar 2021 15:14:28 +0100 (CET) X-Auth-Info: n4FE5xo8DgfmpXvXhCakiikqHXuhd9TFWg/bDxdWv6A= Received: from localhost.localdomain (85-222-111-42.dynamic.chello.pl [85.222.111.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Wed, 17 Mar 2021 15:14:28 +0100 (CET) From: Lukasz Majewski To: u-boot@lists.denx.de Cc: Lukasz Majewski , Joe Hershberger , Ramon Fried , Simon Glass Subject: [PATCH v1 6/6] net: mv88e61xx: Reset switch PHYs when bootstrapped to !NO_CPU Date: Wed, 17 Mar 2021 15:14:10 +0100 Message-Id: <20210317141410.32152-7-lukma@denx.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210317141410.32152-1-lukma@denx.de> References: <20210317141410.32152-1-lukma@denx.de> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean Some devices, when configured in bootstrap to 'no cpu' mode require PHY manual reset to get them operational and responding to reading their ID registers. Without this step - the PHYLIB probing will fail. In more details - the bootstrap configuration from switch must be read. The value of CONFIG Data1 (0x71) of Scratch and Misc register is read to check if 'no_cpu' and 'addr4' bits were set. Signed-off-by: Lukasz Majewski Reviewed-by: Ramon Fried --- drivers/net/phy/mv88e61xx.c | 63 +++++++++++++++++++++++++++++++++++-- 1 file changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 325d5b56135f..1fa821ca162b 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -202,6 +202,17 @@ struct mv88e61xx_phy_priv { u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */ u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */ u8 direct_access; /* Access switch device directly */ + /* + * Bootstrap configuration: + * + * If addr4 = 1 device is accessible from 0x10 address on MDIO bus. + */ + u8 addr4; + /* + * If no_cpu = 1 switch is automatically setup, otherwise PHY reset is + * required from CPU for normal operation. + */ + u8 no_cpu; }; static inline int smi_cmd(int cmd, int addr, int reg) @@ -1235,6 +1246,33 @@ int phy_mv88e61xx_init(void) return 0; } +static int mv88e61xx_read_bootstrap(struct phy_device *phydev) +{ + struct mv88e61xx_phy_priv *priv = phydev->priv; + struct mii_dev *mdio_bus = priv->mdio_bus; + int val; + + /* mv88e6020 - ID = 0x0200 (REG 3 on non PHY port) */ + if (priv->id == PORT_SWITCH_ID_6020) { + /* Prepare to read scratch and misc register */ + mdio_bus->write(mdio_bus, priv->global2, 0, + 0x1a /*MV_SCRATCH_MISC*/, + (0x71 /*MV_CONFIG_DATA1*/ << 8)); + + val = mdio_bus->read(mdio_bus, priv->global2, 0, + 0x1a /*MV_SCRATCH_MISC*/); + + if (val & (1 << 0)) + priv->no_cpu = 1; + if (val & (1 << 4)) + priv->addr4 = 1; + debug("mv88e6020: no_cpu=%d addr4=%d\n", priv->no_cpu, + priv->addr4); + } + + return 0; +} + /* * Overload weak get_phy_id definition since we need non-standard functions * to read PHY registers @@ -1274,13 +1312,34 @@ int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id) if (val < 0) return val; - val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1); + mv88e61xx_read_bootstrap(&temp_phy); + + /* + * When switch is configured to work with CPU (i.e. NO_CPU == 0), PHYs + * require reset (to at least single one) to have its registers + * accessible. + */ + if (!temp_priv.no_cpu && temp_priv.id == PORT_SWITCH_ID_6020) { + /* Reset PHY */ + val = mv88e61xx_phy_read_indirect(&temp_mii, temp_phy.addr, + devad, MII_BMCR); + if (val & BMCR_PDOWN) + val &= ~BMCR_PDOWN; + + mv88e61xx_phy_write_indirect(&temp_mii, temp_phy.addr, devad, + MII_BMCR, val); + } + + /* Read PHY_ID */ + val = mv88e61xx_phy_read_indirect(&temp_mii, temp_phy.addr, devad, + MII_PHYSID1); if (val < 0) return -EIO; *phy_id = val << 16; - val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2); + val = mv88e61xx_phy_read_indirect(&temp_mii, temp_phy.addr, devad, + MII_PHYSID2); if (val < 0) return -EIO;