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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id l20sm18556705pfd.82.2021.03.16.18.16.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Mar 2021 18:16:47 -0700 (PDT) From: Vincent Chen To: opensbi@lists.infradead.org Cc: Vincent Chen Subject: [PATCH v3 1/2] firmware: Use lla to access all global symbols Date: Wed, 17 Mar 2021 09:16:37 +0800 Message-Id: <1615943798-14296-2-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615943798-14296-1-git-send-email-vincent.chen@sifive.com> References: <1615943798-14296-1-git-send-email-vincent.chen@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210317_011655_268386_1B691C92 X-CRM114-Status: GOOD ( 14.69 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: When OpenSBI is compiled as fPIE mode, the assembler will translate "la" to GOT reference pattern. It will cause to cost an additional load instruction when obtaining the symbol address. However, if t [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:431 listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org When OpenSBI is compiled as fPIE mode, the assembler will translate "la" to GOT reference pattern. It will cause to cost an additional load instruction when obtaining the symbol address. However, if the symbol locates within the positive or negative 2GB region, we can use "lla" instead of "la" to avoid unneeded GOT references. This patch assumes that the OpenSBI image excluding the payload does not exceed 2GB. Based on this assumption, all "la" instructions are replaced by "lla" to avoid performance degradation when compiling as fPIE mode. Signed-off-by: Vincent Chen Reviewed-by: Anup Patel --- firmware/fw_base.S | 88 +++++++++++++++++++++---------------------- firmware/fw_dynamic.S | 18 ++++----- firmware/fw_jump.S | 2 +- firmware/fw_payload.S | 2 +- firmware/payloads/test_head.S | 18 ++++----- 5 files changed, 64 insertions(+), 64 deletions(-) diff --git a/firmware/fw_base.S b/firmware/fw_base.S index ab33e11..6cc5f88 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -57,39 +57,39 @@ _start: bne a0, a6, _wait_relocate_copy_done _try_lottery: /* Jump to relocation wait loop if we don't get relocation lottery */ - la a6, _relocate_lottery + lla a6, _relocate_lottery li a7, 1 amoadd.w a6, a7, (a6) bnez a6, _wait_relocate_copy_done /* Save load address */ - la t0, _load_start - la t1, _start + lla t0, _load_start + lla t1, _start REG_S t1, 0(t0) /* Relocate if load address != link address */ _relocate: - la t0, _link_start + lla t0, _link_start REG_L t0, 0(t0) - la t1, _link_end + lla t1, _link_end REG_L t1, 0(t1) - la t2, _load_start + lla t2, _load_start REG_L t2, 0(t2) sub t3, t1, t0 add t3, t3, t2 beq t0, t2, _relocate_done - la t4, _relocate_done + lla t4, _relocate_done sub t4, t4, t2 add t4, t4, t0 blt t2, t0, _relocate_copy_to_upper _relocate_copy_to_lower: ble t1, t2, _relocate_copy_to_lower_loop - la t3, _relocate_lottery + lla t3, _relocate_lottery BRANGE t2, t1, t3, _start_hang - la t3, _boot_status + lla t3, _boot_status BRANGE t2, t1, t3, _start_hang - la t3, _relocate - la t5, _relocate_done + lla t3, _relocate + lla t5, _relocate_done BRANGE t2, t1, t3, _start_hang BRANGE t2, t1, t5, _start_hang BRANGE t3, t5, t2, _start_hang @@ -102,12 +102,12 @@ _relocate_copy_to_lower_loop: jr t4 _relocate_copy_to_upper: ble t3, t0, _relocate_copy_to_upper_loop - la t2, _relocate_lottery + lla t2, _relocate_lottery BRANGE t0, t3, t2, _start_hang - la t2, _boot_status + lla t2, _boot_status BRANGE t0, t3, t2, _start_hang - la t2, _relocate - la t5, _relocate_done + lla t2, _relocate + lla t5, _relocate_done BRANGE t0, t3, t2, _start_hang BRANGE t0, t3, t5, _start_hang BRANGE t2, t5, t0, _start_hang @@ -119,12 +119,12 @@ _relocate_copy_to_upper_loop: blt t0, t1, _relocate_copy_to_upper_loop jr t4 _wait_relocate_copy_done: - la t0, _start - la t1, _link_start + lla t0, _start + lla t1, _link_start REG_L t1, 0(t1) beq t0, t1, _wait_for_boot_hart - la t2, _boot_status - la t3, _wait_for_boot_hart + lla t2, _boot_status + lla t3, _wait_for_boot_hart sub t3, t3, t0 add t3, t3, t1 1: @@ -143,10 +143,10 @@ _relocate_done: * Mark relocate copy done * Use _boot_status copy relative to the load address */ - la t0, _boot_status - la t1, _link_start + lla t0, _boot_status + lla t1, _link_start REG_L t1, 0(t1) - la t2, _load_start + lla t2, _load_start REG_L t2, 0(t2) sub t0, t0, t1 add t0, t0, t2 @@ -161,19 +161,19 @@ _relocate_done: call _reset_regs /* Zero-out BSS */ - la s4, _bss_start - la s5, _bss_end + lla s4, _bss_start + lla s5, _bss_end _bss_zero: REG_S zero, (s4) add s4, s4, __SIZEOF_POINTER__ blt s4, s5, _bss_zero /* Setup temporary trap handler */ - la s4, _start_hang + lla s4, _start_hang csrw CSR_MTVEC, s4 /* Setup temporary stack */ - la s4, _fw_end + lla s4, _fw_end li s5, (SBI_SCRATCH_SIZE * 2) add sp, s4, s5 @@ -184,7 +184,7 @@ _bss_zero: #ifdef FW_FDT_PATH /* Override previous arg1 */ - la a1, fw_fdt_bin + lla a1, fw_fdt_bin #endif /* @@ -202,7 +202,7 @@ _bss_zero: * s7 -> HART Count * s8 -> HART Stack Size */ - la a4, platform + lla a4, platform #if __riscv_xlen == 64 lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4) @@ -212,7 +212,7 @@ _bss_zero: #endif /* Setup scratch space for all the HARTs*/ - la tp, _fw_end + lla tp, _fw_end mul a5, s7, s8 add tp, tp, a5 /* Keep a copy of tp */ @@ -230,8 +230,8 @@ _scratch_init: /* Initialize scratch space */ /* Store fw_start and fw_size in scratch space */ - la a4, _fw_start - la a5, _fw_end + lla a4, _fw_start + lla a5, _fw_end mul t0, s7, s8 add a5, a5, t0 sub a5, a5, a4 @@ -253,16 +253,16 @@ _scratch_init: REG_S a0, SBI_SCRATCH_NEXT_MODE_OFFSET(tp) MOV_3R a0, s0, a1, s1, a2, s2 /* Store warm_boot address in scratch space */ - la a4, _start_warm + lla a4, _start_warm REG_S a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) /* Store platform address in scratch space */ - la a4, platform + lla a4, platform REG_S a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp) /* Store hartid-to-scratch function address in scratch space */ - la a4, _hartid_to_scratch + lla a4, _hartid_to_scratch REG_S a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) /* Store trap-exit function address in scratch space */ - la a4, _trap_exit + lla a4, _trap_exit REG_S a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp) /* Clear tmp0 in scratch space */ REG_S zero, SBI_SCRATCH_TMP0_OFFSET(tp) @@ -343,7 +343,7 @@ _fdt_reloc_done: /* mark boot hart done */ li t0, BOOT_STATUS_BOOT_HART_DONE - la t1, _boot_status + lla t1, _boot_status REG_S t0, 0(t1) fence rw, rw j _start_warm @@ -351,7 +351,7 @@ _fdt_reloc_done: /* waiting for boot hart to be done (_boot_status == 2) */ _wait_for_boot_hart: li t0, BOOT_STATUS_BOOT_HART_DONE - la t1, _boot_status + lla t1, _boot_status REG_L t1, 0(t1) /* Reduce the bus traffic so that boot hart may proceed faster */ nop @@ -369,7 +369,7 @@ _start_warm: csrw CSR_MIP, zero /* Find HART count and HART stack size */ - la a4, platform + lla a4, platform #if __riscv_xlen == 64 lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4) lwu s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4) @@ -400,7 +400,7 @@ _start_warm: 3: bge s6, s7, _start_hang /* Find the scratch space based on HART index */ - la tp, _fw_end + lla tp, _fw_end mul a5, s7, s8 add tp, tp, a5 mul a5, s8, s6 @@ -415,13 +415,13 @@ _start_warm: add sp, tp, zero /* Setup trap handler */ - la a4, _trap_handler + lla a4, _trap_handler #if __riscv_xlen == 32 csrr a5, CSR_MISA srli a5, a5, ('H' - 'A') andi a5, a5, 0x1 beq a5, zero, _skip_trap_handler_rv32_hyp - la a4, _trap_handler_rv32_hyp + lla a4, _trap_handler_rv32_hyp _skip_trap_handler_rv32_hyp: #endif csrw CSR_MTVEC, a4 @@ -432,7 +432,7 @@ _skip_trap_handler_rv32_hyp: srli a5, a5, ('H' - 'A') andi a5, a5, 0x1 beq a5, zero, _skip_trap_exit_rv32_hyp - la a4, _trap_exit_rv32_hyp + lla a4, _trap_exit_rv32_hyp csrr a5, CSR_MSCRATCH REG_S a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(a5) _skip_trap_exit_rv32_hyp: @@ -468,7 +468,7 @@ _hartid_to_scratch: * t1 -> HART Stack End * t2 -> Temporary */ - la t2, platform + lla t2, platform #if __riscv_xlen == 64 lwu t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2) lwu t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2) @@ -478,7 +478,7 @@ _hartid_to_scratch: #endif sub t2, t2, a1 mul t2, t2, t0 - la t1, _fw_end + lla t1, _fw_end add t1, t1, t2 li t2, SBI_SCRATCH_SIZE sub a0, t1, t2 diff --git a/firmware/fw_dynamic.S b/firmware/fw_dynamic.S index 8b56947..0705e63 100644 --- a/firmware/fw_dynamic.S +++ b/firmware/fw_dynamic.S @@ -54,7 +54,7 @@ fw_boot_hart: */ fw_save_info: /* Save next arg1 in 'a1' */ - la a4, _dynamic_next_arg1 + lla a4, _dynamic_next_arg1 REG_S a1, (a4) /* Sanity checks */ @@ -66,13 +66,13 @@ fw_save_info: bgt a3, a4, _bad_dynamic_info /* Save version == 0x1 fields */ - la a4, _dynamic_next_addr + lla a4, _dynamic_next_addr REG_L a3, FW_DYNAMIC_INFO_NEXT_ADDR_OFFSET(a2) REG_S a3, (a4) - la a4, _dynamic_next_mode + lla a4, _dynamic_next_mode REG_L a3, FW_DYNAMIC_INFO_NEXT_MODE_OFFSET(a2) REG_S a3, (a4) - la a4, _dynamic_options + lla a4, _dynamic_options REG_L a3, FW_DYNAMIC_INFO_OPTIONS_OFFSET(a2) REG_S a3, (a4) @@ -80,7 +80,7 @@ fw_save_info: li a4, 0x2 REG_L a3, FW_DYNAMIC_INFO_VERSION_OFFSET(a2) blt a3, a4, 2f - la a4, _dynamic_boot_hart + lla a4, _dynamic_boot_hart REG_L a3, FW_DYNAMIC_INFO_BOOT_HART_OFFSET(a2) REG_S a3, (a4) 2: @@ -96,7 +96,7 @@ fw_save_info: * The next arg1 should be returned in 'a0'. */ fw_next_arg1: - la a0, _dynamic_next_arg1 + lla a0, _dynamic_next_arg1 REG_L a0, (a0) ret @@ -108,7 +108,7 @@ fw_next_arg1: * The next address should be returned in 'a0'. */ fw_next_addr: - la a0, _dynamic_next_addr + lla a0, _dynamic_next_addr REG_L a0, (a0) ret @@ -120,7 +120,7 @@ fw_next_addr: * The next address should be returned in 'a0' */ fw_next_mode: - la a0, _dynamic_next_mode + lla a0, _dynamic_next_mode REG_L a0, (a0) ret @@ -133,7 +133,7 @@ fw_next_mode: * The next address should be returned in 'a0'. */ fw_options: - la a0, _dynamic_options + lla a0, _dynamic_options REG_L a0, (a0) ret diff --git a/firmware/fw_jump.S b/firmware/fw_jump.S index 8553f8c..5b24f8b 100644 --- a/firmware/fw_jump.S +++ b/firmware/fw_jump.S @@ -59,7 +59,7 @@ fw_next_arg1: * The next address should be returned in 'a0'. */ fw_next_addr: - la a0, _jump_addr + lla a0, _jump_addr REG_L a0, (a0) ret diff --git a/firmware/fw_payload.S b/firmware/fw_payload.S index 1ef121e..c53a3bb 100644 --- a/firmware/fw_payload.S +++ b/firmware/fw_payload.S @@ -59,7 +59,7 @@ fw_next_arg1: * The next address should be returned in 'a0'. */ fw_next_addr: - la a0, payload_bin + lla a0, payload_bin ret .section .entry, "ax", %progbits diff --git a/firmware/payloads/test_head.S b/firmware/payloads/test_head.S index 840013e..4852f71 100644 --- a/firmware/payloads/test_head.S +++ b/firmware/payloads/test_head.S @@ -28,20 +28,20 @@ .globl _start _start: /* Pick one hart to run the main boot sequence */ - la a3, _hart_lottery + lla a3, _hart_lottery li a2, 1 amoadd.w a3, a2, (a3) bnez a3, _start_hang /* Save a0 and a1 */ - la a3, _boot_a0 + lla a3, _boot_a0 REG_S a0, 0(a3) - la a3, _boot_a1 + lla a3, _boot_a1 REG_S a1, 0(a3) /* Zero-out BSS */ - la a4, _bss_start - la a5, _bss_end + lla a4, _bss_start + lla a5, _bss_end _bss_zero: REG_S zero, (a4) add a4, a4, __SIZEOF_POINTER__ @@ -53,18 +53,18 @@ _start_warm: csrw CSR_SIP, zero /* Setup exception vectors */ - la a3, _start_hang + lla a3, _start_hang csrw CSR_STVEC, a3 /* Setup stack */ - la a3, _payload_end + lla a3, _payload_end li a4, 0x2000 add sp, a3, a4 /* Jump to C main */ - la a3, _boot_a0 + lla a3, _boot_a0 REG_L a0, 0(a3) - la a3, _boot_a1 + lla a3, _boot_a1 REG_L a1, 0(a3) call test_main From patchwork Wed Mar 17 01:16:38 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Chen X-Patchwork-Id: 1454376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1:d65d:64ff:fe57:4e05; helo=desiato.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=desiato.20200630 header.b=evfVuD4R; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=KTDuGm5U; dkim-atps=neutral Received: from desiato.infradead.org (desiato.infradead.org [IPv6:2001:8b0:10b:1:d65d:64ff:fe57:4e05]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4F0XLx66nHz9sWH for ; Wed, 17 Mar 2021 12:17:13 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:MIME-Version:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:Cc:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=B5PQYZY5wTWqwXMyJ4zb7yXFhvAO2qgelKAiE0DSzC0=; b=evfVuD4RNoyxz/0foS8LlcDV47 iGw28DbdEwjYeylRSwZX+0uPEW7EzUenLFPI86iqciRuVOfW7/qoFyKVwj0jhfWGtmE9AQX2E5/tC WLfTBI7412aCrTaK6SYRkU5kLSsZzExe8MIhYDUbIdXuItCvIMAk/lgE3T4rd/wbd0ppUkmdeqVZg FHvHCsPF9J7ptWHGN7AchNDDXNhAIO7rg4lQD2xzSgr4gB3/395bnwnvattoqUBJt3nNNszUZSs9Z dnTTmXqcKUr0Rt99tXGSlM4t8nRitiyeY4bSq2OITsmEmlqh16juZkbf1l71wBfnx+p2EpgnuhsIy IjlP1qUw==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lMKo5-002BSX-CY; Wed, 17 Mar 2021 01:17:05 +0000 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lMKns-002BPu-NJ for opensbi@lists.infradead.org; Wed, 17 Mar 2021 01:16:59 +0000 Received: by mail-pg1-x52e.google.com with SMTP id l2so23807693pgb.1 for ; Tue, 16 Mar 2021 18:16:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=q8J50e1excBApjSvqZ3GZiAKdLyWLMmf7d0b8CBtaLE=; b=KTDuGm5UVRxVGDZehK60p/UeVsje6NFAroTz5BPUtS+ARAHlP33FGnp/cazrECs1d2 ObC9PqNs5eWW+GE6pUEXfzS6YUu3uOuXF1y8cVbIG33Af6Ht8vhERPYt96GY32y5Mxlu CkQGeXSujJx9+gbYLnaF0wr7W8Y7uSPhnNbqIz1VNjGN7oX6UvGdrw8nc7n4tAUNa442 QtzFD/gZeRDl+S07/BLby1NjAZ6Vbqzo7JdTmJaIi9LCFumuImdoNitQFLJd4L930dPq EfyX4pB71jgZ02Db0zndYqov3Y/+caWHzIQDIQnw4oeWpCGHOIbafv0xGi5zwgv4YRKc PxPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=q8J50e1excBApjSvqZ3GZiAKdLyWLMmf7d0b8CBtaLE=; b=oz+bgTTTkGmrRG0YviJLY0MH/wwlKE6KlgWVaiYTbZTUs1zduAx+uQh4Jprfdh1Ei5 lu7Q/BmmxIZXSdl1n4Vx/gxfxz42IdtCq1ymX7ODWlcIrgGCcqqJ4bDky7CIB5pWgaIe EuLMYnEqJR9RVawpehnPuf1VejikCP5luME2jfebkJXjNw1b3DEZHIWUK3oh0s+91LTk DFNwz+x8cYVRXlNZ/4/aN+1khObe5R0qY+W2lF2/VxerkIQ6hchBBaVWfsz2nyMShSNj lT9kcUN9fDr4Hdc8LIStoMwuriVPNj0oCLrEnUXElBWyYYizgGJFFkg1firtI5cylZka nbcg== X-Gm-Message-State: AOAM533fj4rcf2h0wrceSsZExYo+TuvvX8b3FE3Cf2Y6rlUNuHbuBdOt amET0LhUc57Xutk16PH+wpqf64hVz7xZUhKt X-Google-Smtp-Source: ABdhPJxnMKMmi9myyyB4eqt7nSY3QE02ym1XZmkpIvxtvVr9uBWyXk3gmZIfhTuApRd7cVNp8RRm4g== X-Received: by 2002:a63:520e:: with SMTP id g14mr448535pgb.350.1615943809370; Tue, 16 Mar 2021 18:16:49 -0700 (PDT) Received: from VincentChen-ThinkPad-T480s.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id l20sm18556705pfd.82.2021.03.16.18.16.48 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Mar 2021 18:16:49 -0700 (PDT) From: Vincent Chen To: opensbi@lists.infradead.org Cc: Vincent Chen Subject: [PATCH v3 2/2] firmware: Support position independent execution Date: Wed, 17 Mar 2021 09:16:38 +0800 Message-Id: <1615943798-14296-3-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615943798-14296-1-git-send-email-vincent.chen@sifive.com> References: <1615943798-14296-1-git-send-email-vincent.chen@sifive.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210317_011655_310611_80AB4C31 X-CRM114-Status: GOOD ( 18.43 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Enable OpenSBI to support position independent execution. Because the position independent code will cause an additional GOT reference when accessing the global variables, it will reduce performance a [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52e listed in] [list.dnswl.org] 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain X-BeenThere: opensbi@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "opensbi" Errors-To: opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Enable OpenSBI to support position independent execution. Because the position independent code will cause an additional GOT reference when accessing the global variables, it will reduce performance a bit. Therefore, the position independent execution is disabled by default. Users can through specifying "FW_PIC=y" on the make command to enable this feature. In theory, after enabling position-independent execution, the OpenSBI can run at arbitrary address with appropriate alignment. Therefore, the original relocation mechanism will be skipped. In other words, OpenSBI will directly run at the load address without any code movement. Signed-off-by: Vincent Chen Reviewed-by: Anup Patel --- Makefile | 2 +- firmware/fw_base.S | 62 ++++++++++++++++++++++++++++++++++++++++++++++++- firmware/fw_base.ldS | 13 +++++++++++ firmware/objects.mk | 7 ++++++ include/sbi/riscv_elf.h | 14 +++++++++++ 5 files changed, 96 insertions(+), 2 deletions(-) create mode 100644 include/sbi/riscv_elf.h diff --git a/Makefile b/Makefile index d6f097d..038cc99 100644 --- a/Makefile +++ b/Makefile @@ -210,8 +210,8 @@ CFLAGS += -mabi=$(PLATFORM_RISCV_ABI) -march=$(PLATFORM_RISCV_ISA) CFLAGS += -mcmodel=$(PLATFORM_RISCV_CODE_MODEL) CFLAGS += $(GENFLAGS) CFLAGS += $(platform-cflags-y) -CFLAGS += $(firmware-cflags-y) CFLAGS += -fno-pie -no-pie +CFLAGS += $(firmware-cflags-y) CPPFLAGS += $(GENFLAGS) CPPFLAGS += $(platform-cppflags-y) diff --git a/firmware/fw_base.S b/firmware/fw_base.S index 6cc5f88..2ce3851 100644 --- a/firmware/fw_base.S +++ b/firmware/fw_base.S @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -67,6 +68,58 @@ _try_lottery: lla t1, _start REG_S t1, 0(t0) +#ifdef FW_PIC + /* relocate the global table content */ + lla t0, _link_start + REG_L t0, 0(t0) + /* t1 shall has the address of _start */ + sub t2, t1, t0 + lla t3, _runtime_offset + REG_S t2, (t3) + lla t0, __rel_dyn_start + lla t1, __rel_dyn_end + beq t0, t1, _relocate_done + j 5f +2: + REG_L t5, -(REGBYTES*2)(t0) /* t5 <-- relocation info:type */ + li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */ + bne t5, t3, 3f + REG_L t3, -(REGBYTES*3)(t0) + REG_L t5, -(REGBYTES)(t0) /* t5 <-- addend */ + add t5, t5, t2 + add t3, t3, t2 + REG_S t5, 0(t3) /* store runtime address to the GOT entry */ + j 5f + +3: + lla t4, __dyn_sym_start + +4: + REG_L t5, -(REGBYTES*2)(t0) /* t5 <-- relocation info:type */ + srli t6, t5, SYM_INDEX /* t6 <--- sym table index */ + andi t5, t5, 0xFF /* t5 <--- relocation type */ + li t3, RELOC_TYPE + bne t5, t3, 5f + + /* address R_RISCV_64 or R_RISCV_32 cases*/ + REG_L t3, -(REGBYTES*3)(t0) + li t5, SYM_SIZE + mul t6, t6, t5 + add s5, t4, t6 + REG_L t6, -(REGBYTES)(t0) /* t0 <-- addend */ + REG_L t5, REGBYTES(s5) + add t5, t5, t6 + add t5, t5, t2 /* t5 <-- location to fix up in RAM */ + add t3, t3, t2 /* t3 <-- location to fix up in RAM */ + REG_S t5, 0(t3) /* store runtime address to the variable */ + +5: + addi t0, t0, (REGBYTES*3) + ble t0, t1, 2b + j _relocate_done +_wait_relocate_copy_done: + j _wait_for_boot_hart +#else /* Relocate if load address != link address */ _relocate: lla t0, _link_start @@ -137,6 +190,7 @@ _wait_relocate_copy_done: nop bgt t4, t5, 1b jr t3 +#endif _relocate_done: /* @@ -144,12 +198,14 @@ _relocate_done: * Use _boot_status copy relative to the load address */ lla t0, _boot_status +#ifndef FW_PIC lla t1, _link_start REG_L t1, 0(t1) lla t2, _load_start REG_L t2, 0(t2) sub t0, t0, t1 add t0, t0, t2 +#endif li t1, BOOT_STATUS_RELOCATE_DONE REG_S t1, 0(t0) fence rw, rw @@ -446,6 +502,10 @@ _skip_trap_exit_rv32_hyp: j _start_hang .align 3 +#ifdef FW_PIC +_runtime_offset: + RISCV_PTR 0 +#endif _relocate_lottery: RISCV_PTR 0 _boot_status: @@ -453,7 +513,7 @@ _boot_status: _load_start: RISCV_PTR _fw_start _link_start: - RISCV_PTR _fw_start + RISCV_PTR FW_TEXT_START _link_end: RISCV_PTR _fw_reloc_end diff --git a/firmware/fw_base.ldS b/firmware/fw_base.ldS index 0ac75f2..0d222da 100644 --- a/firmware/fw_base.ldS +++ b/firmware/fw_base.ldS @@ -61,6 +61,19 @@ PROVIDE(_data_end = .); } + .dynsym : { + PROVIDE(__dyn_sym_start = .); + *(.dynsym) + PROVIDE(__dyn_sym_end = .); + } + + .rela.dyn : { + PROVIDE(__rel_dyn_start = .); + *(.rela*) + . = ALIGN(8); + PROVIDE(__rel_dyn_end = .); + } + . = ALIGN(0x1000); /* Ensure next section is page aligned */ .bss : diff --git a/firmware/objects.mk b/firmware/objects.mk index b2ace75..c1f632e 100644 --- a/firmware/objects.mk +++ b/firmware/objects.mk @@ -13,6 +13,13 @@ firmware-cflags-y += firmware-asflags-y += firmware-ldflags-y += +ifeq ($(FW_PIC),y) +firmware-genflags-y += -DFW_PIC +firmware-asflags-y += -fpic +firmware-cflags-y += -fPIE -pie +firmware-ldflags-y += -Wl,--no-dynamic-linker +endif + ifdef FW_TEXT_START firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START) endif diff --git a/include/sbi/riscv_elf.h b/include/sbi/riscv_elf.h new file mode 100644 index 0000000..5d6180a --- /dev/null +++ b/include/sbi/riscv_elf.h @@ -0,0 +1,14 @@ +#ifndef SBI_RISCV_ELF_H__ +#define SBI_RISCV_ELF_H__ + +#include + +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 + +#define RELOC_TYPE __REG_SEL(R_RISCV_64, R_RISCV_32) +#define SYM_INDEX __REG_SEL(0x20, 0x8) +#define SYM_SIZE __REG_SEL(0x18,0x10) + +#endif