From patchwork Sat Sep 9 07:05:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 811915 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xq4wX3SbNz9sBW for ; Sat, 9 Sep 2017 17:06:04 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xq4wX2KgXzDrnl for ; Sat, 9 Sep 2017 17:06:04 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xq4wN0Lj5zDrcf for ; Sat, 9 Sep 2017 17:05:55 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8975TdS025373; Sat, 9 Sep 2017 02:05:30 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 9 Sep 2017 17:05:19 +1000 Message-Id: <20170909070525.8154-1-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 Subject: [Skiboot] [PATCH 1/7] xive: Remove useless memory barriers in VP/EQ inits X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We no longer update "live" memory structures, we use a temporary copy on the stack and update the actual memory structure using the cache watch, so those barriers are pointless. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index e478efc1..fb9257e3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -887,7 +887,6 @@ static void xive_init_default_vp(struct xive_vp *vp, */ vp->w1 = (eq_blk << 28) | eq_idx; vp->w5 = 0xff000000; - lwsync(); vp->w0 = VP_W0_VALID; } @@ -903,7 +902,6 @@ static void xive_init_emu_eq(uint32_t vp_blk, uint32_t vp_idx, eq->w6 = SETFIELD(EQ_W6_NVT_BLOCK, 0ul, vp_blk) | SETFIELD(EQ_W6_NVT_INDEX, 0ul, vp_idx); eq->w7 = SETFIELD(EQ_W7_F0_PRIORITY, 0ul, prio); - eieio(); eq->w0 = EQ_W0_VALID | EQ_W0_ENQUEUE | SETFIELD(EQ_W0_QSIZE, 0ul, EQ_QSIZE_64K) | EQ_W0_FIRMWARE; From patchwork Sat Sep 9 07:05:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 811920 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xq4xW5L4jz9sBW for ; Sat, 9 Sep 2017 17:06:55 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xq4xW4Rv1zDrpg for ; Sat, 9 Sep 2017 17:06:55 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xq4wV2mqZzDrnS for ; Sat, 9 Sep 2017 17:06:01 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8975TdT025373; Sat, 9 Sep 2017 02:05:32 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 9 Sep 2017 17:05:20 +1000 Message-Id: <20170909070525.8154-2-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170909070525.8154-1-benh@kernel.crashing.org> References: <20170909070525.8154-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 2/7] xive: Don't try setting the reserved ACK# field in VPs X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" That doesn't work, the HW doesn't implement it in the cache watch facility anyway. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index fb9257e3..9148c5f6 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -882,11 +882,8 @@ static void xive_init_default_vp(struct xive_vp *vp, { memset(vp, 0, sizeof(struct xive_vp)); - /* Stash the EQ base in the pressure relief interrupt field - * and set the ACK# to 0xff to disable pressure relief interrupts - */ + /* Stash the EQ base in the pressure relief interrupt field */ vp->w1 = (eq_blk << 28) | eq_idx; - vp->w5 = 0xff000000; vp->w0 = VP_W0_VALID; } From patchwork Sat Sep 9 07:05:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 811921 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xq4xt2xnYz9sBW for ; Sat, 9 Sep 2017 17:07:14 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xq4xt25glzDrqB for ; Sat, 9 Sep 2017 17:07:14 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xq4wc6vZHzDrnj for ; Sat, 9 Sep 2017 17:06:08 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8975TdU025373; Sat, 9 Sep 2017 02:05:39 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 9 Sep 2017 17:05:21 +1000 Message-Id: <20170909070525.8154-3-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170909070525.8154-1-benh@kernel.crashing.org> References: <20170909070525.8154-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 3/7] xive: Ensure pressure relief interrupts are disabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We don't use them and we hijack the VP field with their configuration to store the EQ reference, so make sure the kernel or guest can't turn them back on by doing MMIO writes to ACK# Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 2 ++ include/xive.h | 1 + 2 files changed, 3 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 9148c5f6..d6628a09 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1623,6 +1623,8 @@ static bool xive_config_init(struct xive *x) #endif val |= PC_TCTXT_CHIPID_OVERRIDE; val |= PC_TCTXT_CFG_TARGET_EN; + /* Disable pressure relief as we hijack the field in the VPs */ + val &= ~PC_TCTXT_CFG_STORE_ACK; val = SETFIELD(PC_TCTXT_CHIPID, val, x->block_id); xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); diff --git a/include/xive.h b/include/xive.h index 860373c9..70f6499f 100644 --- a/include/xive.h +++ b/include/xive.h @@ -75,6 +75,7 @@ #define PC_TCTXT_CFG 0x400 #define PC_TCTXT_CFG_BLKGRP_EN PPC_BIT(0) #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) +#define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) From patchwork Sat Sep 9 07:05:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 811919 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xq4xL4mVBz9sBW for ; Sat, 9 Sep 2017 17:06:46 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xq4xL3rJlzDrpK for ; Sat, 9 Sep 2017 17:06:46 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xq4wR67JKzDrcf for ; Sat, 9 Sep 2017 17:05:59 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8975TdV025373; Sat, 9 Sep 2017 02:05:41 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 9 Sep 2017 17:05:22 +1000 Message-Id: <20170909070525.8154-4-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170909070525.8154-1-benh@kernel.crashing.org> References: <20170909070525.8154-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 4/7] xive: Add debug code to check initial cache updates X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This adds debug code to check that the initial updates of in-memory VPs and EQs via the cache watch and cache scrub facilities has worked properly. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index d6628a09..71280002 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -43,9 +43,11 @@ #ifdef DEBUG #define XIVE_DEBUG_DUPLICATES #define XIVE_PERCPU_LOG +#define XIVE_DEBUG_INIT_CACHE_UPDATES #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG +#undef XIVE_DEBUG_INIT_CACHE_UPDATES #endif /* @@ -2892,12 +2894,57 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + if (1) { + struct xive_eq *eq_p = xive_get_eq(x_eq, + xs->eq_idx + + XIVE_EMULATION_PRIO); + struct xive_eq eq2; + + assert(eq_p); + eq2 = *eq_p; + if (memcmp(&eq, &eq2, sizeof(eq)) != 0) { + xive_err(x_eq, "EQ update mismatch idx %d\n", + xs->eq_idx); + xive_err(x_eq, "want: %08x %08x %08x %08x\n", + eq.w0, eq.w1, eq.w2, eq.w3); + xive_err(x_eq, " %08x %08x %08x %08x\n", + eq.w4, eq.w5, eq.w6, eq.w7); + xive_err(x_eq, "got : %08x %08x %08x %08x\n", + eq2.w0, eq2.w1, eq2.w2, eq2.w3); + xive_err(x_eq, " %08x %08x %08x %08x\n", + eq2.w4, eq2.w5, eq2.w6, eq2.w7); + } + } +#endif /* Initialize/enable the VP */ xive_init_default_vp(&vp, xs->eq_blk, xs->eq_idx); /* Use the cache watch to write it out */ xive_vpc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, 0, 8, &vp, false, true); + + /* Debug code */ +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + if (1) { + struct xive_vp *vp_p = xive_get_vp(x_vp, xs->vp_idx); + struct xive_vp vp2; + + assert(vp_p); + vp2 = *vp_p; + if (memcmp(&vp, &vp2, sizeof(vp)) != 0) { + xive_err(x_vp, "VP update mismatch idx %d\n", xs->vp_idx); + xive_err(x_vp, "want: %08x %08x %08x %08x\n", + vp.w0, vp.w1, vp.w2, vp.w3); + xive_err(x_vp, " %08x %08x %08x %08x\n", + vp.w4, vp.w5, vp.w6, vp.w7); + xive_err(x_vp, "got : %08x %08x %08x %08x\n", + vp2.w0, vp2.w1, vp2.w2, vp2.w3); + xive_err(x_vp, " %08x %08x %08x %08x\n", + vp2.w4, vp2.w5, vp2.w6, vp2.w7); + } + } +#endif } static void xive_init_cpu_emulation(struct xive_cpu_state *xs, From patchwork Sat Sep 9 07:05:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 811917 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xq4x76cXwz9sBW for ; Sat, 9 Sep 2017 17:06:35 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xq4x75VCWzDrnw for ; Sat, 9 Sep 2017 17:06:35 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xq4wP4tB5zDrcf for ; Sat, 9 Sep 2017 17:05:57 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8975TdW025373; Sat, 9 Sep 2017 02:05:42 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 9 Sep 2017 17:05:23 +1000 Message-Id: <20170909070525.8154-5-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170909070525.8154-1-benh@kernel.crashing.org> References: <20170909070525.8154-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 5/7] xive: Make assertion in xive_eq_for_target() more informative X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" If this fails, print a bit more info about it. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index 71280002..4f08e655 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -2226,7 +2226,11 @@ static inline bool xive_eq_for_target(uint32_t target, uint8_t prio, eq_idx = vp->w1 & 0x0fffffff; /* Currently the EQ block and VP block should be the same */ - assert(eq_blk == vp_blk); + if (eq_blk != vp_blk) { + xive_err(x, "eq_blk != vp_blk (%d vs. %d) for target 0x%08x/%d\n", + eq_blk, vp_blk, target, prio); + assert(false); + } if (out_eq_blk) *out_eq_blk = eq_blk; From patchwork Sat Sep 9 07:05:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 811916 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xq4wn6x2fz9sBW for ; Sat, 9 Sep 2017 17:06:17 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xq4wn13dRzDrnj for ; Sat, 9 Sep 2017 17:06:17 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xq4wP5GcyzDrcg for ; Sat, 9 Sep 2017 17:05:57 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8975TdX025373; Sat, 9 Sep 2017 02:05:44 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 9 Sep 2017 17:05:24 +1000 Message-Id: <20170909070525.8154-6-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170909070525.8154-1-benh@kernel.crashing.org> References: <20170909070525.8154-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 6/7] xive: Add exerciser for cache watch/scrub facility in DEBUG builds X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This runs 1000 iterations exercising the cache watch and scrub facilities on VPs and ENDs at boot. This exposes a HW bug with the scrub which will be worked around in a subsequent patch. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 125 ++++++++++++++++++++++++++++++++++++++++---------------------- 1 file changed, 80 insertions(+), 45 deletions(-) diff --git a/hw/xive.c b/hw/xive.c index 4f08e655..d1fae1a3 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -44,10 +44,12 @@ #define XIVE_DEBUG_DUPLICATES #define XIVE_PERCPU_LOG #define XIVE_DEBUG_INIT_CACHE_UPDATES +#define XIVE_EXTRA_CHECK_INIT_CACHE #else #undef XIVE_DEBUG_DUPLICATES #undef XIVE_PERCPU_LOG #undef XIVE_DEBUG_INIT_CACHE_UPDATES +#undef XIVE_EXTRA_CHECK_INIT_CACHE #endif /* @@ -2870,6 +2872,79 @@ void xive_cpu_callin(struct cpu_thread *cpu) in_be64(xs->tm_ring1 + TM_QW3_HV_PHYS)); } +static bool xive_check_eq_update(struct xive *x, uint32_t idx, struct xive_eq *eq) +{ +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + struct xive_eq *eq_p = xive_get_eq(x, idx); + struct xive_eq eq2; + + assert(eq_p); + eq2 = *eq_p; + if (memcmp(eq, &eq2, sizeof(eq)) != 0) { + xive_err(x, "EQ update mismatch idx %d\n", idx); + xive_err(x, "want: %08x %08x %08x %08x\n", + eq->w0, eq->w1, eq->w2, eq->w3); + xive_err(x, " %08x %08x %08x %08x\n", + eq->w4, eq->w5, eq->w6, eq->w7); + xive_err(x, "got : %08x %08x %08x %08x\n", + eq2.w0, eq2.w1, eq2.w2, eq2.w3); + xive_err(x, " %08x %08x %08x %08x\n", + eq2.w4, eq2.w5, eq2.w6, eq2.w7); + return false; + } +#endif + return true; +} + +static bool xive_check_vpc_update(struct xive *x, uint32_t idx, struct xive_vp *vp) +{ +#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES + struct xive_vp *vp_p = xive_get_vp(x, idx); + struct xive_vp vp2; + + assert(vp_p); + vp2 = *vp_p; + if (memcmp(vp, &vp2, sizeof(vp)) != 0) { + xive_err(x, "VP update mismatch idx %d\n", idx); + xive_err(x, "want: %08x %08x %08x %08x\n", + vp->w0, vp->w1, vp->w2, vp->w3); + xive_err(x, " %08x %08x %08x %08x\n", + vp->w4, vp->w5, vp->w6, vp->w7); + xive_err(x, "got : %08x %08x %08x %08x\n", + vp2.w0, vp2.w1, vp2.w2, vp2.w3); + xive_err(x, " %08x %08x %08x %08x\n", + vp2.w4, vp2.w5, vp2.w6, vp2.w7); + return false; + } +#endif + return true; +} + +#ifdef XIVE_EXTRA_CHECK_INIT_CACHE +static void xive_special_cache_check(struct xive *x, uint32_t blk, uint32_t idx) +{ + struct xive_vp vp = {}; + uint32_t i; + + for (i = 0; i < 1000; i++) { + struct xive_vp *vp_m = xive_get_vp(x, idx); + + memset(vp_m, (~i) & 0xff, sizeof(*vp_m)); + sync(); + vp.w1 = (i << 16) | i; + xive_vpc_cache_update(x, blk, idx, + 0, 8, &vp, false, true); + if (!xive_check_vpc_update(x, idx, &vp)) { + xive_dbg(x, "Test failed at %d iterations\n", i); + return; + } + } + xive_dbg(x, "1000 iterations test success at %d/0x%x\n", blk, idx); +} +#else +static inline void xive_special_cache_check(struct xive *x, uint32_t blk, uint32_t idx) { } +#endif + static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) { struct xive_eq eq; @@ -2897,58 +2972,18 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) xive_eqc_cache_update(x_eq, xs->eq_blk, xs->eq_idx + XIVE_EMULATION_PRIO, 0, 4, &eq, false, true); + xive_check_eq_update(x_eq, xs->eq_idx + XIVE_EMULATION_PRIO, &eq); + + /* Extra testing of cache watch & scrub facilities */ + xive_special_cache_check(x_vp, xs->vp_blk, xs->vp_idx); -#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES - if (1) { - struct xive_eq *eq_p = xive_get_eq(x_eq, - xs->eq_idx + - XIVE_EMULATION_PRIO); - struct xive_eq eq2; - - assert(eq_p); - eq2 = *eq_p; - if (memcmp(&eq, &eq2, sizeof(eq)) != 0) { - xive_err(x_eq, "EQ update mismatch idx %d\n", - xs->eq_idx); - xive_err(x_eq, "want: %08x %08x %08x %08x\n", - eq.w0, eq.w1, eq.w2, eq.w3); - xive_err(x_eq, " %08x %08x %08x %08x\n", - eq.w4, eq.w5, eq.w6, eq.w7); - xive_err(x_eq, "got : %08x %08x %08x %08x\n", - eq2.w0, eq2.w1, eq2.w2, eq2.w3); - xive_err(x_eq, " %08x %08x %08x %08x\n", - eq2.w4, eq2.w5, eq2.w6, eq2.w7); - } - } -#endif /* Initialize/enable the VP */ xive_init_default_vp(&vp, xs->eq_blk, xs->eq_idx); /* Use the cache watch to write it out */ xive_vpc_cache_update(x_vp, xs->vp_blk, xs->vp_idx, 0, 8, &vp, false, true); - - /* Debug code */ -#ifdef XIVE_DEBUG_INIT_CACHE_UPDATES - if (1) { - struct xive_vp *vp_p = xive_get_vp(x_vp, xs->vp_idx); - struct xive_vp vp2; - - assert(vp_p); - vp2 = *vp_p; - if (memcmp(&vp, &vp2, sizeof(vp)) != 0) { - xive_err(x_vp, "VP update mismatch idx %d\n", xs->vp_idx); - xive_err(x_vp, "want: %08x %08x %08x %08x\n", - vp.w0, vp.w1, vp.w2, vp.w3); - xive_err(x_vp, " %08x %08x %08x %08x\n", - vp.w4, vp.w5, vp.w6, vp.w7); - xive_err(x_vp, "got : %08x %08x %08x %08x\n", - vp2.w0, vp2.w1, vp2.w2, vp2.w3); - xive_err(x_vp, " %08x %08x %08x %08x\n", - vp2.w4, vp2.w5, vp2.w6, vp2.w7); - } - } -#endif + xive_check_vpc_update(x_vp, xs->vp_idx, &vp); } static void xive_init_cpu_emulation(struct xive_cpu_state *xs, From patchwork Sat Sep 9 07:05:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 811918 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3xq4xC1RNkz9sBW for ; Sat, 9 Sep 2017 17:06:39 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3xq4xC0dNTzDrpF for ; Sat, 9 Sep 2017 17:06:39 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3xq4wR68TyzDrcg for ; Sat, 9 Sep 2017 17:05:59 +1000 (AEST) Received: from pasglop.au.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8975TdY025373; Sat, 9 Sep 2017 02:05:46 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Sat, 9 Sep 2017 17:05:25 +1000 Message-Id: <20170909070525.8154-7-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170909070525.8154-1-benh@kernel.crashing.org> References: <20170909070525.8154-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 7/7] xive: Workaround HW issue with scrub facility X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Without this, we sometimes don't observe from a CPU the values written to the ENDs or NVTs via the cache watch. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/hw/xive.c b/hw/xive.c index d1fae1a3..a81d2b8e 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1232,6 +1232,12 @@ enum xive_cache_type { xive_cache_vpc, }; +static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, + uint64_t block, uint64_t idx, + uint32_t start_dword, uint32_t dword_count, + void *new_data, bool light_watch, + bool synchronous); + static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, uint64_t block, uint64_t idx, bool want_inval, bool want_disable) @@ -1239,6 +1245,17 @@ static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, uint64_t sreg, sregx, mreg, mregx; uint64_t mval, sval; + /* Workaround a HW bug in XIVE where the scrub completion + * isn't ordered by loads, thus the data might still be + * in a queue and may not have reached coherency. + * + * The workaround is two folds: We force the scrub to also + * invalidate, then after the scrub, we do a dummy cache + * watch which will make the HW read the data back, which + * should be ordered behind all the preceding stores. + */ + want_inval = true; + switch (ctype) { case xive_cache_ivc: sreg = VC_IVC_SCRUB_TRIG; @@ -1293,6 +1310,9 @@ static int64_t __xive_cache_scrub(struct xive *x, enum xive_cache_type ctype, time_wait(100); } sync(); + + /* Workaround for HW bug described above */ + __xive_cache_watch(x, ctype, block, idx, 0, 0, NULL, true, false); return 0; } @@ -1304,7 +1324,6 @@ static int64_t xive_ivc_scrub(struct xive *x, uint64_t block, uint64_t idx) static int64_t xive_vpc_scrub_clean(struct xive *x, uint64_t block, uint64_t idx) { - /* IVC has no "want_inval" bit, it always invalidates */ return __xive_cache_scrub(x, xive_cache_vpc, block, idx, true, false); } @@ -1348,6 +1367,14 @@ static int64_t __xive_cache_watch(struct xive *x, enum xive_cache_type ctype, /* Load data0 register to populate the watch */ dval0 = __xive_regr(x, dreg0, dreg0x, NULL); + /* If new_data is NULL, this is a dummy watch used as a + * workaround for a HW bug + */ + if (!new_data) { + __xive_regw(x, dreg0, dreg0x, dval0, NULL); + return 0; + } + /* Write the words into the watch facility. We write in reverse * order in case word 0 is part of it as it must be the last * one written.