From patchwork Fri Feb 26 09:11:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 1444844 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Dn3pv1cFcz9sTD for ; Fri, 26 Feb 2021 20:13:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230228AbhBZJMz (ORCPT ); Fri, 26 Feb 2021 04:12:55 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:54090 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbhBZJMX (ORCPT ); Fri, 26 Feb 2021 04:12:23 -0500 Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:4cb:a870:297a:447b:deb4:3f5c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 2E5461F464C9; Fri, 26 Feb 2021 09:11:37 +0000 (GMT) From: Benjamin Gaignard To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org, kernel@collabora.com, benjamin.gaignard@collabora.com Subject: [PATCH v2 1/5] dt-bindings: reset: IMX8MQ VPU reset Date: Fri, 26 Feb 2021 10:11:24 +0100 Message-Id: <20210226091128.14379-2-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210226091128.14379-1-benjamin.gaignard@collabora.com> References: <20210226091128.14379-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document bindings for IMX8MQ VPU reset hardware block Signed-off-by: Benjamin Gaignard --- .../bindings/reset/fsl,imx8mq-vpu-reset.yaml | 54 +++++++++++++++++++ include/dt-bindings/reset/imx8mq-vpu-reset.h | 16 ++++++ 2 files changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml create mode 100644 include/dt-bindings/reset/imx8mq-vpu-reset.h diff --git a/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml new file mode 100644 index 000000000000..00020421c0e3 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/fsl,imx8mq-vpu-reset.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/fsl,imx8mq-vpu-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MQ VPU Reset Controller + +maintainers: + - Benjamin Gaignard + +description: | + The VPU reset controller is used to reset the video processor + unit peripherals. Device nodes that need access to reset lines should + specify them as a reset phandle in their corresponding node as + specified in reset.txt. + + For list of all valid reset indices see + for i.MX8MQ. + +properties: + compatible: + items: + - const: fsl,imx8mq-vpu-reset + - const: syscon + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + vpu-reset@38320000 { + compatible = "fsl,imx8mq-vpu-reset", "syscon"; + reg = <0x38320000 0x10000>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/imx8mq-vpu-reset.h b/include/dt-bindings/reset/imx8mq-vpu-reset.h new file mode 100644 index 000000000000..efcbe18177fe --- /dev/null +++ b/include/dt-bindings/reset/imx8mq-vpu-reset.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, Collabora + * + * i.MX7 System Reset Controller (SRC) driver + * + * Author: Benjamin Gaignard + */ + +#ifndef DT_BINDINGS_VPU_RESET_IMX8MQ +#define DT_BINDINGS_VPU_RESET_IMX8MQ + +#define IMX8MQ_RESET_VPU_RESET_G1 0 +#define IMX8MQ_RESET_VPU_RESET_G2 1 + +#endif From patchwork Fri Feb 26 09:11:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 1444845 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Dn3pv4W6Lz9sRR for ; Fri, 26 Feb 2021 20:13:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbhBZJNA (ORCPT ); Fri, 26 Feb 2021 04:13:00 -0500 Received: from bhuna.collabora.co.uk ([46.235.227.227]:54106 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230107AbhBZJMX (ORCPT ); Fri, 26 Feb 2021 04:12:23 -0500 Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:4cb:a870:297a:447b:deb4:3f5c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 21EB51F464CA; Fri, 26 Feb 2021 09:11:38 +0000 (GMT) From: Benjamin Gaignard To: p.zabel@pengutronix.de, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, ezequiel@collabora.com, mchehab@kernel.org, gregkh@linuxfoundation.org Cc: kernel@pengutronix.de, linux-imx@nxp.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devel@driverdev.osuosl.org, kernel@collabora.com, benjamin.gaignard@collabora.com Subject: [PATCH v2 2/5] dt-bindings: media: IMX8MQ VPU: document reset usage Date: Fri, 26 Feb 2021 10:11:25 +0100 Message-Id: <20210226091128.14379-3-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210226091128.14379-1-benjamin.gaignard@collabora.com> References: <20210226091128.14379-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document IMX8MQ VPU bindings to add the phandle to the reset driver. Provide an independent reset driver allow to the both VPUs to share their control/reset hardware block. The reset driver replace what was previously done be using the 'ctrl' registers inside the driver. This breaks the compatibility between DTB and kernel but the driver is still in staging directory and limited to IMX8MQ SoC. Signed-off-by: Benjamin Gaignard --- .../devicetree/bindings/media/nxp,imx8mq-vpu.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index 762be3f96ce9..c860f6b201f9 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -18,13 +18,12 @@ properties: const: nxp,imx8mq-vpu reg: - maxItems: 3 + maxItems: 2 reg-names: items: - const: g1 - const: g2 - - const: ctrl interrupts: maxItems: 2 @@ -46,6 +45,9 @@ properties: power-domains: maxItems: 1 + resets: + maxItems: 1 + required: - compatible - reg @@ -54,6 +56,7 @@ required: - interrupt-names - clocks - clock-names + - resets additionalProperties: false @@ -61,13 +64,14 @@ examples: - | #include #include + #include vpu: video-codec@38300000 { compatible = "nxp,imx8mq-vpu"; reg = <0x38300000 0x10000>, <0x38310000 0x10000>, <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; + reg-names = "g1", "g2"; interrupts = , ; interrupt-names = "g1", "g2"; @@ -76,4 +80,5 @@ examples: <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; clock-names = "g1", "g2", "bus"; power-domains = <&pgc_vpu>; + resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>; };