From patchwork Tue Feb 23 20:46:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443624 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWLt6DYQz9sVX for ; Wed, 24 Feb 2021 07:47:02 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B56A282A89; Tue, 23 Feb 2021 21:46:59 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 143B582A86; Tue, 23 Feb 2021 21:46:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs49.siol.net [185.57.226.240]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E85C182A80 for ; Tue, 23 Feb 2021 21:46:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 8CDD252454D; Tue, 23 Feb 2021 21:46:43 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id knQeWxlcHnzz; Tue, 23 Feb 2021 21:46:43 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 4C6B0524384; Tue, 23 Feb 2021 21:46:43 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 01B0A52454D; Tue, 23 Feb 2021 21:46:40 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 01/19] sunxi: video: select dw-hdmi in Kconfig, not Makefile Date: Tue, 23 Feb 2021 21:46:13 +0100 Message-Id: <20210223204631.1609597-2-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently sunxi Makefile manually specifies full path to dw-hdmi common code. However, that is not needed because it can be selected in Kconfig instead. Select proper symbol in Kconfig and drop path from Makefile. Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/video/sunxi/Makefile | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 0135575ca1eb..9149196b223e 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -972,6 +972,7 @@ config VIDEO_DE2 depends on SUNXI_DE2 select DM_VIDEO select DISPLAY + select VIDEO_DW_HDMI imply VIDEO_DT_SIMPLEFB default y ---help--- diff --git a/drivers/video/sunxi/Makefile b/drivers/video/sunxi/Makefile index 147e18799229..4321673312bf 100644 --- a/drivers/video/sunxi/Makefile +++ b/drivers/video/sunxi/Makefile @@ -4,4 +4,4 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o simplefb_common.o lcdc.o tve_common.o ../videomodes.o -obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o ../dw_hdmi.o sunxi_lcd.o +obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o simplefb_common.o lcdc.o sunxi_lcd.o From patchwork Tue Feb 23 20:46:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443625 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWM95JFpz9sVX for ; Wed, 24 Feb 2021 07:47:17 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 0D97B82A9D; Tue, 23 Feb 2021 21:47:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 4BD9982A8C; Tue, 23 Feb 2021 21:46:50 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs27.siol.net [185.57.226.218]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 35EE582A81 for ; Tue, 23 Feb 2021 21:46:46 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id D29515244B9; Tue, 23 Feb 2021 21:46:45 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id ufPr3CsVa33a; Tue, 23 Feb 2021 21:46:45 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 9A3D25244B5; Tue, 23 Feb 2021 21:46:45 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 63F755244B9; Tue, 23 Feb 2021 21:46:43 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 02/19] video: sunxi: Add mode_valid callback to sunxi_dw_hdmi Date: Tue, 23 Feb 2021 21:46:14 +0100 Message-Id: <20210223204631.1609597-3-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently driver accepts all resolution which won't work on 4k screens. Add validation callback which limits acceptable resolutions to 297 MHz. Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara --- drivers/video/sunxi/sunxi_dw_hdmi.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0b8cefc311ef..e3811a2ec15f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -305,6 +305,12 @@ static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); } +static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev, + const struct display_timing *timing) +{ + return timing->pixelclock.typ <= 297000000; +} + static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { @@ -388,6 +394,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) static const struct dm_display_ops sunxi_dw_hdmi_ops = { .read_edid = sunxi_dw_hdmi_read_edid, .enable = sunxi_dw_hdmi_enable, + .mode_valid = sunxi_dw_hdmi_mode_valid, }; U_BOOT_DRIVER(sunxi_dw_hdmi) = { From patchwork Tue Feb 23 20:46:15 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443626 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWMP3cffz9sVX for ; Wed, 24 Feb 2021 07:47:29 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7C91782A7F; Tue, 23 Feb 2021 21:47:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id D210182A8C; Tue, 23 Feb 2021 21:46:53 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs44.siol.net [185.57.226.235]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 7599982A89 for ; Tue, 23 Feb 2021 21:46:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 1282F52454D; Tue, 23 Feb 2021 21:46:48 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id HTEmawaGkXIM; Tue, 23 Feb 2021 21:46:47 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id D0B675244B5; Tue, 23 Feb 2021 21:46:47 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 9FE7752454D; Tue, 23 Feb 2021 21:46:45 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 03/19] common: edid: check for digital display earlier Date: Tue, 23 Feb 2021 21:46:15 +0100 Message-Id: <20210223204631.1609597-4-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean When searching for detailed timing in EDID, check for digital display earlier. There is no point parsing other parameters if this flag is not present. Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara --- common/edid.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/common/edid.c b/common/edid.c index 553ab8fd01a1..1cb7177742e8 100644 --- a/common/edid.c +++ b/common/edid.c @@ -185,6 +185,11 @@ int edid_get_timing_validate(u8 *buf, int buf_size, return -EINVAL; } + if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { + debug("%s: Not a digital display\n", __func__); + return -ENOSYS; + } + if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { debug("%s: No preferred timing\n", __func__); return -ENOENT; @@ -211,10 +216,6 @@ int edid_get_timing_validate(u8 *buf, int buf_size, if (!timing_done) return -EINVAL; - if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { - debug("%s: Not a digital display\n", __func__); - return -ENOSYS; - } if (edid->version != 1 || edid->revision < 4) { debug("%s: EDID version %d.%d does not have required info\n", __func__, edid->version, edid->revision); From patchwork Tue Feb 23 20:46:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443627 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWMd2lHSz9sVX for ; Wed, 24 Feb 2021 07:47:41 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1CE3E82ABE; Tue, 23 Feb 2021 21:47:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 47AF182A98; Tue, 23 Feb 2021 21:46:56 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs44.siol.net [185.57.226.235]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9BE7F82A81 for ; Tue, 23 Feb 2021 21:46:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 51C5A5244B9; Tue, 23 Feb 2021 21:46:50 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id EcOx_kZYrBrs; Tue, 23 Feb 2021 21:46:50 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 1373652454D; Tue, 23 Feb 2021 21:46:50 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id D6A135244B9; Tue, 23 Feb 2021 21:46:47 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 04/19] common: edid: extract code for detailed timing search Date: Tue, 23 Feb 2021 21:46:16 +0100 Message-Id: <20210223204631.1609597-5-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Code which searches for valid detailed timing entry will be used in more places. Extract it. Signed-off-by: Jernej Skrabec --- common/edid.c | 49 ++++++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/common/edid.c b/common/edid.c index 1cb7177742e8..a6c875d9c8e8 100644 --- a/common/edid.c +++ b/common/edid.c @@ -169,6 +169,29 @@ static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) return false; } +static bool edid_find_valid_timing(void *buf, int count, + struct display_timing *timing, + bool (*mode_valid)(void *priv, + const struct display_timing *timing), + void *mode_valid_priv) +{ + struct edid_detailed_timing *t = buf; + bool found = false; + int i; + + for (i = 0; i < count && !found; i++, t++) + if (EDID_DETAILED_TIMING_PIXEL_CLOCK(*t) != 0) { + decode_timing((u8 *)t, timing); + if (mode_valid) + found = mode_valid(mode_valid_priv, + timing); + else + found = true; + } + + return found; +} + int edid_get_timing_validate(u8 *buf, int buf_size, struct display_timing *timing, int *panel_bits_per_colourp, @@ -177,8 +200,7 @@ int edid_get_timing_validate(u8 *buf, int buf_size, void *mode_valid_priv) { struct edid1_info *edid = (struct edid1_info *)buf; - bool timing_done; - int i; + bool found; if (buf_size < sizeof(*edid) || edid_check_info(edid)) { debug("%s: Invalid buffer\n", __func__); @@ -195,25 +217,10 @@ int edid_get_timing_validate(u8 *buf, int buf_size, return -ENOENT; } - /* Look for detailed timing */ - timing_done = false; - for (i = 0; i < 4; i++) { - struct edid_monitor_descriptor *desc; - - desc = &edid->monitor_details.descriptor[i]; - if (desc->zero_flag_1 != 0) { - decode_timing((u8 *)desc, timing); - if (mode_valid) - timing_done = mode_valid(mode_valid_priv, - timing); - else - timing_done = true; - - if (timing_done) - break; - } - } - if (!timing_done) + /* Look for detailed timing in base EDID */ + found = edid_find_valid_timing(edid->monitor_details.descriptor, 4, + timing, mode_valid, mode_valid_priv); + if (!found) return -EINVAL; if (edid->version != 1 || edid->revision < 4) { From patchwork Tue Feb 23 20:46:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443629 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWN64lKzz9sVX for ; Wed, 24 Feb 2021 07:48:06 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BB3F982A5E; Tue, 23 Feb 2021 21:47:48 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 613DE82A96; Tue, 23 Feb 2021 21:47:03 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs36.siol.net [185.57.226.227]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 74AB282A81 for ; Tue, 23 Feb 2021 21:46:58 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 1A75652454D; Tue, 23 Feb 2021 21:46:58 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id KstDBWr-RxZT; Tue, 23 Feb 2021 21:46:57 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id D4458524384; Tue, 23 Feb 2021 21:46:57 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 1943B524558; Tue, 23 Feb 2021 21:46:50 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 05/19] common: edid: Search for valid timing in extension block Date: Tue, 23 Feb 2021 21:46:17 +0100 Message-Id: <20210223204631.1609597-6-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean One of my monitors have only 4k@60 timing in base EDID block which is out of range for devices with HDMI 1.4. It turns out that it has additional detailed timings in CTA-861 Extension Block and two of them are appropriate for HDMI 1.4. Add additional search for valid detailed timing in extension block. Signed-off-by: Jernej Skrabec --- common/edid.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/common/edid.c b/common/edid.c index a6c875d9c8e8..14d8836c360e 100644 --- a/common/edid.c +++ b/common/edid.c @@ -220,6 +220,24 @@ int edid_get_timing_validate(u8 *buf, int buf_size, /* Look for detailed timing in base EDID */ found = edid_find_valid_timing(edid->monitor_details.descriptor, 4, timing, mode_valid, mode_valid_priv); + + /* Look for detailed timing in CTA-861 Extension Block */ + if (!found && edid->extension_flag && buf_size >= EDID_EXT_SIZE) { + struct edid_cea861_info *info = + (struct edid_cea861_info *)(buf + sizeof(*edid)); + + if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) { + int count = EDID_CEA861_DTD_COUNT(*info); + int offset = info->dtd_offset; + int size = count * sizeof(struct edid_detailed_timing); + + if (offset >= 4 && offset + size < EDID_SIZE) + found = edid_find_valid_timing( + (u8*)info + offset, count, timing, + mode_valid, mode_valid_priv); + } + } + if (!found) return -EINVAL; From patchwork Tue Feb 23 20:46:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443630 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWNM464zz9sVX for ; Wed, 24 Feb 2021 07:48:19 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9002E82A92; Tue, 23 Feb 2021 21:47:52 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8C6FB82AA3; Tue, 23 Feb 2021 21:47:08 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs5.siol.net [185.57.226.196]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A2E1E82A8D for ; Tue, 23 Feb 2021 21:47:00 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 4F3DD5244B5; Tue, 23 Feb 2021 21:47:00 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id V2NIODpE9AR2; Tue, 23 Feb 2021 21:47:00 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 150A8524384; Tue, 23 Feb 2021 21:47:00 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id D9BCE5244B5; Tue, 23 Feb 2021 21:46:57 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 06/19] video: sunxi: Use DW-HDMI hpd function Date: Tue, 23 Feb 2021 21:46:18 +0100 Message-Id: <20210223204631.1609597-7-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It turns out that even though A64, H3 and H5 have custom PHY, standard hot plug detection for DW-HDMI works just fine. Remove custom hpd method to reduce amount of custom code. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_dw_hdmi.c | 34 +++++------------------------ 1 file changed, 6 insertions(+), 28 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index e3811a2ec15f..37e78ff24111 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -114,28 +114,6 @@ static void sunxi_dw_hdmi_phy_init(void) writel(0x42494E47, &phy->unscramble); } -static int sunxi_dw_hdmi_get_plug_in_status(void) -{ - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); - - return !!(readl(&phy->status) & (1 << 19)); -} - -static int sunxi_dw_hdmi_wait_for_hpd(void) -{ - ulong start; - - start = get_timer(0); - do { - if (sunxi_dw_hdmi_get_plug_in_status()) - return 0; - udelay(100); - } while (get_timer(start) < 300); - - return -1; -} - static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) { struct sunxi_hdmi_phy * const phy = @@ -370,12 +348,6 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) sunxi_dw_hdmi_phy_init(); - ret = sunxi_dw_hdmi_wait_for_hpd(); - if (ret < 0) { - debug("hdmi can not get hpd signal\n"); - return -1; - } - priv->hdmi.ioaddr = SUNXI_HDMI_BASE; priv->hdmi.i2c_clk_high = 0xd8; priv->hdmi.i2c_clk_low = 0xfe; @@ -383,6 +355,12 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; priv->mux = uc_plat->source_id; + ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); + if (ret < 0) { + debug("hdmi can not get hpd signal\n"); + return -1; + } + uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", &priv->hdmi.ddc_bus); From patchwork Tue Feb 23 20:46:19 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443628 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWMt4Xndz9sVX for ; Wed, 24 Feb 2021 07:47:54 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7269082A85; Tue, 23 Feb 2021 21:47:45 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id ED09282AA5; Tue, 23 Feb 2021 21:47:09 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs17.siol.net [185.57.226.208]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DF59582A97 for ; Tue, 23 Feb 2021 21:47:02 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 7DA5552454D; Tue, 23 Feb 2021 21:47:02 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id H1dGpkZ2h3V3; Tue, 23 Feb 2021 21:47:02 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 4AA1B5244B5; Tue, 23 Feb 2021 21:47:02 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 1B68C52454D; Tue, 23 Feb 2021 21:47:00 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 07/19] video: sunxi: Remove check for ddc-i2c-bus property Date: Tue, 23 Feb 2021 21:46:19 +0100 Message-Id: <20210223204631.1609597-8-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean No Allwinner boards with DW-HDMI controller use separate I2C bus for EDID read. Remove that check. Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara --- drivers/video/sunxi/sunxi_dw_hdmi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 37e78ff24111..6d2bc206fc2c 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -361,9 +361,6 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) return -1; } - uclass_get_device_by_phandle(UCLASS_I2C, dev, "ddc-i2c-bus", - &priv->hdmi.ddc_bus); - dw_hdmi_init(&priv->hdmi); return 0; From patchwork Tue Feb 23 20:46:20 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443631 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWNd2mDYz9sVr for ; Wed, 24 Feb 2021 07:48:33 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9BD5F82AA5; Tue, 23 Feb 2021 21:47:56 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id DBACF82A87; Tue, 23 Feb 2021 21:47:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs31.siol.net [185.57.226.222]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1E5FD82A98 for ; Tue, 23 Feb 2021 21:47:05 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id B479D5244B9; Tue, 23 Feb 2021 21:47:04 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id iHt2pdZtBJ4Q; Tue, 23 Feb 2021 21:47:04 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 81AC75244B5; Tue, 23 Feb 2021 21:47:04 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 50CE35244B9; Tue, 23 Feb 2021 21:47:02 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 08/19] video: sunxi: Remove TV probe from DE2 Date: Tue, 23 Feb 2021 21:46:20 +0100 Message-Id: <20210223204631.1609597-9-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean TV driver was never fully implemented. Remove search for it from DE2 driver. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_de2.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index a3e21aa5f13e..6b836a011944 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -281,20 +281,7 @@ static int sunxi_de2_probe(struct udevice *dev) debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_tve", &disp); - if (ret) { - debug("%s: tv not found (ret=%d)\n", __func__, ret); - return ret; - } - - ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true); - if (ret) - return ret; - - video_set_flush_dcache(dev, 1); - - return 0; + return -ENODEV; } static int sunxi_de2_bind(struct udevice *dev) From patchwork Tue Feb 23 20:46:21 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443636 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWPn1YMkz9sVX for ; Wed, 24 Feb 2021 07:49:33 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EE58482AC4; Tue, 23 Feb 2021 21:48:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 9447782AA5; Tue, 23 Feb 2021 21:47:19 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs33.siol.net [185.57.226.224]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id CFC0A82AA2 for ; Tue, 23 Feb 2021 21:47:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 095F452454D; Tue, 23 Feb 2021 21:47:07 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id 5n6UEYlLgnuu; Tue, 23 Feb 2021 21:47:06 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id B69735244B5; Tue, 23 Feb 2021 21:47:06 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 87FA9524556; Tue, 23 Feb 2021 21:47:04 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 09/19] video: sunxi: de2: switch to public uclass functions Date: Tue, 23 Feb 2021 21:46:21 +0100 Message-Id: <20210223204631.1609597-10-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently DE2 driver uses functions which are defined in -internal header. They are not meant to be used outside of uclass framework. Switch DE2 driver to public ones. This has additional benefit that device_probe doesn't need to be called manually. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_de2.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 6b836a011944..e02d359cd259 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -19,8 +19,6 @@ #include #include #include -#include -#include #include #include "simplefb_common.h" @@ -198,13 +196,6 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, disp_uc_plat->source_id = mux; - ret = device_probe(disp); - if (ret) { - debug("%s: device '%s' display won't probe (ret=%d)\n", - __func__, dev->name, ret); - return ret; - } - ret = display_read_timing(disp, &timing); if (ret) { debug("%s: Failed to read timings\n", __func__); @@ -245,8 +236,8 @@ static int sunxi_de2_probe(struct udevice *dev) if (!(gd->flags & GD_FLG_RELOC)) return 0; - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_lcd", &disp); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_lcd), &disp); if (!ret) { int mux; @@ -262,8 +253,8 @@ static int sunxi_de2_probe(struct udevice *dev) debug("%s: lcd display not found (ret=%d)\n", __func__, ret); - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_dw_hdmi", &disp); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_dw_hdmi), &disp); if (!ret) { int mux; if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) @@ -332,8 +323,8 @@ int sunxi_simplefb_setup(void *blob) mux = 1; /* Skip simplefb setting if DE2 / HDMI is not present */ - ret = uclass_find_device_by_name(UCLASS_VIDEO, - "sunxi_de2", &de2); + ret = uclass_get_device_by_driver(UCLASS_VIDEO, + DM_DRIVER_GET(sunxi_de2), &de2); if (ret) { debug("DE2 not present\n"); return 0; @@ -342,8 +333,8 @@ int sunxi_simplefb_setup(void *blob) return 0; } - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_dw_hdmi", &hdmi); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_dw_hdmi), &hdmi); if (ret) { debug("HDMI not present\n"); } else if (device_active(hdmi)) { @@ -355,8 +346,8 @@ int sunxi_simplefb_setup(void *blob) debug("HDMI present but not probed\n"); } - ret = uclass_find_device_by_name(UCLASS_DISPLAY, - "sunxi_lcd", &lcd); + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_DRIVER_GET(sunxi_lcd), &lcd); if (ret) debug("LCD not present\n"); else if (device_active(lcd)) From patchwork Tue Feb 23 20:46:22 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443633 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWP722Qbz9sVw for ; Wed, 24 Feb 2021 07:48:59 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 37F2D82AB2; Tue, 23 Feb 2021 21:48:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 5A11B82A8D; Tue, 23 Feb 2021 21:47:24 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs44.siol.net [185.57.226.235]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 8FC0082AA3 for ; Tue, 23 Feb 2021 21:47:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 33F335244B9; Tue, 23 Feb 2021 21:47:09 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id m3D_HMU3yTJ1; Tue, 23 Feb 2021 21:47:09 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id EF2B0524556; Tue, 23 Feb 2021 21:47:08 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id BC5AE5244B9; Tue, 23 Feb 2021 21:47:06 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 10/19] video: sunxi: dw-hdmi: probe driver by compatible Date: Tue, 23 Feb 2021 21:46:22 +0100 Message-Id: <20210223204631.1609597-11-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently sunxi dw-hdmi driver is probed unconditionally, even if there is no such device. Switch driver to probing via compatible string. This brings many benefits - driver can read DT node and allows driver to be always enabled. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_dw_hdmi.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 6d2bc206fc2c..6f77b2a43b40 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -372,14 +372,16 @@ static const struct dm_display_ops sunxi_dw_hdmi_ops = { .mode_valid = sunxi_dw_hdmi_mode_valid, }; +static const struct udevice_id sunxi_dw_hdmi_ids[] = { + { .compatible = "allwinner,sun8i-a83t-dw-hdmi" }, + { } +}; + U_BOOT_DRIVER(sunxi_dw_hdmi) = { .name = "sunxi_dw_hdmi", .id = UCLASS_DISPLAY, + .of_match = sunxi_dw_hdmi_ids, .ops = &sunxi_dw_hdmi_ops, .probe = sunxi_dw_hdmi_probe, .priv_auto = sizeof(struct sunxi_dw_hdmi_priv), }; - -U_BOOT_DRVINFO(sunxi_dw_hdmi) = { - .name = "sunxi_dw_hdmi" -}; From patchwork Tue Feb 23 20:46:23 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443634 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWPM2cylz9sVr for ; Wed, 24 Feb 2021 07:49:11 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id BA8C082ABA; Tue, 23 Feb 2021 21:48:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B0E3D82A87; Tue, 23 Feb 2021 21:47:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs27.siol.net [185.57.226.218]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D6AD982A96 for ; Tue, 23 Feb 2021 21:47:11 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 7DAD052455A; Tue, 23 Feb 2021 21:47:11 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id KQ7LaqPOtyFM; Tue, 23 Feb 2021 21:47:11 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 2EAAF524556; Tue, 23 Feb 2021 21:47:11 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id F408E524559; Tue, 23 Feb 2021 21:47:08 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 11/19] video: sunxi: dw-hdmi: read address from DT node Date: Tue, 23 Feb 2021 21:46:23 +0100 Message-Id: <20210223204631.1609597-12-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently HDMI controller MMIO address is hardcoded. Change that so address is read from DT node. That will make adding support for new variants a bit easier. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_dw_hdmi.c | 38 ++++++++++++++++++----------- 1 file changed, 24 insertions(+), 14 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 6f77b2a43b40..0744954fa15f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -57,10 +57,10 @@ static int sunxi_dw_hdmi_get_divider(uint clock) return 1; } -static void sunxi_dw_hdmi_phy_init(void) +static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) { struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); + (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); unsigned long tmo; u32 tmp; @@ -114,10 +114,10 @@ static void sunxi_dw_hdmi_phy_init(void) writel(0x42494E47, &phy->unscramble); } -static void sunxi_dw_hdmi_phy_set(uint clock, int phy_div) +static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) { struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); + (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); int div = sunxi_dw_hdmi_get_divider(clock); u32 tmp; @@ -271,7 +271,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) int phy_div; sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(mpixelclock, phy_div); + sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div); return 0; } @@ -292,9 +292,9 @@ static bool sunxi_dw_hdmi_mode_valid(struct udevice *dev, static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { - struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS); struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); + struct sunxi_hdmi_phy * const phy = + (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS); int ret; ret = dw_hdmi_enable(&priv->hdmi, edid); @@ -316,12 +316,26 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, * again or othwerwise BSP driver won't work. Dummy read is * needed or otherwise last write doesn't get written correctly. */ - (void)readb(SUNXI_HDMI_BASE); + (void)readb(priv->hdmi.ioaddr); writel(0, &phy->unscramble); return 0; } +static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) +{ + struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); + struct dw_hdmi *hdmi = &priv->hdmi; + + hdmi->ioaddr = (ulong)dev_read_addr(dev); + hdmi->i2c_clk_high = 0xd8; + hdmi->i2c_clk_low = 0xfe; + hdmi->reg_io_width = 1; + hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; + + return 0; +} + static int sunxi_dw_hdmi_probe(struct udevice *dev) { struct display_plat *uc_plat = dev_get_uclass_plat(dev); @@ -346,13 +360,8 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) /* Clock on */ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); - sunxi_dw_hdmi_phy_init(); + sunxi_dw_hdmi_phy_init(&priv->hdmi); - priv->hdmi.ioaddr = SUNXI_HDMI_BASE; - priv->hdmi.i2c_clk_high = 0xd8; - priv->hdmi.i2c_clk_low = 0xfe; - priv->hdmi.reg_io_width = 1; - priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; priv->mux = uc_plat->source_id; ret = dw_hdmi_phy_wait_for_hpd(&priv->hdmi); @@ -382,6 +391,7 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = { .id = UCLASS_DISPLAY, .of_match = sunxi_dw_hdmi_ids, .ops = &sunxi_dw_hdmi_ops, + .of_to_plat = sunxi_dw_hdmi_of_to_plat, .probe = sunxi_dw_hdmi_probe, .priv_auto = sizeof(struct sunxi_dw_hdmi_priv), }; From patchwork Tue Feb 23 20:46:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443632 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWNv4lNvz9sVX for ; Wed, 24 Feb 2021 07:48:47 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1005B82A9D; Tue, 23 Feb 2021 21:48:07 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 9397D82AAB; Tue, 23 Feb 2021 21:47:23 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs17.siol.net [185.57.226.208]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 178DA82A4C for ; Tue, 23 Feb 2021 21:47:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id C1E28524558; Tue, 23 Feb 2021 21:47:13 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id lwSbJwDbnRaW; Tue, 23 Feb 2021 21:47:13 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 73B405244B5; Tue, 23 Feb 2021 21:47:13 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 349BC524558; Tue, 23 Feb 2021 21:47:11 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Neil Armstrong Subject: [PATCH 12/19] video: dw-hdmi: modify phy init callback to include full timings Date: Tue, 23 Feb 2021 21:46:24 +0100 Message-Id: <20210223204631.1609597-13-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently PHY init callback has only pixel clock as a parameter, but other timing parameters may be needed for custom PHYs. Modify callback signature to include full timings. Cc: Neil Armstrong Signed-off-by: Jernej Skrabec --- drivers/video/dw_hdmi.c | 6 +++--- drivers/video/meson/meson_dw_hdmi.c | 5 +++-- drivers/video/sunxi/sunxi_dw_hdmi.c | 7 ++++--- include/dw_hdmi.h | 4 ++-- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index c4fbb1829446..8d71f713f99f 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -901,7 +901,7 @@ static const u8 pre_buf[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, }; -int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid) { int i, ret; @@ -912,7 +912,7 @@ int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) hdmi_phy_enable_tmds(hdmi, 0); hdmi_phy_enable_power(hdmi, 0); - ret = hdmi_phy_configure(hdmi, mpixelclock); + ret = hdmi_phy_configure(hdmi, edid->pixelclock.typ); if (ret) { debug("hdmi phy config failure %d\n", ret); return ret; @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) hdmi_av_composer(hdmi, edid); - ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); + ret = hdmi->phy_set(hdmi, edid); if (ret) return ret; diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index e5f281320534..7558814b3491 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -292,7 +292,8 @@ static void meson_dw_hdmi_phy_setup_mode(struct meson_dw_hdmi *priv, } } -static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock) +static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, + const struct display_timing *edid) { struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi, hdmi); @@ -322,7 +323,7 @@ static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock) dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); /* Setup PHY parameters */ - meson_dw_hdmi_phy_setup_mode(priv, pixel_clock); + meson_dw_hdmi_phy_setup_mode(priv, edid->pixelclock.typ); /* Setup PHY */ dw_hdmi_hhi_update_bits(priv, HHI_HDMI_PHY_CNTL1, diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0744954fa15f..483d57293155 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -266,12 +266,13 @@ static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid, lcdc_enable(lcdc, bpp); } -static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) +static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, + const struct display_timing *edid) { int phy_div; - sunxi_dw_hdmi_pll_set(mpixelclock / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(hdmi, mpixelclock, phy_div); + sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div); + sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div); return 0; } diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h index 8acae3839fb3..46b87916b8bb 100644 --- a/include/dw_hdmi.h +++ b/include/dw_hdmi.h @@ -544,12 +544,12 @@ struct dw_hdmi { struct hdmi_data_info hdmi_data; struct udevice *ddc_bus; - int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); + int (*phy_set)(struct dw_hdmi *hdmi, const struct display_timing *edid); void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); }; -int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, const struct display_timing *edid); int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); void dw_hdmi_phy_init(struct dw_hdmi *hdmi); From patchwork Tue Feb 23 20:46:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443635 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWPZ3c2Pz9sVX for ; Wed, 24 Feb 2021 07:49:22 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9914F82ABB; Tue, 23 Feb 2021 21:48:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 517A182AA3; Tue, 23 Feb 2021 21:47:25 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs27.siol.net [185.57.226.218]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 576F582AB1 for ; Tue, 23 Feb 2021 21:47:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id E75FE52454D; Tue, 23 Feb 2021 21:47:15 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id vP8o9a5YCbu5; Tue, 23 Feb 2021 21:47:15 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id A894C5244B9; Tue, 23 Feb 2021 21:47:15 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 79E0B524556; Tue, 23 Feb 2021 21:47:13 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 13/19] video: sunxi: dw-hdmi: move PHY config to appropriate place Date: Tue, 23 Feb 2021 21:46:25 +0100 Message-Id: <20210223204631.1609597-14-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently sunxi_dw_hdmi_enable() configures PHY timing related parameters. However, sunxi_dw_hdmi_phy_cfg() is better suited place for that. Move the code there. This also allows to easier driver expansion when controller uses different PHY than currently supported (like that in H6). Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_dw_hdmi.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 483d57293155..4cc175d714ea 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -114,11 +114,13 @@ static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) writel(0x42494E47, &phy->unscramble); } -static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) +static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, + const struct display_timing *edid, + int phy_div) { struct sunxi_hdmi_phy * const phy = (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); - int div = sunxi_dw_hdmi_get_divider(clock); + int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); u32 tmp; /* @@ -187,6 +189,14 @@ static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, uint clock, int phy_div) writel(0x0F81C405, &phy->unk2); break; } + + if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) + setbits_le32(&phy->pol, 0x200); + + if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) + setbits_le32(&phy->pol, 0x100); + + setbits_le32(&phy->ctrl, 0xf << 12); } static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div) @@ -272,7 +282,7 @@ static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, int phy_div; sunxi_dw_hdmi_pll_set(edid->pixelclock.typ / 1000, &phy_div); - sunxi_dw_hdmi_phy_set(hdmi, edid->pixelclock.typ, phy_div); + sunxi_dw_hdmi_phy_set(hdmi, edid, phy_div); return 0; } @@ -304,14 +314,6 @@ static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp, sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp); - if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) - setbits_le32(&phy->pol, 0x200); - - if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) - setbits_le32(&phy->pol, 0x100); - - setbits_le32(&phy->ctrl, 0xf << 12); - /* * This is last hdmi access before boot, so scramble addresses * again or othwerwise BSP driver won't work. Dummy read is From patchwork Tue Feb 23 20:46:26 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443640 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWQg1RXwz9sVr for ; Wed, 24 Feb 2021 07:50:19 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5BFDC82AD8; Tue, 23 Feb 2021 21:48:38 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A298182A85; Tue, 23 Feb 2021 21:47:35 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs4.siol.net [185.57.226.195]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 1B00582AAC for ; Tue, 23 Feb 2021 21:47:19 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id A63BF5244B9; Tue, 23 Feb 2021 21:47:18 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id PrGIat3ubP7n; Tue, 23 Feb 2021 21:47:17 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id E1986524559; Tue, 23 Feb 2021 21:47:17 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id AF1E4524558; Tue, 23 Feb 2021 21:47:15 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 14/19] video: sunxi: dw-hdmi: rework PHY initialization Date: Tue, 23 Feb 2021 21:46:26 +0100 Message-Id: <20210223204631.1609597-15-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Now that bit meanings are somewhat known, rework PHY initialization. This is modelled after Linux driver. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_dw_hdmi.c | 411 +++++++++++++++++++--------- 1 file changed, 279 insertions(+), 132 deletions(-) diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 4cc175d714ea..c4cded569bfb 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -18,100 +18,200 @@ #include #include +#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8) +#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9) +#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16) +#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16) + +#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31) + +#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545 + +#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47 + +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVRCAL(x) ((x) << 26) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(x) ((x) << 24) +#define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23) +#define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT BIT(22) +#define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT BIT(21) +#define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT BIT(20) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL BIT(19) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG BIT(18) +#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS BIT(17) +#define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN BIT(16) +#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK GENMASK(15, 12) +#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL (0xf << 12) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK BIT(11) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 BIT(10) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 BIT(9) +#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 BIT(8) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK BIT(7) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 BIT(6) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 BIT(5) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 BIT(4) +#define SUN8I_HDMI_PHY_ANA_CFG1_CKEN BIT(3) +#define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN BIT(2) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS BIT(1) +#define SUN8I_HDMI_PHY_ANA_CFG1_ENBI BIT(0) + +#define SUN8I_HDMI_PHY_ANA_CFG2_M_EN BIT(31) +#define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN BIT(30) +#define SUN8I_HDMI_PHY_ANA_CFG2_SEN BIT(29) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD BIT(28) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN BIT(27) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK BIT(26) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLR(x) ((x) << 23) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK BIT(22) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN BIT(21) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CD(x) ((x) << 19) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(x) ((x) << 17) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK BIT(16) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW BIT(15) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(x) ((x) << 13) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(x) ((x) << 10) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOSTCK(x) ((x) << 8) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOST(x) ((x) << 6) +#define SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(x) ((x) << 0) + +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOWCK(x) ((x) << 30) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOW(x) ((x) << 28) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(x) ((x) << 18) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(x) ((x) << 14) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMPCK(x) ((x) << 11) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(x) ((x) << 7) +#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(x) ((x) << 4) +#define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD BIT(3) +#define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN BIT(2) +#define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD BIT(1) +#define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN BIT(0) + +#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 BIT(31) +#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD BIT(30) +#define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29) +#define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28) +#define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27) +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26) +#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26 +#define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25) +#define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22) +#define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20) +#define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN BIT(19) +#define SUN8I_HDMI_PHY_PLL_CFG1_CS BIT(18) +#define SUN8I_HDMI_PHY_PLL_CFG1_CP_S(x) ((x) << 13) +#define SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(x) ((x) << 7) +#define SUN8I_HDMI_PHY_PLL_CFG1_BWS BIT(6) +#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK GENMASK(5, 0) +#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT 0 + +#define SUN8I_HDMI_PHY_PLL_CFG2_SV_H BIT(31) +#define SUN8I_HDMI_PHY_PLL_CFG2_PDCLKSEL(x) ((x) << 29) +#define SUN8I_HDMI_PHY_PLL_CFG2_CLKSTEP(x) ((x) << 27) +#define SUN8I_HDMI_PHY_PLL_CFG2_PSET(x) ((x) << 24) +#define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL BIT(23) +#define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS BIT(22) +#define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN BIT(21) +#define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN BIT(20) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN BIT(19) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN(x) ((x) << 16) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(x) ((x) << 12) +#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN BIT(11) +#define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC BIT(10) +#define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2 BIT(9) +#define SUN8I_HDMI_PHY_PLL_CFG2_S(x) ((x) << 6) +#define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5 BIT(5) +#define SUN8I_HDMI_PHY_PLL_CFG2_S5_7 BIT(4) +#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK GENMASK(3, 0) +#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT 0 +#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(x) (((x) - 1) << 0) + +#define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2 BIT(0) + +#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT 11 +#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK GENMASK(16, 11) +#define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D BIT(7) +#define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK GENMASK(5, 0) + struct sunxi_dw_hdmi_priv { struct dw_hdmi hdmi; int mux; + uint rcal; }; struct sunxi_hdmi_phy { - u32 pol; - u32 res1[3]; + u32 dbg_ctrl; + u32 rext_ctrl; + u32 res1[2]; u32 read_en; u32 unscramble; u32 res2[2]; - u32 ctrl; - u32 unk1; - u32 unk2; - u32 pll; - u32 clk; - u32 unk3; - u32 status; + u32 ana_cfg1; + u32 ana_cfg2; + u32 ana_cfg3; + u32 pll_cfg1; + u32 pll_cfg2; + u32 pll_cfg3; + u32 ana_sts; }; #define HDMI_PHY_OFFS 0x10000 -static int sunxi_dw_hdmi_get_divider(uint clock) -{ - /* - * Due to missing documentaion of HDMI PHY, we know correct - * settings only for following four PHY dividers. Select one - * based on clock speed. - */ - if (clock <= 27000000) - return 11; - else if (clock <= 74250000) - return 4; - else if (clock <= 148500000) - return 2; - else - return 1; -} - -static void sunxi_dw_hdmi_phy_init(struct dw_hdmi *hdmi) +static void sunxi_dw_hdmi_phy_init(struct sunxi_dw_hdmi_priv *priv) { struct sunxi_hdmi_phy * const phy = - (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); + (struct sunxi_hdmi_phy *)(priv->hdmi.ioaddr + HDMI_PHY_OFFS); unsigned long tmo; - u32 tmp; - /* - * HDMI PHY settings are taken as-is from Allwinner BSP code. - * There is no documentation. - */ - writel(0, &phy->ctrl); - setbits_le32(&phy->ctrl, BIT(0)); + /* enable read access to HDMI controller */ + writel(SUN8I_HDMI_PHY_READ_EN_MAGIC, &phy->read_en); + /* descramble register offsets */ + writel(SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC, &phy->unscramble); + + writel(0, &phy->ana_cfg1); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENBI); udelay(5); - setbits_le32(&phy->ctrl, BIT(16)); - setbits_le32(&phy->ctrl, BIT(1)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENVBS); udelay(10); - setbits_le32(&phy->ctrl, BIT(2)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_LDOEN); udelay(5); - setbits_le32(&phy->ctrl, BIT(3)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_CKEN); udelay(40); - setbits_le32(&phy->ctrl, BIT(19)); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL); udelay(100); - setbits_le32(&phy->ctrl, BIT(18)); - setbits_le32(&phy->ctrl, 7 << 4); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG); + setbits_le32(&phy->ana_cfg1, + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2); /* Note that Allwinner code doesn't fail in case of timeout */ tmo = timer_get_us() + 2000; - while ((readl(&phy->status) & 0x80) == 0) { + while ((readl(&phy->ana_sts) & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D) == 0) { if (timer_get_us() > tmo) { printf("Warning: HDMI PHY init timeout!\n"); break; } } - setbits_le32(&phy->ctrl, 0xf << 8); - setbits_le32(&phy->ctrl, BIT(7)); + setbits_le32(&phy->ana_cfg1, + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK); - writel(0x39dc5040, &phy->pll); - writel(0x80084343, &phy->clk); - udelay(10000); - writel(1, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - udelay(100000); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FF0F7F, &phy->ctrl); - writel(0x80639000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); + /* enable DDC communication */ + writel(SUN8I_HDMI_PHY_ANA_CFG3_SCLEN | + SUN8I_HDMI_PHY_ANA_CFG3_SDAEN, &phy->ana_cfg3); - /* enable read access to HDMI controller */ - writel(0x54524545, &phy->read_en); - /* descramble register offsets */ - writel(0x42494E47, &phy->unscramble); + priv->rcal = readl(&phy->ana_sts) & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK; + priv->rcal >>= 2; } static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, @@ -120,83 +220,130 @@ static void sunxi_dw_hdmi_phy_set(struct dw_hdmi *hdmi, { struct sunxi_hdmi_phy * const phy = (struct sunxi_hdmi_phy *)(hdmi->ioaddr + HDMI_PHY_OFFS); - int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ); - u32 tmp; + struct sunxi_dw_hdmi_priv *priv = + container_of(hdmi, struct sunxi_dw_hdmi_priv, hdmi); + u32 pll_cfg1, pll_cfg2, ana_cfg1, ana_cfg2, ana_cfg3; + u32 tmp, b_offset = 0; - /* - * Unfortunately, we don't know much about those magic - * numbers. They are taken from Allwinner BSP driver. - */ - switch (div) { - case 1: - writel(0x30dc5fc0, &phy->pll); - writel(0x800863C0 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(200); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - if (tmp < 0x3d) - setbits_le32(&phy->pll, tmp + 2); - else - setbits_le32(&phy->pll, 0x3f); - mdelay(100); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F8246B5, &phy->unk2); - break; - case 2: - writel(0x39dc5040, &phy->pll); - writel(0x80084380 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063a800, &phy->unk1); - writel(0x0F81C485, &phy->unk2); - break; - case 4: - writel(0x39dc5040, &phy->pll); - writel(0x80084340 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); - break; - case 11: - writel(0x39dc5040, &phy->pll); - writel(0x80084300 | (phy_div - 1), &phy->clk); - mdelay(10); - writel(0x00000001, &phy->unk3); - setbits_le32(&phy->pll, BIT(25)); - mdelay(100); - tmp = (readl(&phy->status) & 0x1f800) >> 11; - setbits_le32(&phy->pll, BIT(31) | BIT(30)); - setbits_le32(&phy->pll, tmp); - writel(0x01FFFF7F, &phy->ctrl); - writel(0x8063b000, &phy->unk1); - writel(0x0F81C405, &phy->unk2); - break; + /* bandwidth / frequency independent settings */ + + pll_cfg1 = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN | + SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN | + SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) | + SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) | + SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN | + SUN8I_HDMI_PHY_PLL_CFG1_CS | + SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) | + SUN8I_HDMI_PHY_PLL_CFG1_BWS; + + pll_cfg2 = SUN8I_HDMI_PHY_PLL_CFG2_SV_H | + SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN | + SUN8I_HDMI_PHY_PLL_CFG2_SDIV2; + + ana_cfg1 = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) | + SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT | + SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL | + SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG | + SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS | + SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN | + SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 | + SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 | + SUN8I_HDMI_PHY_ANA_CFG1_CKEN | + SUN8I_HDMI_PHY_ANA_CFG1_LDOEN | + SUN8I_HDMI_PHY_ANA_CFG1_ENVBS | + SUN8I_HDMI_PHY_ANA_CFG1_ENBI; + + ana_cfg2 = SUN8I_HDMI_PHY_ANA_CFG2_M_EN | + SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK | + SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN | + SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) | + SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1); + + ana_cfg3 = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) | + SUN8I_HDMI_PHY_ANA_CFG3_SDAEN | + SUN8I_HDMI_PHY_ANA_CFG3_SCLEN; + + /* bandwidth / frequency dependent settings */ + if (edid->pixelclock.typ <= 27000000) { + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | + SUN8I_HDMI_PHY_PLL_CFG2_S(4); + ana_cfg1 |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW; + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) | + SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(priv->rcal); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5); + } else if (edid->pixelclock.typ <= 74250000) { + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | + SUN8I_HDMI_PHY_PLL_CFG2_S(5); + ana_cfg1 |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW; + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) | + SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(priv->rcal); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7); + } else if (edid->pixelclock.typ <= 148500000) { + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | + SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | + SUN8I_HDMI_PHY_PLL_CFG2_S(6); + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK | + SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | + SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9); + } else { + b_offset = 2; + pll_cfg1 |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63); + pll_cfg2 |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) | + SUN8I_HDMI_PHY_PLL_CFG2_S(7); + ana_cfg2 |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK | + SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | + SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4); + ana_cfg3 |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) | + SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3); } + writel(pll_cfg1, &phy->pll_cfg1); + writel(pll_cfg2 | (phy_div - 1), &phy->pll_cfg2); + mdelay(10); + writel(SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2, &phy->pll_cfg3); + setbits_le32(&phy->pll_cfg1, SUN8I_HDMI_PHY_PLL_CFG1_PLLEN); + mdelay(100); + tmp = readl(&phy->ana_sts) & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK; + tmp >>= SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT; + tmp = min(tmp + b_offset, (u32)0x3f); + setbits_le32(&phy->pll_cfg1, + SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 | + SUN8I_HDMI_PHY_PLL_CFG1_REG_OD); + setbits_le32(&phy->pll_cfg1, tmp); + mdelay(100); + writel(ana_cfg1, &phy->ana_cfg1); + writel(ana_cfg2, &phy->ana_cfg2); + writel(ana_cfg3, &phy->ana_cfg3); + if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) - setbits_le32(&phy->pol, 0x200); + setbits_le32(&phy->dbg_ctrl, + SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC); if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) - setbits_le32(&phy->pol, 0x100); + setbits_le32(&phy->dbg_ctrl, + SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC); - setbits_le32(&phy->ctrl, 0xf << 12); + setbits_le32(&phy->ana_cfg1, SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL); } static void sunxi_dw_hdmi_pll_set(uint clk_khz, int *phy_div) @@ -363,7 +510,7 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) /* Clock on */ setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); - sunxi_dw_hdmi_phy_init(&priv->hdmi); + sunxi_dw_hdmi_phy_init(priv); priv->mux = uc_plat->source_id; From patchwork Tue Feb 23 20:46:27 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443637 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWPz4Yrgz9sVw for ; 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dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 6E474524558; Tue, 23 Feb 2021 21:47:20 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id gjbQxQZNgTqS; Tue, 23 Feb 2021 21:47:20 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 2410B5244B9; Tue, 23 Feb 2021 21:47:20 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id E7E1B52455A; Tue, 23 Feb 2021 21:47:17 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 15/19] video: sunxi: de2: switch to DT probing Date: Tue, 23 Feb 2021 21:46:27 +0100 Message-Id: <20210223204631.1609597-16-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently DE2 driver is probed via driver info. Switch probing to device tree compatible string method. Display is now searched via driver name which has same limitation as previous method. This can be improved only when all drivers in chain are probed via device tree compatible strings. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_de2.c | 88 +++++++++++++++++++-------------- 1 file changed, 52 insertions(+), 36 deletions(-) diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index e02d359cd259..81576e45e9ef 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -31,6 +31,11 @@ enum { LCD_MAX_LOG2_BPP = VIDEO_BPP32, }; +struct sunxi_de2_data { + int id; + const char *disp_drv_name; +}; + static void sunxi_de2_composer_init(void) { struct sunxi_ccm_reg * const ccm = @@ -228,51 +233,34 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, static int sunxi_de2_probe(struct udevice *dev) { + const struct sunxi_de2_data *data = + (const struct sunxi_de2_data *)dev_get_driver_data(dev); struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct udevice *disp; - int ret; + int ret, index = 0; /* Before relocation we don't need to do anything */ if (!(gd->flags & GD_FLG_RELOC)) return 0; - ret = uclass_get_device_by_driver(UCLASS_DISPLAY, - DM_DRIVER_GET(sunxi_lcd), &disp); - if (!ret) { - int mux; + while (!(ret = uclass_get_device(UCLASS_DISPLAY, index++, &disp))) { + if (strcmp(disp->driver->name, data->disp_drv_name)) + continue; - mux = 0; + ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, + data->id, false); + if (ret) + return ret; - ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, - false); - if (!ret) { - video_set_flush_dcache(dev, 1); - return 0; - } - } - - debug("%s: lcd display not found (ret=%d)\n", __func__, ret); - - ret = uclass_get_device_by_driver(UCLASS_DISPLAY, - DM_DRIVER_GET(sunxi_dw_hdmi), &disp); - if (!ret) { - int mux; - if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5)) - mux = 0; - else - mux = 1; + video_set_flush_dcache(dev, 1); - ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, - false); - if (!ret) { - video_set_flush_dcache(dev, 1); - return 0; - } + return 0; } - debug("%s: hdmi display not found (ret=%d)\n", __func__, ret); + debug("%s: %s not found (ret=%d)\n", __func__, + data->disp_drv_name, ret); - return -ENODEV; + return ret; } static int sunxi_de2_bind(struct udevice *dev) @@ -285,22 +273,50 @@ static int sunxi_de2_bind(struct udevice *dev) return 0; } +const struct sunxi_de2_data h3_mixer_0 = { + .id = 0, + .disp_drv_name = "sunxi_dw_hdmi", +}; + +const struct sunxi_de2_data a64_mixer_0 = { + .id = 0, + .disp_drv_name = "sunxi_lcd", +}; + +const struct sunxi_de2_data a64_mixer_1 = { + .id = 1, + .disp_drv_name = "sunxi_dw_hdmi", +}; + +static const struct udevice_id sunxi_de2_ids[] = { + { + .compatible = "allwinner,sun8i-h3-de2-mixer-0", + .data = (ulong)&h3_mixer_0, + }, + { + .compatible = "allwinner,sun50i-a64-de2-mixer-0", + .data = (ulong)&a64_mixer_0, + }, + { + .compatible = "allwinner,sun50i-a64-de2-mixer-1", + .data = (ulong)&a64_mixer_1, + }, + { } +}; + static const struct video_ops sunxi_de2_ops = { }; U_BOOT_DRIVER(sunxi_de2) = { .name = "sunxi_de2", .id = UCLASS_VIDEO, + .of_match = sunxi_de2_ids, .ops = &sunxi_de2_ops, .bind = sunxi_de2_bind, .probe = sunxi_de2_probe, .flags = DM_FLAG_PRE_RELOC, }; -U_BOOT_DRVINFO(sunxi_de2) = { - .name = "sunxi_de2" -}; - /* * Simplefb support. */ From patchwork Tue Feb 23 20:46:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443638 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWQB35Pjz9sVX for ; Wed, 24 Feb 2021 07:49:54 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7DF3D82ACA; Tue, 23 Feb 2021 21:48:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 03FB782A98; Tue, 23 Feb 2021 21:47:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs11.siol.net [185.57.226.202]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EDC2782A96 for ; Tue, 23 Feb 2021 21:47:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 9021F524558; Tue, 23 Feb 2021 21:47:22 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id HOBHr41u7xA5; Tue, 23 Feb 2021 21:47:22 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 59451524384; Tue, 23 Feb 2021 21:47:22 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 2A3DF524559; Tue, 23 Feb 2021 21:47:20 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 16/19] video: sunxi: de2: read address from DT node Date: Tue, 23 Feb 2021 21:46:28 +0100 Message-Id: <20210223204631.1609597-17-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Currently DE2 uses hardcoded address based on SoC for which U-Boot is built. Read it from DT instead so there is no need to specify it when support for new SoC is added. Signed-off-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_de2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index 81576e45e9ef..f6c8ca075aba 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -64,11 +64,10 @@ static void sunxi_de2_composer_init(void) setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); } -static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, +static void sunxi_de2_mode_set(ulong de_mux_base, int mux, + const struct display_timing *mode, int bpp, ulong address, bool is_composite) { - ulong de_mux_base = (mux == 0) ? - SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE; struct de_clk * const de_clk_regs = (struct de_clk *)(SUNXI_DE2_BASE); struct de_glb * const de_glb_regs = @@ -208,7 +207,8 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, } sunxi_de2_composer_init(); - sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite); + sunxi_de2_mode_set((ulong)dev_read_addr(dev), mux, &timing, + 1 << l2bpp, fbbase, is_composite); ret = display_enable(disp, 1 << l2bpp, &timing); if (ret) { From patchwork Tue Feb 23 20:46:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443639 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWQQ703Dz9sVr for ; Wed, 24 Feb 2021 07:50:06 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1D3A782ADA; Tue, 23 Feb 2021 21:48:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id C01DE82A9F; Tue, 23 Feb 2021 21:47:33 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,KHOP_HELO_FCRDNS, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs26.siol.net [185.57.226.217]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4C9F882A6C for ; Tue, 23 Feb 2021 21:47:25 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id D4A3B5244B9; Tue, 23 Feb 2021 21:47:24 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id SICqZcB0fPsA; Tue, 23 Feb 2021 21:47:24 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 929F15244B5; Tue, 23 Feb 2021 21:47:24 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 5F9E95244B9; Tue, 23 Feb 2021 21:47:22 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Lukasz Majewski Subject: [PATCH 17/19] clk: sunxi: Add DE2 clocks to H3 and A64 Date: Tue, 23 Feb 2021 21:46:29 +0100 Message-Id: <20210223204631.1609597-18-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean With the next commit another clock and reset driver will be implemented which requires DE2 related clocks and resets. Add them. Cc: Lukasz Majewski Signed-off-by: Jernej Skrabec --- drivers/clk/sunxi/clk_a64.c | 6 ++++++ drivers/clk/sunxi/clk_h3.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c index 0553ffa4399a..c7cf88ce3436 100644 --- a/drivers/clk/sunxi/clk_a64.c +++ b/drivers/clk/sunxi/clk_a64.c @@ -26,6 +26,8 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)), + [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -41,6 +43,8 @@ static const struct ccu_clk_gate a64_gates[] = { [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)), [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)), [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), + + [CLK_DE] = GATE(0x104, BIT(31)), }; static const struct ccu_reset a64_resets[] = { @@ -60,6 +64,8 @@ static const struct ccu_reset a64_resets[] = { [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)), [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)), + [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index f81633b92d5a..bf8d963d18b6 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -30,6 +30,8 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), + [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), @@ -48,6 +50,8 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)), + + [CLK_DE] = GATE(0x104, BIT(31)), }; static struct ccu_reset h3_resets[] = { @@ -72,6 +76,8 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)), + [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), From patchwork Tue Feb 23 20:46:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443641 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWQs6pzhz9sVX for ; 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dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 2FE005244B5; Tue, 23 Feb 2021 21:47:27 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id nhBumSYsktVW; Tue, 23 Feb 2021 21:47:26 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id D23A45244B9; Tue, 23 Feb 2021 21:47:26 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id 98FDE524558; Tue, 23 Feb 2021 21:47:24 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, Lukasz Majewski Subject: [PATCH 18/19] clk: sunxi: add DE2 clock driver Date: Tue, 23 Feb 2021 21:46:30 +0100 Message-Id: <20210223204631.1609597-19-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Video driver currently manages clocks and resets by directly writing to registers. This is already a bit messy because each SoC has some specifics. It's much better to implement proper clock and reset driver which takes information from device tree file. Note that this driver is not perfect yet. It still sets PLL and parent by hand. Sunxi clock framework still doesn't know how to set parents or rates. However, this is already big step in right direction. Cc: Lukasz Majewski Signed-off-by: Jernej Skrabec --- drivers/clk/sunxi/Kconfig | 5 +++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_de2.c | 85 +++++++++++++++++++++++++++++++++++++ 3 files changed, 91 insertions(+) create mode 100644 drivers/clk/sunxi/clk_de2.c diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index bf084fa7a84a..6c96affb1f87 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -44,6 +44,11 @@ config CLK_SUN8I_A83T This enables common clock driver support for platforms based on Allwinner A83T SoC. +config CLK_SUN8I_DE2 + bool "Clock driver for Allwinner Display Engine 2 and 3" + help + This enables common clock driver support for Display Engine 2 and 3. + config CLK_SUN8I_R40 bool "Clock driver for Allwinner R40" default MACH_SUN8I_R40 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 0dfc0593fb1c..620ff96ac6f5 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o +obj-$(CONFIG_CLK_SUN8I_DE2) += clk_de2.o obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o diff --git a/drivers/clk/sunxi/clk_de2.c b/drivers/clk/sunxi/clk_de2.c new file mode 100644 index 000000000000..b8c45404c1b6 --- /dev/null +++ b/drivers/clk/sunxi/clk_de2.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Jernej Skrabec + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct ccu_clk_gate de2_gates[] = { + [CLK_MIXER0] = GATE(0x00, BIT(0)), + [CLK_MIXER1] = GATE(0x00, BIT(1)), + [CLK_WB] = GATE(0x00, BIT(2)), + + [CLK_BUS_MIXER0] = GATE(0x04, BIT(0)), + [CLK_BUS_MIXER1] = GATE(0x04, BIT(1)), + [CLK_BUS_WB] = GATE(0x04, BIT(2)), +}; + +static struct ccu_reset de2_resets[] = { + [RST_MIXER0] = RESET(0x08, BIT(0)), + [RST_MIXER1] = RESET(0x08, BIT(1)), + [RST_WB] = RESET(0x08, BIT(2)), +}; + +static const struct ccu_desc de2_ccu_desc = { + .gates = de2_gates, + .resets = de2_resets, +}; + +static int de2_clk_probe(struct udevice *dev) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + u32 val; + + if (device_is_compatible(dev_get_parent(dev), + "allwinner,sun50i-a64-de2")) { + /* set SRAM for video use */ + val = readl(SUNXI_SRAMC_BASE + 0x04); + val &= ~(0x01 << 24); + writel(val, SUNXI_SRAMC_BASE + 0x04); + } + + /* clock driver doesn't know how to set rate or parent yet */ + clock_set_pll10(432000000); + + /* Set DE parent to pll10 */ + clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, + CCM_DE2_CTRL_PLL10); + + return sunxi_clk_probe(dev); +} + +static int de2_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(de2_resets)); +} + +static const struct udevice_id de2_ccu_ids[] = { + { .compatible = "allwinner,sun8i-h3-de2-clk", + .data = (ulong)&de2_ccu_desc }, + { .compatible = "allwinner,sun50i-a64-de2-clk", + .data = (ulong)&de2_ccu_desc }, + { .compatible = "allwinner,sun50i-h5-de2-clk", + .data = (ulong)&de2_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_de2) = { + .name = "sun8i_de2_ccu", + .id = UCLASS_CLK, + .of_match = de2_ccu_ids, + .priv_auto = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = de2_clk_probe, + .bind = de2_clk_bind, +}; From patchwork Tue Feb 23 20:46:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1443642 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DlWR44cFYz9sVX for ; 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dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTP id 5F16952454D; Tue, 23 Feb 2021 21:47:29 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta11.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id GwH-J0Qpnl5z; Tue, 23 Feb 2021 21:47:29 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Postfix) with ESMTPS id 11E5F5244B9; Tue, 23 Feb 2021 21:47:29 +0100 (CET) Received: from kista.localdomain (cpe-86-58-17-133.cable.triera.net [86.58.17.133]) (Authenticated sender: 031275009) by mail.siol.net (Postfix) with ESMTPSA id D7AE652454D; Tue, 23 Feb 2021 21:47:26 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com, agust@denx.de Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH 19/19] video: sunxi: de2: switch clock setup to DM model Date: Tue, 23 Feb 2021 21:46:31 +0100 Message-Id: <20210223204631.1609597-20-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210223204631.1609597-1-jernej.skrabec@siol.net> References: <20210223204631.1609597-1-jernej.skrabec@siol.net> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Now that proper DM clock and reset driver exists for Display Engine 2 and 3, remove all clock and reset related code and use appropriate framework instead. Signed-off-by: Jernej Skrabec --- arch/arm/mach-sunxi/Kconfig | 1 + drivers/video/sunxi/sunxi_de2.c | 67 +++++++++++---------------------- 2 files changed, 23 insertions(+), 45 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 9149196b223e..34ef1f4b030f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -970,6 +970,7 @@ config SUNXI_DE2 config VIDEO_DE2 bool "Display Engine 2 video driver" depends on SUNXI_DE2 + select CLK_SUN8I_DE2 select DM_VIDEO select DISPLAY select VIDEO_DW_HDMI diff --git a/drivers/video/sunxi/sunxi_de2.c b/drivers/video/sunxi/sunxi_de2.c index f6c8ca075aba..cee9b46b1259 100644 --- a/drivers/video/sunxi/sunxi_de2.c +++ b/drivers/video/sunxi/sunxi_de2.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -14,10 +15,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include "simplefb_common.h" @@ -36,40 +37,10 @@ struct sunxi_de2_data { const char *disp_drv_name; }; -static void sunxi_de2_composer_init(void) -{ - struct sunxi_ccm_reg * const ccm = - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - -#ifdef CONFIG_MACH_SUN50I - u32 reg_value; - - /* set SRAM for video use (A64 only) */ - reg_value = readl(SUNXI_SRAMC_BASE + 0x04); - reg_value &= ~(0x01 << 24); - writel(reg_value, SUNXI_SRAMC_BASE + 0x04); -#endif - - clock_set_pll10(432000000); - - /* Set DE parent to pll10 */ - clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, - CCM_DE2_CTRL_PLL10); - - /* Set ahb gating to pass */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); - setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); - - /* Clock on */ - setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); -} - -static void sunxi_de2_mode_set(ulong de_mux_base, int mux, +static void sunxi_de2_mode_set(ulong de_mux_base, const struct display_timing *mode, int bpp, ulong address, bool is_composite) { - struct de_clk * const de_clk_regs = - (struct de_clk *)(SUNXI_DE2_BASE); struct de_glb * const de_glb_regs = (struct de_glb *)(de_mux_base + SUNXI_DE2_MUX_GLB_REGS); @@ -87,17 +58,6 @@ static void sunxi_de2_mode_set(ulong de_mux_base, int mux, int channel; u32 format; - /* enable clock */ -#ifdef CONFIG_MACH_SUN8I_H3 - setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4); -#else - setbits_le32(&de_clk_regs->rst_cfg, BIT(mux)); -#endif - setbits_le32(&de_clk_regs->gate_cfg, BIT(mux)); - setbits_le32(&de_clk_regs->bus_cfg, BIT(mux)); - - clrbits_le32(&de_clk_regs->sel_cfg, 1); - writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl); writel(0, &de_glb_regs->status); writel(1, &de_glb_regs->dbuff); @@ -189,6 +149,8 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, struct video_priv *uc_priv = dev_get_uclass_priv(dev); struct display_timing timing; struct display_plat *disp_uc_plat; + struct reset_ctl_bulk resets; + struct clk_bulk clocks; int ret; disp_uc_plat = dev_get_uclass_plat(disp); @@ -206,8 +168,23 @@ static int sunxi_de2_init(struct udevice *dev, ulong fbbase, return ret; } - sunxi_de2_composer_init(); - sunxi_de2_mode_set((ulong)dev_read_addr(dev), mux, &timing, + ret = reset_get_bulk(dev, &resets); + if (ret) + return ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + + ret = reset_deassert_bulk(&resets); + if (ret) + return ret; + + sunxi_de2_mode_set((ulong)dev_read_addr(dev), &timing, 1 << l2bpp, fbbase, is_composite); ret = display_enable(disp, 1 << l2bpp, &timing);