From patchwork Sat Feb 13 20:37:49 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Wilson X-Patchwork-Id: 1440249 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=2620:52:3:1:0:246e:9693:128c; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=NsOAwLKT; dkim-atps=neutral Received: from sourceware.org (server2.sourceware.org [IPv6:2620:52:3:1:0:246e:9693:128c]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DdMd773Fhz9sBJ for ; Sun, 14 Feb 2021 07:38:01 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5586B3896825; Sat, 13 Feb 2021 20:37:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by sourceware.org (Postfix) with ESMTPS id BFDA3387084D for ; Sat, 13 Feb 2021 20:37:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org BFDA3387084D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jimw@sifive.com Received: by mail-pj1-x1035.google.com with SMTP id cl8so1518239pjb.0 for ; Sat, 13 Feb 2021 12:37:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=efaDZ78SYHHUhLMSTtTOOL7QSKyrkSLDGuzI0+zPQZ8=; b=NsOAwLKTCBN8n7lUXQmHE10v9qa3XYp2GBLNWoBoT/PDiWVjb6Ii/viFXcWwj2YjPs x+PXuJ1HWEnX88lYhXv+mfMaBXOer/rnafPkd0nc574XsipM6p8wqYsrs37mG3U62Wte 9sgDMVD54+oL76ashdUb6qWtpW7kEwyLLpVUTJvsw6KFv797+YKLHzEDPhzKQIpERc2K 8VySOud86MhfOAFYLJsYAyfLubpW4Q56cfZcRfZfHbpUYmER9iF9nQisEGyQYzH9okGA f2bKXDSxy/pYnCxkakdGef/3imyjzFzWoAtFMCoKcw3wg3LFm3Kbh98O1wVr8HbYUc4H FMuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=efaDZ78SYHHUhLMSTtTOOL7QSKyrkSLDGuzI0+zPQZ8=; b=q4ImsT4+DR11ikJ4+CXbZSgHedqxr/DAeSW3wi+VnaAsglSOIPdQ0s75oIEskxS8sd /Lo4fS0qIffw6AAisgi+Y/udhiL5eYudM0qqIYkNsQd+fL81k3Jex2CYHJ9aMYaVuN12 gQM/vcSQ+ykn+EG+ZAzWA1K+VXqqKsG6CQtMMiB7n3MBo7edXmNvjaO2aX/8UHUUD4ZQ qIkTzM8u+h8ozJs68uZZIxl66ECB3aZnsHKWeYG9SNPhA/sgEHSUB1zKc5Bg8qwqE6UW iillKNiP7DSErL58hcdNJFUQVZFWDAHfdaMJ79nnM/iYHRNMiPq8ykO3iG2Dt3eNPZpW 5Gkg== X-Gm-Message-State: AOAM530vntzN6/wsiz2b5YXjZ4P09Zvc5uXBK3U6hsc9U6uXDQ4foIQV o4IGtRGNbQ8NdRKx584pC+Tn/tJsrSbbjw== X-Google-Smtp-Source: ABdhPJzWQpsdtd6ToW16d+ud1VVSF3Bt7/hMCMMlCYjzvXe31USLe8I6WeDU54AM3WBWv7Xi4gYKIw== X-Received: by 2002:a17:902:b941:b029:e3:1628:97b7 with SMTP id h1-20020a170902b941b02900e3162897b7mr8323224pls.60.1613248674491; Sat, 13 Feb 2021 12:37:54 -0800 (PST) Received: from rohan.hsd1.ca.comcast.net ([2601:646:c180:b150:e8ee:15df:b599:9672]) by smtp.gmail.com with ESMTPSA id 3sm11354391pjk.26.2021.02.13.12.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 Feb 2021 12:37:54 -0800 (PST) From: Jim Wilson To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417. Date: Sat, 13 Feb 2021 12:37:49 -0800 Message-Id: <20210213203749.25463-1-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Levy Hsu Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" From: Levy Hsu This expands sub-word loads as a zero/sign extended load, followed by a subreg. This helps eliminate unnecessary zero/sign extend insns after the load, particularly for volatiles, but also in some other cases. Testing shows that it gives consistent code size decreases. Tested with riscv32-elf rv32imac/ilp32 and riscv64-linux rv64gc/lp064d builds and checks. Some -gsplit-stack tests fail with the patch, but this turns out to be an existing bug with the split-stack support that I hadn't noticed before. It isn't a bug in this patch. Ignoring that there are no regressions. Committed. gcc/ PR target/97417 * config/riscv/riscv-shorten-memrefs.c (pass_shorten_memrefs): Add extend parameter to get_si_mem_base_reg declaration. (get_si_mem_base_reg): Add extend parameter. Set it. (analyze): Pass extend arg to get_si_mem_base_reg. (transform): Likewise. Use it when rewriting mems. * config/riscv/riscv.c (riscv_legitimize_move): Check for subword loads and emit sign/zero extending load followed by subreg move. --- gcc/config/riscv/riscv-shorten-memrefs.c | 34 +++++++++++++++++++----- gcc/config/riscv/riscv.c | 22 +++++++++++++++ 2 files changed, 49 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-shorten-memrefs.c b/gcc/config/riscv/riscv-shorten-memrefs.c index b1b57f1b5e0..3f34065c1ce 100644 --- a/gcc/config/riscv/riscv-shorten-memrefs.c +++ b/gcc/config/riscv/riscv-shorten-memrefs.c @@ -75,12 +75,19 @@ private: regno_map * analyze (basic_block bb); void transform (regno_map *m, basic_block bb); - bool get_si_mem_base_reg (rtx mem, rtx *addr); + bool get_si_mem_base_reg (rtx mem, rtx *addr, bool *extend); }; // class pass_shorten_memrefs bool -pass_shorten_memrefs::get_si_mem_base_reg (rtx mem, rtx *addr) +pass_shorten_memrefs::get_si_mem_base_reg (rtx mem, rtx *addr, bool *extend) { + /* Whether it's sign/zero extended. */ + if (GET_CODE (mem) == ZERO_EXTEND || GET_CODE (mem) == SIGN_EXTEND) + { + *extend = true; + mem = XEXP (mem, 0); + } + if (!MEM_P (mem) || GET_MODE (mem) != SImode) return false; *addr = XEXP (mem, 0); @@ -110,7 +117,8 @@ pass_shorten_memrefs::analyze (basic_block bb) { rtx mem = XEXP (pat, i); rtx addr; - if (get_si_mem_base_reg (mem, &addr)) + bool extend = false; + if (get_si_mem_base_reg (mem, &addr, &extend)) { HOST_WIDE_INT regno = REGNO (XEXP (addr, 0)); /* Do not count store zero as these cannot be compressed. */ @@ -150,7 +158,8 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block bb) { rtx mem = XEXP (pat, i); rtx addr; - if (get_si_mem_base_reg (mem, &addr)) + bool extend = false; + if (get_si_mem_base_reg (mem, &addr, &extend)) { HOST_WIDE_INT regno = REGNO (XEXP (addr, 0)); /* Do not transform store zero as these cannot be compressed. */ @@ -161,9 +170,20 @@ pass_shorten_memrefs::transform (regno_map *m, basic_block bb) } if (m->get_or_insert (regno) > 3) { - addr - = targetm.legitimize_address (addr, addr, GET_MODE (mem)); - XEXP (pat, i) = replace_equiv_address (mem, addr); + if (extend) + { + addr + = targetm.legitimize_address (addr, addr, + GET_MODE (XEXP (mem, 0))); + XEXP (XEXP (pat, i), 0) + = replace_equiv_address (XEXP (mem, 0), addr); + } + else + { + addr = targetm.legitimize_address (addr, addr, + GET_MODE (mem)); + XEXP (pat, i) = replace_equiv_address (mem, addr); + } df_insn_rescan (insn); } } diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 7d274596ba3..fffd0814eee 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1524,6 +1524,28 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) bool riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) { + /* Expand + (set (reg:QI target) (mem:QI (address))) + to + (set (reg:DI temp) (zero_extend:DI (mem:QI (address)))) + (set (reg:QI target) (subreg:QI (reg:DI temp) 0)) + with auto-sign/zero extend. */ + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) < UNITS_PER_WORD + && can_create_pseudo_p () + && MEM_P (src)) + { + rtx temp_reg; + int zero_extend_p; + + temp_reg = gen_reg_rtx (word_mode); + zero_extend_p = (LOAD_EXTEND_OP (mode) == ZERO_EXTEND); + emit_insn (gen_extend_insn (temp_reg, src, word_mode, mode, + zero_extend_p)); + riscv_emit_move (dest, gen_lowpart (mode, temp_reg)); + return true; + } + if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) { rtx reg;