From patchwork Mon Feb 1 17:25:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Jernej_=C5=A0krabec?= X-Patchwork-Id: 1434252 X-Patchwork-Delegate: andre.przywara@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DTvxM28xxz9vTr for ; Tue, 2 Feb 2021 04:26:15 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 3D8FA82627; Mon, 1 Feb 2021 18:26:08 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 8A12C82654; Mon, 1 Feb 2021 18:26:06 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_LOW, SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail.siol.net (mailoutvs27.siol.net [185.57.226.218]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 9BDFE801D8 for ; Mon, 1 Feb 2021 18:26:03 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=siol.net Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jernej.skrabec@siol.net Received: from localhost (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTP id 4894B521F31; Mon, 1 Feb 2021 18:26:03 +0100 (CET) Received: from mail.siol.net ([127.0.0.1]) by localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id kWFnzb_5K2vR; Mon, 1 Feb 2021 18:26:03 +0100 (CET) Received: from mail.siol.net (localhost [127.0.0.1]) by mail.siol.net (Zimbra) with ESMTPS id 0CC53521C8D; Mon, 1 Feb 2021 18:26:03 +0100 (CET) Received: from kista.localdomain (cpe-86-58-58-53.static.triera.net [86.58.58.53]) (Authenticated sender: 031275009) by mail.siol.net (Zimbra) with ESMTPSA id 95B97521F96; Mon, 1 Feb 2021 18:26:02 +0100 (CET) From: Jernej Skrabec To: jagan@amarulasolutions.com, andre.przywara@arm.com Cc: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Subject: [PATCH v2] sunxi: spl: Fix H616 clock initialization Date: Mon, 1 Feb 2021 18:25:57 +0100 Message-Id: <20210201172557.3776708-1-jernej.skrabec@siol.net> X-Mailer: git-send-email 2.30.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean It turns out that there is a magic bit in PRCM region which seemingly makes PLLs work if it's enabled. Sadly, there is no documentation what it does exactly, so we'll just mimick BSP boot0 behaviour and enable it before any clock is set up. Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks") Signed-off-by: Jernej Skrabec --- Changes from v1: - use if (IS_ENABLED()) instead of #ifdef #endif arch/arm/mach-sunxi/clock_sun50i_h6.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 06d84eb158d7..492fc4a3fca8 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -9,6 +9,11 @@ void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* this seems to enable PLLs on H616 */ + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10); + clock_set_pll1(408000000); writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);