From patchwork Sun Jan 17 01:31:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 1427674 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256 header.s=google header.b=SUINPn4n; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4DJHTX5lHMz9sWL for ; Sun, 17 Jan 2021 12:32:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727520AbhAQBcP (ORCPT ); Sat, 16 Jan 2021 20:32:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726385AbhAQBcM (ORCPT ); Sat, 16 Jan 2021 20:32:12 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A56BC0613CF for ; Sat, 16 Jan 2021 17:31:20 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id n8so5743026ljg.3 for ; Sat, 16 Jan 2021 17:31:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tf8Myeu0NiVasaQllGDJf9giDfGqj4Lr7pfXB9rMYOo=; b=SUINPn4nDwhozYtpjAYsdnMatmtyWqHA6TxOdxuoy66Gg//CsIyk/0UP5HlNlxe0WA 2HQGxdrqNP+dBZ1JmwWKwoCWXpmql1QDN2NkExL7SzEMas7auT73JQ/EZjIrwl15dlLC Jr6ulZmwqC3IuPL/lC0SVx36WrNATUjdHDg5PBDGaOjGQcAOgPD057tYKf55Z2YbRcKR ATQERCJSRvK9z0NUAvGYre3baY52oiGlR+SnPwsKvirN0oU7k3Ab+Jwt5awYTuPVm7YQ J7KO52y3q2hI4FFLg40Kxt+rDgTQga42FiDilL3fW3QBg6Eh70pDLZHDqWfJTeTaTz1C h+4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tf8Myeu0NiVasaQllGDJf9giDfGqj4Lr7pfXB9rMYOo=; b=P6D8ZFajgzYV3rzEc4j3J/KnccejfmNSMUgrWVFlYm9mY9ej+jDfCZKCZKQT1jLI2K VHImtyWCXhdsfmAxFgPHIunWFenfoBCcpc2X4j1M1wcwQ1BCXFYEMSz2XoBTVbHPYmgO 0VzGId1twzuIhMa9oY0HCXLro6HdYLWwNM+oh45McG79nxvzIa/WENWM9vDV/15hdxCT CWJJZZhU/LQn/KpCEguPdlPW8NHyZM83OhuAfmgJA+13++29zgAlBWCJ0rYNsb2sRC19 Z7+WRkmQNSSIwf33ZdvpTDpXLCJBlPg7t8ZOFpw37yEBS8zkC9aeL2LIdKx6zrjACU/u U5pg== X-Gm-Message-State: AOAM5323+Rbxs7QZWWU40/J6PboTwZHfb/poZLRUOhnYGn0wHjPZCx7S r7QPWqYnycvmCZ/z1WIjQe0bKw== X-Google-Smtp-Source: ABdhPJxCQoQi5eX6x8dtjhEPZ/R38mG5z7G4Vj9Sh7u3S7dHXvKe6mzmI97nOXkWNrLDX4Co6I6BUA== X-Received: by 2002:a2e:80d4:: with SMTP id r20mr7822175ljg.495.1610847078683; Sat, 16 Jan 2021 17:31:18 -0800 (PST) Received: from eriador.lumag.spb.ru ([94.25.228.101]) by smtp.gmail.com with ESMTPSA id c1sm1286298ljd.117.2021.01.16.17.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Jan 2021 17:31:18 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , linux-pci@vger.kernel.org Subject: [PATCH v5 1/2] dt-bindings: pci: qcom: Document ddrss_sf_tbu clock for sm8250 Date: Sun, 17 Jan 2021 04:31:13 +0300 Message-Id: <20210117013114.441973-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> References: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Document this requirement in devicetree bindings. Signed-off-by: Dmitry Baryshkov Fixes: 458168247ccc ("dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC") --- .../devicetree/bindings/pci/qcom,pcie.txt | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3b55310390a0..0da458a051b6 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -132,8 +132,20 @@ - "master_bus" AXI Master clock - "slave_bus" AXI Slave clock --clock-names: - Usage: required for sdm845 and sm8250 +- clock-names: + Usage: required for sdm845 + Value type: + Definition: Should contain the following entries + - "aux" Auxiliary clock + - "cfg" Configuration clock + - "bus_master" Master AXI clock + - "bus_slave" Slave AXI clock + - "slave_q2a" Slave Q2A clock + - "tbu" PCIe TBU clock + - "pipe" PIPE clock + +- clock-names: + Usage: required for sm8250 Value type: Definition: Should contain the following entries - "aux" Auxiliary clock @@ -142,6 +154,7 @@ - "bus_slave" Slave AXI clock - "slave_q2a" Slave Q2A clock - "tbu" PCIe TBU clock + - "ddrss_sf_tbu" PCIe SF TBU clock - "pipe" PIPE clock - resets: From patchwork Sun Jan 17 01:31:14 2021 Content-Type: text/plain; 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Sat, 16 Jan 2021 17:31:19 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Lorenzo Pieralisi Cc: linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam , linux-pci@vger.kernel.org Subject: [PATCH v5 2/2] PCI: qcom: add support for ddrss_sf_tbu clock Date: Sun, 17 Jan 2021 04:31:14 +0300 Message-Id: <20210117013114.441973-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> References: <20210117013114.441973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On SM8250 additional clock is required for PCIe devices to access NOC. Update PCIe controller driver to control this clock. Signed-off-by: Dmitry Baryshkov Fixes: e1dd639e374a ("PCI: qcom: Add SM8250 SoC support") Reviewed-by: Manivannan Sadhasivam Acked-by: Stanimir Varbanov --- drivers/pci/controller/dwc/pcie-qcom.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index affa2713bf80..ab21aa01c95d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -159,8 +159,10 @@ struct qcom_pcie_resources_2_3_3 { struct reset_control *rst[7]; }; +/* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[6]; + struct clk_bulk_data clks[7]; + int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; struct clk *pipe_clk; @@ -1152,8 +1154,14 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[3].id = "bus_slave"; res->clks[4].id = "slave_q2a"; res->clks[5].id = "tbu"; + if (of_device_is_compatible(dev->of_node, "qcom,pcie-sm8250")) { + res->clks[6].id = "ddrss_sf_tbu"; + res->num_clks = 7; + } else { + res->num_clks = 6; + } - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + ret = devm_clk_bulk_get(dev, res->num_clks, res->clks); if (ret < 0) return ret; @@ -1175,7 +1183,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return ret; } - ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + ret = clk_bulk_prepare_enable(res->num_clks, res->clks); if (ret < 0) goto err_disable_regulators; @@ -1227,7 +1235,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) return 0; err_disable_clocks: - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); err_disable_regulators: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); @@ -1238,7 +1246,7 @@ static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; - clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); + clk_bulk_disable_unprepare(res->num_clks, res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); }