From patchwork Thu Jan 7 10:56:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Zissulescu X-Patchwork-Id: 1423242 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=u+s0ERX5; dkim-atps=neutral Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4DBNTw1dXPz9sWC for ; Thu, 7 Jan 2021 21:57:06 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E714D396E844; Thu, 7 Jan 2021 10:57:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E714D396E844 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1610017022; bh=pOuFpv97+9a2C9918wW1jaaBlEptbnO+YC89+pFaxU8=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=u+s0ERX5EnweDDi+AK5FeBu5+b8gUHLvfbtEKvqMXMGc2kjwrNDfyRBoAWjpOB7ag 0MJeJiW6xfxrQvNcUYhl6ARCukYBHsvmQtgBO0EtLw6MPwje5OIWmHsvHBvlpkzuyx cDGDCMMK22bLWJFpy1XieU4VL0ktD2QpIZZMmD18= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id AAA8F3851C26 for ; Thu, 7 Jan 2021 10:56:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org AAA8F3851C26 Received: by mail-ej1-x62c.google.com with SMTP id ga15so9122278ejb.4 for ; Thu, 07 Jan 2021 02:56:59 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=pOuFpv97+9a2C9918wW1jaaBlEptbnO+YC89+pFaxU8=; b=ZNWnpazy/yxL21uqlIqz4LPYJ13jS73ACoh/g7Ki4SOQ9YJYWcyqynByjLh/rlOCVg iCZdaKBWiXlB7c8/3r8EVCxkyS6364mcXRGiXBHtF30f14WYMVaYIaPsDlVswv/9wl9a dyOTi5DPhnyaZ4TOQsVJBsC1cUWqZsNLXbFpggrs6BKAxPqqPxS4fdamKegMY1qeEeLs AtC4CKJn7DS2eYt3tnNMuZtd9gvs6DGxwpzUMK4h6XwSP5PytPHEtdsmPnR0gvSGAris NsiZZRXqMqAJg5/cdR7yLODIfWvdb3o1RcCm5160r6LI+5zsQifJZS7aJH7ax3u2HYr0 m9tA== X-Gm-Message-State: AOAM531AyA3KGuUyKUesmV/u8tol6s1q8XRG2wAkQLbEIjxkGXOI1tbz 14Ol8+0aP7YXhFvJ3a5LCXCBepyaWt/2Lw== X-Google-Smtp-Source: ABdhPJzdlFrDIOSPiJKkffwGNRcUlaUUfoMpTVkiM59wo16Qm83+LBiKYUeLv1hxVCrwNfXtvIl3Zw== X-Received: by 2002:a17:906:400a:: with SMTP id v10mr5932710ejj.302.1610017018396; Thu, 07 Jan 2021 02:56:58 -0800 (PST) Received: from localhost.localdomain ([213.232.87.136]) by smtp.gmail.com with ESMTPSA id t15sm2589538eds.38.2021.01.07.02.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Jan 2021 02:56:57 -0800 (PST) X-Google-Original-From: Claudiu Zissulescu To: gcc-patches@gcc.gnu.org Subject: [backport gcc10] arc: Refurbish adc/sbc patterns Date: Thu, 7 Jan 2021 12:56:52 +0200 Message-Id: <20210107105652.159696-1-claziss@synopsys.com> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Claudiu Zissulescu via Gcc-patches From: Claudiu Zissulescu Reply-To: Claudiu Zissulescu Cc: fbedard@synopsys.com, vgupta@synopsys.com Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Back port for gcc10 The adc/sbc patterns were unecessary spliting, remove that and associated functions. gcc/ 2020-12-11 Claudiu Zissulescu * config/arc/arc-protos.h (arc_scheduling_not_expected): Remove it. (arc_sets_cc_p): Likewise. (arc_need_delay): Likewise. * config/arc/arc.c (arc_sets_cc_p): Likewise. (arc_need_delay): Likewise. (arc_scheduling_not_expected): Likewise. * config/arc/arc.md: Convert adc/sbc patterns to simple instruction definitions. Signed-off-by: Claudiu Zissulescu (cherry picked from commit dfbe642c97f7f430926cb6b33cd5c20b42c85573) --- gcc/config/arc/arc-protos.h | 3 -- gcc/config/arc/arc.c | 53 --------------------- gcc/config/arc/arc.md | 95 +++++++++++-------------------------- 3 files changed, 29 insertions(+), 122 deletions(-) diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h index c72d78e3b9e..de4cf47c818 100644 --- a/gcc/config/arc/arc-protos.h +++ b/gcc/config/arc/arc-protos.h @@ -90,10 +90,7 @@ extern void split_subsi (rtx *); extern void arc_split_move (rtx *); extern const char *arc_short_long (rtx_insn *insn, const char *, const char *); extern rtx arc_regno_use_in (unsigned int, rtx); -extern bool arc_scheduling_not_expected (void); -extern bool arc_sets_cc_p (rtx_insn *insn); extern int arc_label_align (rtx_insn *label); -extern bool arc_need_delay (rtx_insn *insn); extern bool arc_text_label (rtx_insn *insn); extern bool arc_short_comparison_p (rtx, int); diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index 6b96c5e4bf5..7902940c16c 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -10291,59 +10291,6 @@ arc_attr_type (rtx_insn *insn) return get_attr_type (insn); } -/* Return true if insn sets the condition codes. */ - -bool -arc_sets_cc_p (rtx_insn *insn) -{ - if (NONJUMP_INSN_P (insn)) - if (rtx_sequence *seq = dyn_cast (PATTERN (insn))) - insn = seq->insn (seq->len () - 1); - return arc_attr_type (insn) == TYPE_COMPARE; -} - -/* Return true if INSN is an instruction with a delay slot we may want - to fill. */ - -bool -arc_need_delay (rtx_insn *insn) -{ - rtx_insn *next; - - if (!flag_delayed_branch) - return false; - /* The return at the end of a function needs a delay slot. */ - if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE - && (!(next = next_active_insn (insn)) - || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE) - && arc_attr_type (next) == TYPE_RETURN)) - && (!TARGET_PAD_RETURN - || (prev_active_insn (insn) - && prev_active_insn (prev_active_insn (insn)) - && prev_active_insn (prev_active_insn (prev_active_insn (insn)))))) - return true; - if (NONJUMP_INSN_P (insn) - ? (GET_CODE (PATTERN (insn)) == USE - || GET_CODE (PATTERN (insn)) == CLOBBER - || GET_CODE (PATTERN (insn)) == SEQUENCE) - : JUMP_P (insn) - ? (GET_CODE (PATTERN (insn)) == ADDR_VEC - || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC) - : !CALL_P (insn)) - return false; - return num_delay_slots (insn) != 0; -} - -/* Return true if the scheduling pass(es) has/have already run, - i.e. where possible, we should try to mitigate high latencies - by different instruction selection. */ - -bool -arc_scheduling_not_expected (void) -{ - return cfun->machine->arc_reorg_started; -} - /* Code has a minimum p2 alignment of 1, which we must restore after an ADDR_DIFF_VEC. */ diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index a7f4056c7af..398034d361e 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2824,43 +2824,25 @@ (define_insn "*add_f_2" (set_attr "type" "compare") (set_attr "length" "4,4,8")]) -; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end -; needlessly prioritizing the matching constraint. -; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional -; execution is used where possible. -(define_insn_and_split "adc" - [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w") - (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0)) - (match_operand:SI 1 "nonmemory_operand" - "%c,0,c,0,cCal")) - (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))] +(define_insn "adc" + [(set (match_operand:SI 0 "register_operand" "=r, r,r,r, r,r") + (plus:SI + (plus:SI + (ltu:SI (reg:CC_C CC_REG) (const_int 0)) + (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r")) + (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I, r,Cal")))] "register_operand (operands[1], SImode) || register_operand (operands[2], SImode)" "@ - adc %0,%1,%2 - add.cs %0,%1,1 - adc %0,%1,%2 - adc %0,%1,%2 - adc %0,%1,%2" - ; if we have a bad schedule after sched2, split. - "reload_completed - && !optimize_size && (!TARGET_ARC600_FAMILY) - && arc_scheduling_not_expected () - && arc_sets_cc_p (prev_nonnote_insn (insn)) - /* If next comes a return or other insn that needs a delay slot, - expect the adc to get into the delay slot. */ - && next_nonnote_insn (insn) - && !arc_need_delay (next_nonnote_insn (insn)) - /* Restore operands before emitting. */ - && (extract_insn_cached (insn), 1)" - [(set (match_dup 0) (match_dup 3)) - (cond_exec - (ltu (reg:CC_C CC_REG) (const_int 0)) - (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))))] - "operands[3] = simplify_gen_binary (PLUS, SImode, operands[1], operands[2]);" + adc\\t%0,%1,%2 + add.cs\\t%0,%1,1 + adc\\t%0,%1,%2 + adc\\t%0,%1,%2 + adc\\t%0,%1,%2 + adc\\t%0,%1,%2" [(set_attr "cond" "use") (set_attr "type" "cc_arith") - (set_attr "length" "4,4,4,4,8")]) + (set_attr "length" "4,4,4,4,8,8")]) ; combiner-splitter cmp / scc -> cmp / adc (define_split @@ -2992,7 +2974,7 @@ (define_expand "subdi3" DONE; } emit_insn (gen_sub_f (l0, l1, l2)); - emit_insn (gen_sbc (h0, h1, h2, gen_rtx_REG (CCmode, CC_REG))); + emit_insn (gen_sbc (h0, h1, h2)); DONE; ") @@ -3007,44 +2989,25 @@ (define_insn "*sbc_0" (set_attr "type" "cc_arith") (set_attr "length" "4")]) -; w/c/c comes first (rather than Rcw/0/C_0) to prevent the middle-end -; needlessly prioritizing the matching constraint. -; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional execution -; is used where possible. -(define_insn_and_split "sbc" - [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w") - (minus:SI (minus:SI (match_operand:SI 1 "nonmemory_operand" - "c,0,c,0,cCal") - (ltu:SI (match_operand:CC_C 3 "cc_use_register") - (const_int 0))) - (match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))] +(define_insn "sbc" + [(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r,r,r") + (minus:SI + (minus:SI + (match_operand:SI 1 "nonmemory_operand" "r, 0,r,0, r,Cal") + (ltu:SI (reg:CC_C CC_REG) (const_int 0))) + (match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I,Cal,r")))] "register_operand (operands[1], SImode) || register_operand (operands[2], SImode)" "@ - sbc %0,%1,%2 - sub.cs %0,%1,1 - sbc %0,%1,%2 - sbc %0,%1,%2 - sbc %0,%1,%2" - ; if we have a bad schedule after sched2, split. - "reload_completed - && !optimize_size && (!TARGET_ARC600_FAMILY) - && arc_scheduling_not_expected () - && arc_sets_cc_p (prev_nonnote_insn (insn)) - /* If next comes a return or other insn that needs a delay slot, - expect the adc to get into the delay slot. */ - && next_nonnote_insn (insn) - && !arc_need_delay (next_nonnote_insn (insn)) - /* Restore operands before emitting. */ - && (extract_insn_cached (insn), 1)" - [(set (match_dup 0) (match_dup 4)) - (cond_exec - (ltu (reg:CC_C CC_REG) (const_int 0)) - (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1))))] - "operands[4] = simplify_gen_binary (MINUS, SImode, operands[1], operands[2]);" + sbc\\t%0,%1,%2 + sub.cs\\t%0,%1,1 + sbc\\t%0,%1,%2 + sbc\\t%0,%1,%2 + sbc\\t%0,%1,%2 + sbc\\t%0,%1,%2" [(set_attr "cond" "use") (set_attr "type" "cc_arith") - (set_attr "length" "4,4,4,4,8")]) + (set_attr "length" "4,4,4,4,8,8")]) (define_insn "sub_f" [(set (reg:CC CC_REG)