From patchwork Sun Jan 3 22:06:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Sutter X-Patchwork-Id: 1421963 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nwl.cc Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D8CVR68Xrz9sVR for ; Mon, 4 Jan 2021 09:05:03 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id EF58F82483; Sun, 3 Jan 2021 23:04:41 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nwl.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 7A81F8263F; Sun, 3 Jan 2021 23:04:38 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from orbyte.nwl.cc (orbyte.nwl.cc [IPv6:2001:41d0:e:133a::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C9A2A82409 for ; Sun, 3 Jan 2021 23:04:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nwl.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=phil@nwl.cc Received: from localhost ([::1]:60820 helo=base) by orbyte.nwl.cc with esmtp (Exim 4.94) (envelope-from ) id 1kwBUI-0007cv-BE; Sun, 03 Jan 2021 23:04:34 +0100 From: Phil Sutter To: u-boot@lists.denx.de Cc: Stefan Roese Subject: [PATCH 2/3] pci: Make auto-config code a little more robust Date: Sun, 3 Jan 2021 23:06:45 +0100 Message-Id: <20210103220646.26707-3-phil@nwl.cc> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210103220646.26707-1-phil@nwl.cc> References: <20210103220646.26707-1-phil@nwl.cc> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean On my DS414, some PCI devices return odd values when probing BAR sizes. An obvious case is all-ones response, the Linux driver (drivers/pci/probe.c) catches those explicitly and a comment explains that either bit 0 or bit 1 must be clear (depending on MEM or IO type). Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break size calculation due to the "middle" zeroes. Mitigate that copying more or less what Linux does and do a "find least bit set". Signed-off-by: Phil Sutter Reviewed-by: Stefan Roese Reviewed-by: Simon Glass --- drivers/pci/pci_auto.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index 3f46b7697d7ca..ea202b0e0959e 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -47,16 +47,17 @@ void dm_pciauto_setup_device(struct udevice *dev, int bars_num, dm_pci_write_config32(dev, bar, 0xffffffff); dm_pci_read_config32(dev, bar, &bar_response); - /* If BAR is not implemented go to the next BAR */ - if (!bar_response) + /* If BAR is not implemented (or invalid) go to the next BAR */ + if (!bar_response || bar_response == 0xffffffff) continue; found_mem64 = 0; /* Check the BAR type and set our address mask */ if (bar_response & PCI_BASE_ADDRESS_SPACE) { - bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK)) - & 0xffff) + 1; + bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK; + bar_size &= ~(bar_size - 1); + if (!enum_only) bar_res = io; From patchwork Sun Jan 3 22:06:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Sutter X-Patchwork-Id: 1421964 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=nwl.cc Received: from phobos.denx.de (unknown [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4D8CVt1S09z9sVR for ; Mon, 4 Jan 2021 09:05:24 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6513C82652; Sun, 3 Jan 2021 23:04:43 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nwl.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 32DEE82483; Sun, 3 Jan 2021 23:04:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_NONE autolearn=ham autolearn_force=no version=3.4.2 Received: from orbyte.nwl.cc (orbyte.nwl.cc [IPv6:2001:41d0:e:133a::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 14FFF823D3 for ; Sun, 3 Jan 2021 23:04:34 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=nwl.cc Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=phil@nwl.cc Received: from localhost ([::1]:60814 helo=base) by orbyte.nwl.cc with esmtp (Exim 4.94) (envelope-from ) id 1kwBUH-0007cq-Ig; Sun, 03 Jan 2021 23:04:33 +0100 From: Phil Sutter To: u-boot@lists.denx.de Cc: Stefan Roese Subject: [PATCH 3/3] pci: pci_mvebu: Define an IO region as well Date: Sun, 3 Jan 2021 23:06:46 +0100 Message-Id: <20210103220646.26707-4-phil@nwl.cc> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210103220646.26707-1-phil@nwl.cc> References: <20210103220646.26707-1-phil@nwl.cc> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Configure an IO region and window for PNP identical to how MEM region is set up. Linux does this only if the DT defines a pcie-io-aperture property for the SOC, but since all supported boards do this should not be needed. Signed-off-by: Phil Sutter Reviewed-by: Stefan Roese --- drivers/pci/pci_mvebu.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index c9afe7515014d..9528e7c40ecfe 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -73,6 +73,7 @@ struct mvebu_pcie { void __iomem *membase; struct resource mem; void __iomem *iobase; + struct resource io; u32 port; u32 lane; int devfn; @@ -81,6 +82,8 @@ struct mvebu_pcie { char name[16]; unsigned int mem_target; unsigned int mem_attr; + unsigned int io_target; + unsigned int io_attr; }; /* @@ -90,6 +93,7 @@ struct mvebu_pcie { */ static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE; #define PCIE_MEM_SIZE (128 << 20) +static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE; static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie) { @@ -306,12 +310,24 @@ static int mvebu_pcie_probe(struct udevice *dev) (u32)pcie->mem.start, PCIE_MEM_SIZE); } + pcie->io.start = (u32)mvebu_pcie_iobase; + pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1; + mvebu_pcie_iobase += MBUS_PCI_IO_SIZE; + + if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr, + (phys_addr_t)pcie->io.start, + MBUS_PCI_IO_SIZE)) { + printf("PCIe unable to add mbus window for IO at %08x+%08x\n", + (u32)pcie->io.start, MBUS_PCI_IO_SIZE); + } + /* Setup windows and configure host bridge */ mvebu_pcie_setup_wins(pcie); /* Master + slave enable. */ reg = readl(pcie->base + PCIE_CMD_OFF); reg |= PCI_COMMAND_MEMORY; + reg |= PCI_COMMAND_IO; reg |= PCI_COMMAND_MASTER; reg |= BIT(10); /* disable interrupts */ writel(reg, pcie->base + PCIE_CMD_OFF); @@ -323,7 +339,9 @@ static int mvebu_pcie_probe(struct udevice *dev) 0, 0, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - hose->region_count = 2; + pci_set_region(hose->regions + 2, pcie->io.start, + pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO); + hose->region_count = 3; /* Set BAR0 to internal registers */ writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); @@ -442,6 +460,14 @@ static int mvebu_pcie_ofdata_to_platdata(struct udevice *dev) goto err; } + ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn, + IORESOURCE_IO, + &pcie->io_target, &pcie->io_attr); + if (ret < 0) { + printf("%s: cannot get tgt/attr for IO window\n", pcie->name); + goto err; + } + /* Parse PCIe controller register base from DT */ ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie); if (ret < 0)