From patchwork Tue Dec 8 21:46:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pat Haugen X-Patchwork-Id: 1413047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gcc.gnu.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.a=rsa-sha256 header.s=default header.b=kNSGM90z; dkim-atps=neutral Received: from sourceware.org (unknown [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CrDKN6GfDz9sVs for ; Wed, 9 Dec 2020 08:46:47 +1100 (AEDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2E2243861001; Tue, 8 Dec 2020 21:46:40 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2E2243861001 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1607464000; bh=lJGZfezyxBz19d8n5QWmvylLpcLoXm2m1oURmdXCd24=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=kNSGM90z4x5cJwewN/noUlvRkPDs0xQxBw6bvfiOfEmqcwcbq+nf5AzGotuKWDliG tqqKgl1QYKG9x+KNSQpWBofZj48w7hG4DITLJ4ENuFRPCH+STATvjtPhh5B62+S+N6 4YFiRcz3BhXIk//uNbp8eLntX51oCPT6NIOvzCVk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 6328D3861001 for ; Tue, 8 Dec 2020 21:46:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6328D3861001 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0B8LaGne151795; Tue, 8 Dec 2020 16:46:36 -0500 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 35afetktf5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Dec 2020 16:46:35 -0500 Received: from m0098414.ppops.net (m0098414.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 0B8Lb0ji156083; Tue, 8 Dec 2020 16:46:35 -0500 Received: from ppma03dal.us.ibm.com (b.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.11]) by mx0b-001b2d01.pphosted.com with ESMTP id 35afetktey-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Dec 2020 16:46:35 -0500 Received: from pps.filterd (ppma03dal.us.ibm.com [127.0.0.1]) by ppma03dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 0B8LaSUi017554; Tue, 8 Dec 2020 21:46:35 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma03dal.us.ibm.com with ESMTP id 3581u99cnh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 08 Dec 2020 21:46:34 +0000 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0B8LkXsV21430766 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 8 Dec 2020 21:46:33 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4857A6A051; Tue, 8 Dec 2020 21:46:33 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6CC3E6A04D; Tue, 8 Dec 2020 21:46:32 +0000 (GMT) Received: from [9.65.207.150] (unknown [9.65.207.150]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 8 Dec 2020 21:46:32 +0000 (GMT) To: GCC Patches Subject: [PATCH, rs6000] Update "size" attribute for Power10 Message-ID: Date: Tue, 8 Dec 2020 15:46:31 -0600 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.4.3 MIME-Version: 1.0 Content-Language: en-US X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-08_15:2020-12-08, 2020-12-08 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 adultscore=0 phishscore=0 mlxlogscore=999 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012080129 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Pat Haugen via Gcc-patches From: Pat Haugen Reply-To: Pat Haugen Cc: Bill Schmidt , David Edelsohn , Segher Boessenkool Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" Update size attribute for Power10. This patch was broken out from my larger patch to update various attributes for Power10, in order to make the review process hopefully easier. This patch only updates the size attribute for various new instructions. There were no changes requested to this portion of the original patch, so nothing is new here. Bootstrap/regtest on powerpc64le (Power8/Power10) with no new regressions. Ok for trunk? -Pat 2020-11-08 Pat Haugen gcc/ * config/rs6000/dfp.md (extendddtd2, trunctddd2, *cmp_internal1, floatditd2, ftrunc2, fixdi2, dfp_ddedpd_, dfp_denbcd_, dfp_dxex_, dfp_diex_, *dfp_sgnfcnc_, dfp_dscli_, dfp_dscri_): Update size attribute for Power10. * config/rs6000/mma.md (*movoo): Likewise. * config/rs6000/rs6000.md (define_attr "size"): Add 256. (define_mode_attr bits): Add DD/TD modes. * config/rs6000/sync.md (load_quadpti, store_quadpti, load_lockedpti, store_conditionalpti): Update size attribute for Power10. diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md index 9a952300cd6..7562e63a919 100644 --- a/gcc/config/rs6000/dfp.md +++ b/gcc/config/rs6000/dfp.md @@ -139,7 +139,8 @@ (define_insn "extendddtd2" (float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dctqpq %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "128")]) ;; The result of drdpq is an even/odd register pair with the converted ;; value in the even register and zero in the odd register. @@ -153,6 +154,7 @@ (define_insn "trunctddd2" "TARGET_DFP" "drdpq %2,%1\;fmr %0,%2" [(set_attr "type" "dfp") + (set_attr "size" "128") (set_attr "length" "8")]) (define_insn "trunctdsd2" @@ -206,7 +208,8 @@ (define_insn "*cmp_internal1" (match_operand:DDTD 2 "gpc_reg_operand" "d")))] "TARGET_DFP" "dcmpu %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "floatdidd2" [(set (match_operand:DD 0 "gpc_reg_operand" "=d") @@ -220,7 +223,8 @@ (define_insn "floatditd2" (float:TD (match_operand:DI 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dcffixq %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "128")]) ;; Convert a decimal64/128 to a decimal64/128 whose value is an integer. ;; This is the first stage of converting it to an integer type. @@ -230,7 +234,8 @@ (define_insn "ftrunc2" (fix:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "drintn. 0,%0,%1,1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) ;; Convert a decimal64/128 whose value is an integer to an actual integer. ;; This is the second stage of converting decimal float to integer type. @@ -240,7 +245,8 @@ (define_insn "fixdi2" (fix:DI (match_operand:DDTD 1 "gpc_reg_operand" "d")))] "TARGET_DFP" "dctfix %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) ;; Decimal builtin support @@ -262,7 +268,8 @@ (define_insn "dfp_ddedpd_" UNSPEC_DDEDPD))] "TARGET_DFP" "ddedpd %1,%0,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_denbcd_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -271,7 +278,8 @@ (define_insn "dfp_denbcd_" UNSPEC_DENBCD))] "TARGET_DFP" "denbcd %1,%0,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_denbcd_v16qi_inst" [(set (match_operand:TD 0 "gpc_reg_operand" "=d") @@ -301,7 +309,8 @@ (define_insn "dfp_dxex_" UNSPEC_DXEX))] "TARGET_DFP" "dxex %0,%1" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_diex_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -310,7 +319,8 @@ (define_insn "dfp_diex_" UNSPEC_DXEX))] "TARGET_DFP" "diex %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_expand "dfptstsfi__" [(set (match_dup 3) @@ -349,7 +359,8 @@ (define_insn "*dfp_sgnfcnc_" operands[1] = GEN_INT (63); return "dtstsfi %0,%1,%2"; } - [(set_attr "type" "fp")]) + [(set_attr "type" "fp") + (set_attr "size" "")]) (define_insn "dfp_dscli_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -358,7 +369,8 @@ (define_insn "dfp_dscli_" UNSPEC_DSCLI))] "TARGET_DFP" "dscli %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) (define_insn "dfp_dscri_" [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d") @@ -367,4 +379,5 @@ (define_insn "dfp_dscri_" UNSPEC_DSCRI))] "TARGET_DFP" "dscri %0,%1,%2" - [(set_attr "type" "dfp")]) + [(set_attr "type" "dfp") + (set_attr "size" "")]) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index 4d291c42f7a..5768a8998e2 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -288,6 +288,7 @@ (define_insn_and_split "*movoo" DONE; } [(set_attr "type" "vecload,vecstore,veclogical") + (set_attr "size" "256,256,*") (set_attr "length" "*,*,8")]) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b89990f46bf..9bd55e7e107 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -209,7 +209,7 @@ (define_attr "type" ;; What data size does this instruction work on? ;; This is used for insert, mul and others as necessary. -(define_attr "size" "8,16,32,64,128" (const_string "32")) +(define_attr "size" "8,16,32,64,128,256" (const_string "32")) ;; What is the insn_cost for this insn? The target hook can still override ;; this. For optimizing for size the "length" attribute is used instead. @@ -670,7 +670,8 @@ (define_mode_attr du_or_d [(QI "du") ;; How many bits in this mode? (define_mode_attr bits [(QI "8") (HI "16") (SI "32") (DI "64") - (SF "32") (DF "64")]) + (SF "32") (DF "64") + (DD "64") (TD "128")]) ; DImode bits (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) diff --git a/gcc/config/rs6000/sync.md b/gcc/config/rs6000/sync.md index 5ad88806818..b07b2e86aae 100644 --- a/gcc/config/rs6000/sync.md +++ b/gcc/config/rs6000/sync.md @@ -131,6 +131,7 @@ (define_insn "load_quadpti" && !reg_mentioned_p (operands[0], operands[1])" "lq %0,%1" [(set_attr "type" "load") + (set_attr "size" "128") (set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED") (const_string "yes") (const_string "no")))]) @@ -205,6 +206,7 @@ (define_insn "store_quadpti" "TARGET_SYNC_TI" "stq %1,%0" [(set_attr "type" "store") + (set_attr "size" "128") (set (attr "prefixed") (if_then_else (match_test "TARGET_PREFIXED") (const_string "yes") (const_string "no")))]) @@ -333,7 +335,8 @@ (define_insn "load_lockedpti" && !reg_mentioned_p (operands[0], operands[1]) && quad_int_reg_operand (operands[0], PTImode)" "lqarx %0,%y1" - [(set_attr "type" "load_l")]) + [(set_attr "type" "load_l") + (set_attr "size" "128")]) (define_insn "store_conditional" [(set (match_operand:CC 0 "cc_reg_operand" "=x") @@ -394,7 +397,8 @@ (define_insn "store_conditionalpti" (match_operand:PTI 2 "quad_int_reg_operand" "r"))] "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)" "stqcx. %2,%y1" - [(set_attr "type" "store_c")]) + [(set_attr "type" "store_c") + (set_attr "size" "128")]) (define_expand "atomic_compare_and_swap" [(match_operand:SI 0 "int_reg_operand") ;; bool out