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Fri, 4 Dec 2020 15:52:54 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 01/11] lib: sbi: Fix sbi_hart_switch_mode() for u-mode Date: Fri, 4 Dec 2020 21:22:14 +0530 Message-Id: <20201204155224.733188-2-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:52:51 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 8f4f70c2-721f-4778-86f9-08d8986ca937 X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:67; 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Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- lib/sbi/sbi_hart.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c index 30d8aef..fc86e9f 100644 --- a/lib/sbi/sbi_hart.c +++ b/lib/sbi/sbi_hart.c @@ -522,9 +522,11 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1, csr_write(CSR_SIE, 0); csr_write(CSR_SATP, 0); } else if (next_mode == PRV_U) { - csr_write(CSR_UTVEC, next_addr); - csr_write(CSR_USCRATCH, 0); - csr_write(CSR_UIE, 0); + if (misa_extension('N')) { + csr_write(CSR_UTVEC, next_addr); + csr_write(CSR_USCRATCH, 0); + csr_write(CSR_UIE, 0); + } } register unsigned long a0 asm("a0") = arg0; From patchwork Fri Dec 4 15:52:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411141 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 4 Dec 2020 15:52:57 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 02/11] lib: sbi: Fix typo in sbi_domain_finalize() Date: Fri, 4 Dec 2020 21:22:15 +0530 Message-Id: <20201204155224.733188-3-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:52:54 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 4b139cb6-a2e0-48a0-f78b-08d8986caaf2 X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:3631; 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Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- lib/sbi/sbi_domain.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c index d4b82fe..4c98a1b 100644 --- a/lib/sbi/sbi_domain.c +++ b/lib/sbi/sbi_domain.c @@ -404,12 +404,12 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid) dhart = dom->boot_hartid; /* Ignore if boot HART not possible for this domain */ - if (!sbi_hartmask_test_hart(i, dom->possible_harts)) + if (!sbi_hartmask_test_hart(dhart, dom->possible_harts)) continue; /* Ignore if boot HART assigned different domain */ if (sbi_hartid_to_domain(dhart) != dom || - !sbi_hartmask_test_hart(i, &dom->assigned_harts)) + !sbi_hartmask_test_hart(dhart, &dom->assigned_harts)) continue; /* Startup boot HART of domain */ From patchwork Fri Dec 4 15:52:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411144 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 4 Dec 2020 15:53:00 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 03/11] lib: sbi: Fix domain_count check in sbi_domain_finalize() Date: Fri, 4 Dec 2020 21:22:16 +0530 Message-Id: <20201204155224.733188-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:52:57 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: f8579598-8f61-4465-b793-08d8986cacd0 X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:3173; 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Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- lib/sbi/sbi_domain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c index 4c98a1b..ac920b8 100644 --- a/lib/sbi/sbi_domain.c +++ b/lib/sbi/sbi_domain.c @@ -371,7 +371,7 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid) * Ensure that we have room for Domain Index to * HART ID mapping */ - if (domain_count <= SBI_DOMAIN_MAX_INDEX) + if (SBI_DOMAIN_MAX_INDEX <= domain_count) return SBI_ENOSPC; /* Sanitize discovered domain */ From patchwork Fri Dec 4 15:52:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411147 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; 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Fri, 4 Dec 2020 15:53:03 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 04/11] lib: sbi: Auto start domain only if boot HART within limits Date: Fri, 4 Dec 2020 21:22:17 +0530 Message-Id: <20201204155224.733188-5-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:53:00 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7fa99006-1565-4653-3423-08d8986cae98 X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- lib/sbi/sbi_domain.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c index ac920b8..ecb098c 100644 --- a/lib/sbi/sbi_domain.c +++ b/lib/sbi/sbi_domain.c @@ -403,6 +403,10 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid) /* Domain boot HART */ dhart = dom->boot_hartid; + /* Ignore of boot HART is off limits */ + if (SBI_HARTMASK_MAX_BITS <= dhart) + continue; + /* Ignore if boot HART not possible for this domain */ if (!sbi_hartmask_test_hart(dhart, dom->possible_harts)) continue; From patchwork Fri Dec 4 15:52:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411145 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; 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Fri, 4 Dec 2020 15:53:06 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 05/11] include: sbi: Use lower bits for domain memory region permissions Date: Fri, 4 Dec 2020 21:22:18 +0530 Message-Id: <20201204155224.733188-6-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:53:03 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 38662392-0382-4dd8-c1ef-08d8986cb060 X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:1284; 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This helps us use same bit assignment for parsing domain memory region access permissions from device tree. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- include/sbi/sbi_domain.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/include/sbi/sbi_domain.h b/include/sbi/sbi_domain.h index 6f90b26..a7cb61e 100644 --- a/include/sbi/sbi_domain.h +++ b/include/sbi/sbi_domain.h @@ -39,8 +39,10 @@ struct sbi_domain_memregion { #define SBI_DOMAIN_MEMREGION_READABLE (1UL << 0) #define SBI_DOMAIN_MEMREGION_WRITEABLE (1UL << 1) #define SBI_DOMAIN_MEMREGION_EXECUTABLE (1UL << 2) -#define SBI_DOMAIN_MEMREGION_MMIO (1UL << 3) -#define SBI_DOMAIN_MEMREGION_MMODE (1UL << 4) +#define SBI_DOMAIN_MEMREGION_MMODE (1UL << 3) +#define SBI_DOMAIN_MEMREGION_ACCESS_MASK (0xfUL) + +#define SBI_DOMAIN_MEMREGION_MMIO (1UL << 31) unsigned long flags; }; From patchwork Fri Dec 4 15:52:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411146 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 4 Dec 2020 15:53:09 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 06/11] lib: sbi: Override domain boot HART when coldboot HART assigned to it Date: Fri, 4 Dec 2020 21:22:19 +0530 Message-Id: <20201204155224.733188-7-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:53:06 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d177366f-a2cb-4457-ca2f-08d8986cb21e X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:2399; 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This allows coldboot HART to continue boot sequence even when it is assigned to some non-root domain. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- lib/sbi/sbi_domain.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c index ecb098c..1b50604 100644 --- a/lib/sbi/sbi_domain.c +++ b/lib/sbi/sbi_domain.c @@ -395,6 +395,17 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid) &tdom->assigned_harts); hartid_to_domain_table[i] = dom; sbi_hartmask_set_hart(i, &dom->assigned_harts); + + /* + * If cold boot HART is assigned to this domain then + * override boot HART of this domain. + */ + if (i == cold_hartid && + dom->boot_hartid != cold_hartid) { + sbi_printf("Domain%d Boot HARTID forced to" + " %d\n", dom->index, cold_hartid); + dom->boot_hartid = cold_hartid; + } } } From patchwork Fri Dec 4 15:52:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411149 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 4 Dec 2020 15:53:12 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 07/11] lib: sbi: Add error prints in sbi_domain_finalize() Date: Fri, 4 Dec 2020 21:22:20 +0530 Message-Id: <20201204155224.733188-8-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:53:09 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: e7cc5627-fe3d-485a-31b9-08d8986cb3de X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:107; 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Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- lib/sbi/sbi_domain.c | 63 ++++++++++++++++++++++++++++++++++++-------- 1 file changed, 52 insertions(+), 11 deletions(-) diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c index 1b50604..639e016 100644 --- a/lib/sbi/sbi_domain.c +++ b/lib/sbi/sbi_domain.c @@ -174,19 +174,33 @@ static int sanitize_domain(const struct sbi_platform *plat, struct sbi_domain_memregion treg, *reg, *reg1; /* Check possible HARTs */ - if (!dom->possible_harts) + if (!dom->possible_harts) { + sbi_printf("%s: %s possible HART mask is NULL\n", + __func__, dom->name); return SBI_EINVAL; + } sbi_hartmask_for_each_hart(i, dom->possible_harts) { - if (sbi_platform_hart_invalid(plat, i)) + if (sbi_platform_hart_invalid(plat, i)) { + sbi_printf("%s: %s possible HART mask has invalid " + "hart %d\n", __func__, dom->name, i); return SBI_EINVAL; + } }; /* Check memory regions */ - if (!dom->regions) + if (!dom->regions) { + sbi_printf("%s: %s regions is NULL\n", + __func__, dom->name); return SBI_EINVAL; + } sbi_domain_for_each_memregion(dom, reg) { - if (!is_region_valid(reg)) + if (!is_region_valid(reg)) { + sbi_printf("%s: %s has invalid region base=0x%lx " + "order=%lu flags=0x%lx\n", __func__, + dom->name, reg->base, reg->order, + reg->flags); return SBI_EINVAL; + } } /* Count memory regions and check presence of firmware region */ @@ -199,8 +213,11 @@ static int sanitize_domain(const struct sbi_platform *plat, have_fw_reg = TRUE; count++; } - if (!have_fw_reg) + if (!have_fw_reg) { + sbi_printf("%s: %s does not have firmware region\n", + __func__, dom->name); return SBI_EINVAL; + } /* Sort the memory regions */ for (i = 0; i < (count - 1); i++) { @@ -208,8 +225,15 @@ static int sanitize_domain(const struct sbi_platform *plat, for (j = i + 1; j < count; j++) { reg1 = &dom->regions[j]; - if (is_region_conflict(reg1, reg)) + if (is_region_conflict(reg1, reg)) { + sbi_printf("%s: %s conflict between regions " + "(base=0x%lx order=%lu flags=0x%lx) and " + "(base=0x%lx order=%lu flags=0x%lx)\n", + __func__, dom->name, + reg->base, reg->order, reg->flags, + reg1->base, reg1->order, reg1->flags); return SBI_EINVAL; + } if (!is_region_before(reg1, reg)) continue; @@ -233,13 +257,19 @@ static int sanitize_domain(const struct sbi_platform *plat, * protect M-mode context and enforce checks on memory accesses. */ if (dom->next_mode != PRV_S && - dom->next_mode != PRV_U) + dom->next_mode != PRV_U) { + sbi_printf("%s: %s invalid next booting stage mode 0x%lx\n", + __func__, dom->name, dom->next_mode); return SBI_EINVAL; + } /* Check next address and next mode*/ if (!sbi_domain_check_addr(dom, dom->next_addr, dom->next_mode, - SBI_DOMAIN_EXECUTE)) + SBI_DOMAIN_EXECUTE)) { + sbi_printf("%s: %s next booting stage addres 0x%lx can't " + "execute\n", __func__, dom->name, dom->next_addr); return SBI_EINVAL; + } return 0; } @@ -371,13 +401,20 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid) * Ensure that we have room for Domain Index to * HART ID mapping */ - if (SBI_DOMAIN_MAX_INDEX <= domain_count) + if (SBI_DOMAIN_MAX_INDEX <= domain_count) { + sbi_printf("%s: No room for %s\n", + __func__, dom->name); return SBI_ENOSPC; + } /* Sanitize discovered domain */ rc = sanitize_domain(plat, dom); - if (rc) + if (rc) { + sbi_printf("%s: sanity checks failed for" + " %s (error %d)\n", __func__, + dom->name, rc); return rc; + } /* Assign index to domain */ dom->index = domain_count++; @@ -437,8 +474,12 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid) dom->next_addr, dom->next_mode, dom->next_arg1); - if (rc) + if (rc) { + sbi_printf("%s: failed to start boot HART %d" + " for %s (error %d)\n", __func__, + dhart, dom->name, rc); return rc; + } } } From patchwork Fri Dec 4 15:52:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411148 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; 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Fri, 4 Dec 2020 15:53:15 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 08/11] include: sbi: Add domains_init() platform operation Date: Fri, 4 Dec 2020 21:22:21 +0530 Message-Id: <20201204155224.733188-9-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:53:12 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 933d77d9-bf64-4786-39b5-08d8986cb5d0 X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:3631; 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The domains_init() is called late in the coldboot sequence from the sbi_domain_finalize() so sbi_printf() can be used by platform support to print errors/warnings at time of populating domains. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- include/sbi/sbi_platform.h | 16 ++++++++++++++++ lib/sbi/sbi_domain.c | 8 ++++++++ 2 files changed, 24 insertions(+) diff --git a/include/sbi/sbi_platform.h b/include/sbi/sbi_platform.h index ee72323..3681a78 100644 --- a/include/sbi/sbi_platform.h +++ b/include/sbi/sbi_platform.h @@ -91,6 +91,8 @@ struct sbi_platform_operations { */ int (*misa_get_xlen)(void); + /** Initialize (or populate) domains for the platform */ + int (*domains_init)(void); /** Get domain pointer for given HART id */ struct sbi_domain *(*domain_get)(u32 hartid); @@ -451,6 +453,20 @@ static inline int sbi_platform_misa_xlen(const struct sbi_platform *plat) return -1; } +/** + * Initialize (or populate) domains for the platform + * + * @param plat pointer to struct sbi_platform + * + * @return 0 on success and negative error code on failure + */ +static inline int sbi_platform_domains_init(const struct sbi_platform *plat) +{ + if (plat && sbi_platform_ops(plat)->domains_init) + return sbi_platform_ops(plat)->domains_init(); + return 0; +} + /** * Get domain pointer for given HART * diff --git a/lib/sbi/sbi_domain.c b/lib/sbi/sbi_domain.c index 639e016..1a3651b 100644 --- a/lib/sbi/sbi_domain.c +++ b/lib/sbi/sbi_domain.c @@ -375,6 +375,14 @@ int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid) struct sbi_domain *dom, *tdom; const struct sbi_platform *plat = sbi_platform_ptr(scratch); + /* Initialize domains for the platform */ + rc = sbi_platform_domains_init(plat); + if (rc) { + sbi_printf("%s: platform domains_init() failed (error %d)\n", + __func__, rc); + return rc; + } + /* Discover domains */ for (i = 0; i < SBI_HARTMASK_MAX_BITS; i++) { /* Ignore invalid HART */ From patchwork Fri Dec 4 15:52:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411150 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- docs/domain_support.md | 208 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 208 insertions(+) diff --git a/docs/domain_support.md b/docs/domain_support.md index 04989df..73931f1 100644 --- a/docs/domain_support.md +++ b/docs/domain_support.md @@ -104,3 +104,211 @@ Few noteworthy effects of a system partitioned into domains are as follows: only work if both HART A and HART B are assigned same domain * A HART running in S-mode or U-mode can only access memory based on the memory regions of the domain assigned to the HART + +Domain Device Tree Bindings +--------------------------- + +The OpenSBI domains can be described in the **device tree (DT) blob** (or +flattened device tree) passed to the OpenSBI firmwares by the previous +booting stage. This allows OpenSBI platform support to parse and populate +OpenSBI domains from the device tree blob (or flattened device tree). + +### Domain Configuration Node + +All OpenSBI domain description related DT nodes should be under the domain +configuration DT node. The **/chosen** DT node is the preferred parent of +the domain configuration DT node. + +The DT properties of a domain configuration DT node are as follows: + +* **compatible** (Mandatory) - The compatible string of the domain + configuration. This DT property should have value *"opensbi,domain,config"* + +### Domain Memory Region Node + +The domain memory region DT node describes details of a memory region and +can be pointed by multiple domain instance DT nodes. The access permissions +of the memory region are specified separately in domain instance node. + +The DT properties of a domain memory region DT node are as follows: + +* **compatible** (Mandatory) - The compatible string of the domain memory + region. This DT property should have value *"opensbi,domain,memregion"* +* **base** (Mandatory) - The base address of the domain memory region. This + DT property should have a **2 ^ order** aligned 64 bit address (i.e. two + DT cells). +* **order** (Mandatory) - The order of the domain memory region. This DT + property should have a 32 bit value (i.e. one DT cell) in the range + **3 <= order <= __riscv_xlen**. +* **mmio** (Optional) - A boolean flag representing whether the domain + memory region is a memory-mapped I/O (MMIO) region. +* **devices** (Optional) - The list of device DT node phandles for devices + which fall under this domain memory region. + +### Domain Instance Node + +The domain instance DT node describes set of possible HARTs, set of memory +regions, and other details of a domain instance. + +The DT properties of a domain instance DT node are as follows: + +* **compatible** (Mandatory) - The compatible string of the domain instance. + This DT property should have value *"opensbi,domain,instance"* +* **possible-harts** (Optional) - The list of CPU DT node phandles for the + the domain instance. This list represents the possible HARTs of the + domain instance. +* **regions** (Optional) - The list of domain memory region DT node phandle + and access permissions for the domain instance. Each list entry is a pair + of DT node phandle and access permissions. The access permissions are + represented as a 32bit bitmask having bits: **readable** (BIT[0]), + **writeable** (BIT[1]), **executable** (BIT[2]), and **m-mode** (BIT[3]). +* **boot-hart** (Optional) - The DT node phandle of the HART booting the + domain instance. If coldboot HART is assigned to the domain instance then + this DT property is ignored and the coldboot HART is assumed to be the + boot HART of the domain instance. +* **next-arg1** (Optional) - The 64 bit next booting stage arg1 for the + domain instance. If this DT property is not available and coldboot HART + is not assigned to the domain instance then **0x0** is used as default + value. If this DT property is not available and coldboot HART is assigned + to the domain instance then **next booting stage arg1 of coldboot HART** + is used as default value. +* **next-addr** (Optional) - The 64 bit next booting stage address for the + domain instance. If this DT property is not available and coldboot HART + is not assigned to the domain instance then **0x0** is used as default + value. If this DT property is not available and coldboot HART is assigned + to the domain instance then **next booting stage address of coldboot HART** + is used as default value. +* **next-mode** (Optional) - The 32 bit next booting stage mode for the + domain instance. The possible values of this DT property are: **0x1** + (s-mode), and **0x0** (u-mode). If this DT property is not available + and coldboot HART is not assigned to the domain instance then **0x1** + is used as default value. If this DT property is not available and + coldboot HART is assigned to the domain instance then **next booting + stage mode of coldboot HART** is used as default value. +* **system-reset-allowed** (Optional) - A boolean flag representing + whether the domain instance is allowed to do system reset. + +### Assigning HART To Domain Instance + +By default, all HARTs are assigned to **the ROOT domain**. The OpenSBI +platform support can provide the HART to domain instance assignment using +platform specific callback. + +The HART to domain instance assignment can be parsed from the device tree +using optional DT property **opensbi,domain** in each CPU DT node. The +value of DT property **opensbi,domain** is the DT phandle of the domain +instance DT node. If **opensbi,domain** DT property is not specified then +corresponding HART is assigned to **the ROOT domain**. + +### Domain Configuration Only Accessible to OpenSBI + +The software running inside a domain instance should only be aware of +devices and hardware resources accessible to itself. + +To hide domain configuration from domain instances, the following should +be done: + +* The previous booting stage should preferably provide a separate device + tree for each domain instance and mention location of device tree in + respective domain instance DT nodes using **next-arg1** DT property. +* If domain assigned to a HART does not have separate device tree then + OpenSBI platform support should remove all domain configuration details + from the device tree passed by previous booting stage before passing it + to the next booting stage. + +### Example + +``` + chosen { + opensbi-domains { + compatible = "opensbi,domain,config"; + + tmem: tmem { + compatible = "opensbi,domain,memregion"; + base = <0x0 0x80100000>; + order = <20>; + }; + + tuart: tuart { + compatible = "opensbi,domain,memregion"; + base = <0x0 0x10011000>; + order = <12>; + mmio; + devices = <&uart1>; + }; + + allmem: allmem { + compatible = "opensbi,domain,memregion"; + base = <0x0 0x0>; + order = <64>; + }; + + tdomain: trusted-domain { + compatible = "opensbi,domain,instance"; + possible-harts = <&cpu0>; + regions = <&tmem 0x7>, <&tuart 0x7>; + boot-hart = <&cpu0>; + next-arg1 = <0x0 0x0>; + next-addr = <0x0 0x80100000>; + next-mode = <0x0>; + system-reset-allowed; + }; + + udomain: untrusted-domain { + compatible = "opensbi,domain,instance"; + possible-harts = <&cpu1 &cpu2 &cpu3 &cpu4>; + regions = <&tmem 0x0>, <&tuart 0x0>, <&allmem 0x7>; + }; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <10000000>; + + cpu0: cpu@0 { + device_type = "cpu"; + reg = <0x00>; + compatible = "riscv"; + opensbi-domain = <&tdomain>; + ... + }; + + cpu1: cpu@1 { + device_type = "cpu"; + reg = <0x01>; + compatible = "riscv"; + opensbi-domain = <&udomain>; + ... + }; + + cpu2: cpu@2 { + device_type = "cpu"; + reg = <0x02>; + compatible = "riscv"; + opensbi-domain = <&udomain>; + ... + }; + + cpu3: cpu@3 { + device_type = "cpu"; + reg = <0x03>; + compatible = "riscv"; + opensbi-domain = <&udomain>; + ... + }; + + cpu4: cpu@4 { + device_type = "cpu"; + reg = <0x04>; + compatible = "riscv"; + opensbi-domain = <&udomain>; + ... + }; + }; + + uart1: serial@10011000 { + ... + }; +``` From patchwork Fri Dec 4 15:52:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411151 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; 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These helper routines can be used by platform support code and FDT fixup code. Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- include/sbi_utils/fdt/fdt_domain.h | 80 ++++++ lib/utils/fdt/fdt_domain.c | 445 +++++++++++++++++++++++++++++ lib/utils/fdt/objects.mk | 1 + 3 files changed, 526 insertions(+) create mode 100644 include/sbi_utils/fdt/fdt_domain.h create mode 100644 lib/utils/fdt/fdt_domain.c diff --git a/include/sbi_utils/fdt/fdt_domain.h b/include/sbi_utils/fdt/fdt_domain.h new file mode 100644 index 0000000..3c02d56 --- /dev/null +++ b/include/sbi_utils/fdt/fdt_domain.h @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * fdt_domain.c - Flat Device Tree Domain helper routines + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __FDT_DOMAIN_H__ +#define __FDT_DOMAIN_H__ + +#include + +struct sbi_domain; + +/** + * Iterate over each domains in device tree + * + * @param fdt device tree blob + * @param opaque private pointer for each iteration + * @param fn callback function for each iteration + */ +void fdt_iterate_each_domain(void *fdt, void *opaque, + void (*fn)(void *fdt, int domain_offset, + void *opaque)); + +/** + * Iterate over each memregion of a domain in device tree + * + * @param fdt device tree blob + * @param domain_offset domain DT node offset + * @param opaque private pointer for each iteration + * @param fn callback function for each iteration + */ +void fdt_iterate_each_memregion(void *fdt, int domain_offset, void *opaque, + void (*fn)(void *fdt, int domain_offset, + int region_offset, u32 region_access, + void *opaque)); + +/** + * Fix up the domain configuration in the device tree + * + * This routine: + * 1. Disables MMIO devices not accessible to the coldboot HART domain + * 2. Removes "opensbi-domain" DT property from CPU DT nodes + * 3. Removes domain configuration DT node under /chosen DT node + * + * It is recommended that platform support call this function in + * their final_init() platform operation. + * + * @param fdt device tree blob + */ +void fdt_domain_fixup(void *fdt); + +/** + * Get domain instance for given HART + * + * Note: Domains should be populated before using this function. + * + * @param hartid the HART for which domain instance is needed + * + * @return pointer to domain instance on success and NULL on failure + */ +struct sbi_domain *fdt_domain_get(u32 hartid); + +/** + * Populate domains from device tree + * + * It is recommended that platform support call this function in + * their domains_init() platform operation. + * + * @param fdt device tree blob + * + * @return 0 on success and negative error code on failure + */ +int fdt_domains_populate(void *fdt); + +#endif /* __FDT_DOMAIN_H__ */ diff --git a/lib/utils/fdt/fdt_domain.c b/lib/utils/fdt/fdt_domain.c new file mode 100644 index 0000000..972a1f4 --- /dev/null +++ b/lib/utils/fdt/fdt_domain.c @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * fdt_domain.c - Flat Device Tree Domain helper routines + * + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include +#include +#include +#include +#include +#include + +void fdt_iterate_each_domain(void *fdt, void *opaque, + void (*fn)(void *fdt, int domain_offset, + void *opaque)) +{ + int doffset, poffset; + + if (!fdt || !fn) + return; + + poffset = fdt_path_offset(fdt, "/chosen"); + if (poffset < 0) + return; + poffset = fdt_node_offset_by_compatible(fdt, poffset, + "opensbi,domain,config"); + if (poffset < 0) + return; + + fdt_for_each_subnode(doffset, fdt, poffset) { + if (fdt_node_check_compatible(fdt, doffset, + "opensbi,domain,instance")) + continue; + + fn(fdt, doffset, opaque); + } +} + +void fdt_iterate_each_memregion(void *fdt, int domain_offset, void *opaque, + void (*fn)(void *fdt, int domain_offset, + int region_offset, u32 region_access, + void *opaque)) +{ + u32 i, rcount; + int len, region_offset; + const u32 *regions; + + if (!fdt || (domain_offset < 0) || !fn) + return; + + if (fdt_node_check_compatible(fdt, domain_offset, + "opensbi,domain,instance")) + return; + + regions = fdt_getprop(fdt, domain_offset, "regions", &len); + if (!regions) + return; + + rcount = (u32)len / (sizeof(u32) * 2); + for (i = 0; i < rcount; i++) { + region_offset = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(regions[2 * i])); + if (region_offset < 0) + continue; + + if (fdt_node_check_compatible(fdt, region_offset, + "opensbi,domain,memregion")) + continue; + + fn(fdt, domain_offset, region_offset, + fdt32_to_cpu(regions[(2 * i) + 1]), opaque); + } +} + +struct __fixup_find_domain_offset_info { + const char *name; + int *doffset; +}; + +static void __fixup_find_domain_offset(void *fdt, int doff, void *p) +{ + struct __fixup_find_domain_offset_info *fdo = p; + + if (sbi_strcmp(fdo->name, fdt_get_name(fdt, doff, NULL))) + return; + + *fdo->doffset = doff; +} + +#define DISABLE_DEVICES_MASK (SBI_DOMAIN_MEMREGION_READABLE | \ + SBI_DOMAIN_MEMREGION_WRITEABLE | \ + SBI_DOMAIN_MEMREGION_EXECUTABLE) + +static void __fixup_count_disable_devices(void *fdt, int doff, int roff, + u32 perm, void *p) +{ + int len; + u32 *dcount = p; + + if (perm & DISABLE_DEVICES_MASK) + return; + + len = 0; + if (fdt_getprop(fdt, roff, "devices", &len)) + *dcount += len / sizeof(u32); +} + +static void __fixup_disable_devices(void *fdt, int doff, int roff, + u32 raccess, void *p) +{ + int i, len, coff; + const u32 *devices; + + if (raccess & DISABLE_DEVICES_MASK) + return; + + len = 0; + devices = fdt_getprop(fdt, roff, "devices", &len); + if (!devices) + return; + len = len / sizeof(u32); + + for (i = 0; i < len; i++) { + coff = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(devices[i])); + if (coff < 0) + continue; + + fdt_setprop_string(fdt, coff, "status", "disabled"); + } +} + +void fdt_domain_fixup(void *fdt) +{ + u32 i, dcount; + int err, poffset, doffset; + struct sbi_domain *dom = sbi_domain_thishart_ptr(); + struct __fixup_find_domain_offset_info fdo; + + /* Remove the domain assignment DT property from CPU DT nodes */ + poffset = fdt_path_offset(fdt, "/cpus"); + if (poffset < 0) + return; + fdt_for_each_subnode(doffset, fdt, poffset) { + err = fdt_parse_hart_id(fdt, doffset, &i); + if (err) + continue; + + fdt_nop_property(fdt, doffset, "opensbi-domain"); + } + + /* Skip device disable for root domain */ + if (!dom->index) + goto skip_device_disable; + + /* Find current domain DT node */ + doffset = -1; + fdo.name = dom->name; + fdo.doffset = &doffset; + fdt_iterate_each_domain(fdt, &fdo, __fixup_find_domain_offset); + if (doffset < 0) + goto skip_device_disable; + + /* Count current domain device DT nodes to be disabled */ + dcount = 0; + fdt_iterate_each_memregion(fdt, doffset, &dcount, + __fixup_count_disable_devices); + if (!dcount) + goto skip_device_disable; + + /* Expand FDT based on device DT nodes to be disabled */ + err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + dcount * 32); + if (err < 0) + return; + + /* Again find current domain DT node */ + doffset = -1; + fdo.name = dom->name; + fdo.doffset = &doffset; + fdt_iterate_each_domain(fdt, &fdo, __fixup_find_domain_offset); + if (doffset < 0) + goto skip_device_disable; + + /* Disable device DT nodes for current domain */ + fdt_iterate_each_memregion(fdt, doffset, NULL, + __fixup_disable_devices); +skip_device_disable: + + /* Remove the OpenSBI domain config DT node */ + poffset = fdt_path_offset(fdt, "/chosen"); + if (poffset < 0) + return; + poffset = fdt_node_offset_by_compatible(fdt, poffset, + "opensbi,domain,config"); + if (poffset < 0) + return; + fdt_nop_node(fdt, poffset); +} + +static struct sbi_domain *fdt_hartid_to_domain[SBI_HARTMASK_MAX_BITS]; + +#define FDT_DOMAIN_MAX_COUNT 8 +#define FDT_DOMAIN_REGION_MAX_COUNT 16 + +static u32 fdt_domains_count; +static struct sbi_domain fdt_domains[FDT_DOMAIN_MAX_COUNT]; +static struct sbi_hartmask fdt_masks[FDT_DOMAIN_MAX_COUNT]; +static struct sbi_domain_memregion + fdt_regions[FDT_DOMAIN_MAX_COUNT][FDT_DOMAIN_REGION_MAX_COUNT + 2]; + +struct sbi_domain *fdt_domain_get(u32 hartid) +{ + if (SBI_HARTMASK_MAX_BITS <= hartid) + return NULL; + return fdt_hartid_to_domain[hartid]; +} + +static void __fdt_parse_region(void *fdt, int domain_offset, + int region_offset, u32 region_access, + void *opaque) +{ + int len; + u32 val32; + u64 val64; + const u32 *val; + u32 *region_count = opaque; + struct sbi_domain_memregion *region; + + /* Find next region of the domain */ + if (FDT_DOMAIN_REGION_MAX_COUNT <= *region_count) + return; + region = &fdt_regions[fdt_domains_count][*region_count]; + + /* Read "base" DT property */ + val = fdt_getprop(fdt, region_offset, "base", &len); + if (!val && len >= 8) + return; + val64 = fdt32_to_cpu(val[0]); + val64 = (val64 << 32) | fdt32_to_cpu(val[1]); + region->base = val64; + + /* Read "order" DT property */ + val = fdt_getprop(fdt, region_offset, "order", &len); + if (!val && len >= 4) + return; + val32 = fdt32_to_cpu(*val); + if (val32 < 3 || __riscv_xlen < val32) + return; + region->order = val32; + + /* Read "mmio" DT property */ + region->flags = region_access & SBI_DOMAIN_MEMREGION_ACCESS_MASK; + if (fdt_get_property(fdt, region_offset, "mmio", NULL)) + region->flags |= SBI_DOMAIN_MEMREGION_MMIO; + + (*region_count)++; +} + +static void __fdt_parse_domain(void *fdt, int domain_offset, void *opaque) +{ + u32 val32; + u64 val64; + const u32 *val; + struct sbi_domain *dom; + struct sbi_hartmask *mask; + int i, err, len, cpu_offset; + int *cold_domain_offset = opaque; + struct sbi_domain_memregion *regions; + + /* Sanity check on maximum domains we can handle */ + if (FDT_DOMAIN_MAX_COUNT <= fdt_domains_count) + return; + dom = &fdt_domains[fdt_domains_count]; + mask = &fdt_masks[fdt_domains_count]; + regions = &fdt_regions[fdt_domains_count][0]; + + /* Read DT node name */ + sbi_strncpy(dom->name, fdt_get_name(fdt, domain_offset, NULL), + sizeof(dom->name)); + dom->name[sizeof(dom->name) - 1] = '\0'; + + /* Setup possible HARTs mask */ + SBI_HARTMASK_INIT(mask); + dom->possible_harts = mask; + val = fdt_getprop(fdt, domain_offset, "possible-harts", &len); + len = len / sizeof(u32); + if (val && len) { + for (i = 0; i < len; i++) { + cpu_offset = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(val[i])); + if (cpu_offset < 0) + continue; + + err = fdt_parse_hart_id(fdt, cpu_offset, &val32); + if (err) + continue; + + sbi_hartmask_set_hart(val32, mask); + } + } + + /* Setup memregions from DT */ + val32 = 0; + sbi_memset(regions, 0, + sizeof(*regions) * (FDT_DOMAIN_REGION_MAX_COUNT + 2)); + dom->regions = regions; + fdt_iterate_each_memregion(fdt, domain_offset, &val32, + __fdt_parse_region); + sbi_domain_memregion_initfw(®ions[val32]); + + /* Read "boot-hart" DT property */ + val32 = -1U; + val = fdt_getprop(fdt, domain_offset, "boot-hart", &len); + if (val && len >= 4) { + cpu_offset = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(*val)); + if (cpu_offset >= 0) + fdt_parse_hart_id(fdt, cpu_offset, &val32); + } else { + if (domain_offset == *cold_domain_offset) + val32 = current_hartid(); + } + dom->boot_hartid = val32; + + /* Read "next-arg1" DT property */ + val64 = 0; + val = fdt_getprop(fdt, domain_offset, "next-arg1", &len); + if (val && len >= 8) { + val64 = fdt32_to_cpu(val[0]); + val64 = (val64 << 32) | fdt32_to_cpu(val[1]); + } else { + if (domain_offset == *cold_domain_offset) + val64 = sbi_scratch_thishart_ptr()->next_arg1; + } + dom->next_arg1 = val64; + + /* Read "next-addr" DT property */ + val64 = 0; + val = fdt_getprop(fdt, domain_offset, "next-addr", &len); + if (val && len >= 8) { + val64 = fdt32_to_cpu(val[0]); + val64 = (val64 << 32) | fdt32_to_cpu(val[1]); + } else { + if (domain_offset == *cold_domain_offset) + val64 = sbi_scratch_thishart_ptr()->next_addr; + } + dom->next_addr = val64; + + /* Read "next-mode" DT property */ + val32 = 0x1; + val = fdt_getprop(fdt, domain_offset, "next-mode", &len); + if (val && len >= 4) { + val32 = fdt32_to_cpu(val[0]); + if (val32 != 0x0 && val32 != 0x1) + val32 = 0x1; + } else { + if (domain_offset == *cold_domain_offset) + val32 = sbi_scratch_thishart_ptr()->next_mode; + } + dom->next_mode = val32; + + /* Read "system-reset-allowed" DT property */ + if (fdt_get_property(fdt, domain_offset, + "system-reset-allowed", NULL)) + dom->system_reset_allowed = TRUE; + else + dom->system_reset_allowed = FALSE; + + /* Increment domains count */ + fdt_domains_count++; +} + +int fdt_domains_populate(void *fdt) +{ + const u32 *val; + int cold_domain_offset; + u32 i, hartid, cold_hartid; + int err, len, cpus_offset, cpu_offset, domain_offset; + + /* Sanity checks */ + if (!fdt) + return SBI_EINVAL; + + /* Find /cpus DT node */ + cpus_offset = fdt_path_offset(fdt, "/cpus"); + if (cpus_offset < 0) + return cpus_offset; + + /* Find coldboot HART domain DT node offset */ + cold_domain_offset = -1; + cold_hartid = current_hartid(); + fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) { + err = fdt_parse_hart_id(fdt, cpu_offset, &hartid); + if (err) + continue; + + if (hartid != cold_hartid) + continue; + + val = fdt_getprop(fdt, cpu_offset, "opensbi-domain", &len); + if (val && len >= 4) + cold_domain_offset = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(*val)); + + break; + } + + /* Iterate over each domain in FDT and populate details */ + fdt_iterate_each_domain(fdt, &cold_domain_offset, __fdt_parse_domain); + + /* HART to domain assignment based on CPU DT nodes*/ + fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) { + err = fdt_parse_hart_id(fdt, cpu_offset, &hartid); + if (err) + continue; + + if (SBI_HARTMASK_MAX_BITS <= hartid) + continue; + + val = fdt_getprop(fdt, cpu_offset, "opensbi-domain", &len); + if (!val || len < 4) + continue; + + domain_offset = fdt_node_offset_by_phandle(fdt, + fdt32_to_cpu(*val)); + if (domain_offset < 0) + continue; + + for (i = 0; i < fdt_domains_count; i++) { + if (!sbi_strcmp(fdt_domains[i].name, + fdt_get_name(fdt, domain_offset, NULL))) { + fdt_hartid_to_domain[hartid] = &fdt_domains[i]; + break; + } + } + } + + return 0; +} diff --git a/lib/utils/fdt/objects.mk b/lib/utils/fdt/objects.mk index b860a83..d9f1eae 100644 --- a/lib/utils/fdt/objects.mk +++ b/lib/utils/fdt/objects.mk @@ -4,5 +4,6 @@ # Copyright (C) 2020 Bin Meng # +libsbiutils-objs-y += fdt/fdt_domain.o libsbiutils-objs-y += fdt/fdt_helper.o libsbiutils-objs-y += fdt/fdt_fixup.o From patchwork Fri Dec 4 15:52:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1411152 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Fri, 4 Dec 2020 15:53:23 +0000 From: Anup Patel To: Atish Patra , Alistair Francis Subject: [PATCH v2 11/11] platform: generic: Populate domains from FDT Date: Fri, 4 Dec 2020 21:22:24 +0530 Message-Id: <20201204155224.733188-12-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201204155224.733188-1-anup.patel@wdc.com> References: <20201204155224.733188-1-anup.patel@wdc.com> X-Originating-IP: [103.15.57.100] X-ClientProxiedBy: PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) To DM6PR04MB6201.namprd04.prod.outlook.com (2603:10b6:5:127::32) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (103.15.57.100) by PN1PR0101CA0071.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:d::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Fri, 4 Dec 2020 15:53:21 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 1fe5ff07-ca99-4ce9-940c-08d8986cbad3 X-MS-TrafficTypeDiagnostic: DM6PR04MB3995: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:1247; 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Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- platform/generic/platform.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/platform/generic/platform.c b/platform/generic/platform.c index abb696a..6c93a51 100644 --- a/platform/generic/platform.c +++ b/platform/generic/platform.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -148,6 +149,7 @@ static int generic_final_init(bool cold_boot) fdt_cpu_fixup(fdt); fdt_fixups(fdt); + fdt_domain_fixup(fdt); if (generic_plat && generic_plat->fdt_fixup) { rc = generic_plat->fdt_fixup(fdt, generic_plat_match); @@ -170,6 +172,11 @@ static void generic_final_exit(void) generic_plat->final_exit(generic_plat_match); } +static int generic_domains_init(void) +{ + return fdt_domains_populate(sbi_scratch_thishart_arg1_ptr()); +} + static u64 generic_tlbr_flush_limit(void) { if (generic_plat && generic_plat->tlbr_flush_limit) @@ -202,6 +209,8 @@ const struct sbi_platform_operations platform_ops = { .final_init = generic_final_init, .early_exit = generic_early_exit, .final_exit = generic_final_exit, + .domains_init = generic_domains_init, + .domain_get = fdt_domain_get, .console_putc = fdt_serial_putc, .console_getc = fdt_serial_getc, .console_init = fdt_serial_init,