From patchwork Mon Jan 8 02:17:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856655 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="Hskahc9D"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFK4s07Mtz9s9Y for ; Mon, 8 Jan 2018 13:30:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754917AbeAHCSZ (ORCPT ); Sun, 7 Jan 2018 21:18:25 -0500 Received: from vern.gendns.com ([206.190.152.46]:50899 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754940AbeAHCSW (ORCPT ); Sun, 7 Jan 2018 21:18:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=mD3NAKH1wbYoqATF8hYwZG7pwcr0dvx5Y5spdi1FOYE=; b=Hskahc9DNMWF4lJFmorJM5gaw IRwhRwE436Zt3kwgLwqA3O9bVSudAuuvn1kFw0vhX79ApuRXl4DRUaFAwVe74pLPacu68uKjMqixF oAD6rMO00daFgFiajy7BPK7Oi5WDkTGVaa+dQmtybyrV0x8tlJzoYTSkJ82V6cOzSin4IcVGB+9ii aMWG9oogLW8F0PJErba6VhAHgsYgnJ0yAfRDxi/pyhFNxOhsPyOAxHZGRDEc4LTADNbbjLH+YsOue zF03Z8Lcc/a7EHUDVC2QKYTjAD/kl6XjQRYXtfscxkMbN706K1vb/PxGjQ1hwN3r67LgP9KxtUKDj 7Ce/rkSHA==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN0t-0009GR-Ry; Sun, 07 Jan 2018 21:18:12 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 01/44] dt-bindings: clock: Add new bindings for TI Davinci PLL clocks Date: Sun, 7 Jan 2018 20:17:00 -0600 Message-Id: <1515377863-20358-2-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for the PLL IP blocks in the mach-davinci family of processors. Currently, only the SYSCLKn and AUXCLK outputs are needed, but in the future additional child nodes could be added for OBSCLK and BPDIV. Note: Although these PLL controllers are very similar to the TI Keystone SoCs, we are not re-using those bindings. The Keystone bindings use a legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs have a slightly different PLL register layout and a number of quirks that can't be handled by the existing bindings, so the keystone bindings could not be used as-is anyway. Signed-off-by: David Lechner --- .../devicetree/bindings/clock/ti/davinci/pll.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/pll.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt new file mode 100644 index 0000000..99bf5da --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt @@ -0,0 +1,47 @@ +Binding for TI DaVinci PLL Controllers + +The PLL provides clocks to most of the components on the SoC. In addition +to the PLL itself, this controller also contains bypasses, gates, dividers, +an multiplexers for various clock signals. + +Required properties: +- compatible: shall be one of: + - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX + - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX +- reg: physical base address and size of the controller's register area. +- clocks: phandle to the PLL input clock source + +Optional child nodes: + +sysclk + Describes the PLLDIVn divider clocks that provide the SYSCLKn clock + domains. The node name must be "sysclk". Consumers of this node should + use "n" in "SYSCLKn" as the parameter for the clock cell. + + Required properties: + - #clock-cells: must be 1 + +auxclk + Describes the AUXCLK output of the PLL. The node name must be "auxclk". + + Required properties: + - #clock-cells: must be 0 + +Examples: + + pll0: clock-controller@11000 { + compatible = "ti,da850-pll0"; + reg = <0x11000 0x1000>; + clocks = <&ref_clk>; + + pll0_sysclk: sysclk { + #clock-cells = <1>; + }; + + pll0_aux_clk: auxclk { + #clock-cells = <0>; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt From patchwork Mon Jan 8 02:17:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856654 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="stch3kow"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFK3h6YbMz9s7h for ; Mon, 8 Jan 2018 13:29:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755390AbeAHC3W (ORCPT ); Sun, 7 Jan 2018 21:29:22 -0500 Received: from vern.gendns.com ([206.190.152.46]:50968 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755069AbeAHCSe (ORCPT ); Sun, 7 Jan 2018 21:18:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=joN3N1p31Xmk7D4e2wiBFGgJqw1XJx99h1n2UfegVgg=; b=stch3kowUDrM4Bd+pzZ01lt1Q lEPZzewBmWJj/lJj1bkQU3omcbCEwdp+3AJp4Yd3XkdO45DVW3thjqT6530XeX3myGhjFSYFulmXb DlQZa1k1M07mUXNlpphDzfExDWRRaGaGSr4y1V9QPT40dGvYQ0U5Wlod7CLvJwU2207SzclXEowyd E6yNwdXM05yjcjirT5i3QDYNOnxN0FmiwmPLKiAZvtciIyoPwrAkNMJflQ8g3J2dFceOTqo6yX7Ir NHGGmy6jvkFLGT2wuZlpeNwSFMqJwG0u3FAISPmBu8AuPmOsmm3VMvhLjmSJyZb2UJw5AYDZ9dYB4 3GxHsvbew==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN16-0009GR-Gx; Sun, 07 Jan 2018 21:18:24 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 09/44] dt-bindings: clock: New bindings for TI Davinci PSC Date: Sun, 7 Jan 2018 20:17:08 -0600 Message-Id: <1515377863-20358-10-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for the Power Sleep Controller (PSC) for the mach-davinci family of processors. Note: Although TI Keystone has a very similar PSC, we are not using the existing bindings. Keystone is using a legacy one-node-per-clock binding (actually two nodes if you count the separate reset binding for the same IP block). Also, some davinci LPSCs have quirks that aren't handled by the keystone bindings, so we would be adding one compatible string per clock with quirks instead of just a new compatible string for each controller. Signed-off-by: David Lechner Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/ti/davinci/psc.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/psc.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt new file mode 100644 index 0000000..83a9da5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt @@ -0,0 +1,47 @@ +Binding for TI DaVinci Power Sleep Controller (PSC) + +The PSC provides power management, clock gating and reset functionality. It is +primarily used for clocking. + +Required properties: +- compatible: shall be one of: + - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX + - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX +- reg: physical base address and size of the controller's register area. +- #clock-cells: from common clock binding; shall be set to 1. +- #reset-cells: from reset binding; shall be set to 1. + +Consumers: + + Clock and reset consumers shall use the local power domain module ID + (LPSC) as the index corresponding to the clock cell. Refer to the + device-specific datasheet to find these numbers. NB: Most local domains + only provide a clock and not a reset. + +Examples: + + psc0: clock-controller@10000 { + compatible = "ti,da850-psc0"; + reg = <0x10000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + /* consumer */ + dsp: dsp@11800000 { + compatible = "ti,da850-dsp"; + reg = <0x11800000 0x40000>, + <0x11e00000 0x8000>, + <0x11f00000 0x8000>, + <0x01c14044 0x4>, + <0x01c14174 0x8>; + reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig"; + interrupt-parent = <&intc>; + interrupts = <28>; + clocks = <&psc0 15>; + resets = <&psc0 15>; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt +- Documentation/devicetree/bindings/reset/reset.txt From patchwork Mon Jan 8 02:17:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856653 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="JnB0xRBl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFJw00JHhz9s7h for ; Mon, 8 Jan 2018 13:22:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754951AbeAHCWL (ORCPT ); Sun, 7 Jan 2018 21:22:11 -0500 Received: from vern.gendns.com ([206.190.152.46]:51034 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755136AbeAHCSr (ORCPT ); Sun, 7 Jan 2018 21:18:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=LLxHbzGidSottYKICT6WdNQxTHA0N7gpEwFZ4yIaRqM=; b=JnB0xRBlI2kTXrLaWKZoxQwTp Et00qB/WlG7/rwMdzYzh/oZxVe9MnInue0VJSEc2ksdL0Dz/Qv9ag1b8zbg0Yc0JMCiXExlqNHwsV b2KnSL/w3tt1HadIzerNYbgK/PsaHX3NoCpIyiwZNr776jDmzdJ7C65JwvVZ2027k5S+zd4TBZwux 1zLoNJUcLnT0BXMikC2g2kfGvcVnBxtDE+j4iq6p1Q9Hrur6XT0AvyB8BK3IjU+vFQsYcXT2qxQK9 u8stP0huOqFvfmmtF1H3dp9oSqluPkg08jIv8a6vNeD+P8CP3XHkZQrY12N0QTZzQWwq0DRDKWbuT hn+vJBdmw==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN1J-0009GR-Tw; Sun, 07 Jan 2018 21:18:38 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 17/44] dt-bindings: clock: Add bindings for DA8XX CFGCHIP gate clocks Date: Sun, 7 Jan 2018 20:17:16 -0600 Message-Id: <1515377863-20358-18-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for the gate clocks present in the CFGCHIP syscon registers in TI DA8XX SoCs. There are actually other gate clocks in this block that could be added in the future, but TBCLK is currently the only one being used. Signed-off-by: David Lechner --- .../clock/ti/davinci/da8xx-cfgchip-gate.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt new file mode 100644 index 0000000..55821b0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt @@ -0,0 +1,38 @@ +Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP gate clocks + +TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of +registers call CFGCHIPn. Some of these registers function as clock +gates. This document describes the bindings for those clocks. + +Required properties: +- compatible: shall be "ti,da830-tbclk". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandle to the parent clock + +Optional properties: +- clock-output-names: from common clock binding. + +Parent: +This node must be a child of a "ti,da830-cfgchip" node. + +Assignment: +The assigned-clocks and assigned-clock-parents from the common clock bindings +can be used to indicate which parent clock should be used. + +Examples: + + cfgchip: syscon@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + ehrpwm_tbclk: tbclk { + compatible = "ti,da830-tbclk"; + #clock-cells = <0>; + clocks = <&psc1 17>; + clock-output-names = "ehrpwm_tbclk"; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt + From patchwork Mon Jan 8 02:17:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856652 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="OfL/c7g2"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFJt92gJQz9s7h for ; Mon, 8 Jan 2018 13:21:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755172AbeAHCS4 (ORCPT ); Sun, 7 Jan 2018 21:18:56 -0500 Received: from vern.gendns.com ([206.190.152.46]:51043 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754923AbeAHCSu (ORCPT ); Sun, 7 Jan 2018 21:18:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=10ZKAtq9+5Hx42gcGz7ZxqSF7c4ltrffaLItmgY+U54=; b=OfL/c7g24sVSUzTnsOQ+B2KoK PHZiQzqPRpAHxVMEOVvpjl5qDx50IJYbwa3jW1655iQFldBema9dYaZx1jYN6cSqh55yCxSf/qWUt MxsShuxRn4lhg+xR4Of7XsNit56GKcRlHUpx7sIvHhUSuJJfD0wbFhcu1sq+LZ9s3p4pMQga443Uf haZ40VbAF8X3FdzECM0uNT8IUr5qKtgPkIcIJjIsb9m+KgKhTZWdckh1US3WMuyj8ShUZSwTgWSUT eskRKuJ9OvV2UWH1pavXOYJmVwjtDDmNV2Dz+4Ce+CX7317oduOG2xBkunRilY5M38cCHVqZM0X7B RTMwLbHug==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN1L-0009GR-DH; Sun, 07 Jan 2018 21:18:39 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 18/44] dt-bindings: clock: Add binding for TI DA8XX CFGCHIP mux clocks Date: Sun, 7 Jan 2018 20:17:17 -0600 Message-Id: <1515377863-20358-19-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for multiplexer clocks that are part of the CFGCHIPn registers on TI DA8XX-like SoCs. Currently, there are only bindings given for the ASYNC3 clock domain, but there are additional clock multiplexers in this syscon that could be added in the future if needed. Signed-off-by: David Lechner --- .../clock/ti/davinci/da8xx-cfgchip-mux.txt | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt new file mode 100644 index 0000000..8c874ad --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt @@ -0,0 +1,42 @@ +Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP multiplexer clocks + +TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of +registers call CFGCHIPn. Some of these registers function as clock +multiplexers. This document describes the bindings for those clocks. + +Required properties: +- compatible: shall be "ti,da850-async3-clock". +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandle list of clocks corresponding to clock-names +- clock-names: must include the following: "pll0_sysclk2", "pll1_sysclk2". + +Optional properties: +- clock-output-names: from common clock binding. + +Parent: +This node must be a child of a "ti,da830-cfgchip" node. + +Assignment: +The assigned-clocks and assigned-clock-parents from the common clock bindings +can be used to indicate which parent clock should be used. + +Examples: + + cfgchip: syscon@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + async3_clk: async3 { + compatible = "ti,da850-async3-clock"; + #clock-cells = <0>; + clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>; + clock-names = "pll0_sysclk2", "pll1_sysclk2"; + assigned-clocks = <&async3_clk>; + assigned-clock-parents = <&pll1_sysclk 2>; + clock-output-names = "async3"; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt + From patchwork Mon Jan 8 02:17:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Lechner X-Patchwork-Id: 856651 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=lechnology.com header.i=@lechnology.com header.b="JqIYE059"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFJsp1hwlz9s7h for ; Mon, 8 Jan 2018 13:21:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755179AbeAHCS5 (ORCPT ); Sun, 7 Jan 2018 21:18:57 -0500 Received: from vern.gendns.com ([206.190.152.46]:51059 "EHLO vern.gendns.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754998AbeAHCSw (ORCPT ); Sun, 7 Jan 2018 21:18:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lechnology.com; s=default; h=References:In-Reply-To:Message-Id:Date:Subject :Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=RdM6gW7w7COmD9NX+HOZzvdnedYJn1tAgvq6upUKK1o=; b=JqIYE059befmK3QnSEST7pXNB qkP0wbBO9OrcFHMPpk0xY7/g1Xt9ADjxENJJvCp00gKbfwG2vT2ijgpOG4xCpcLFQWKvYR04iN4EY hg39+kQid38aGcpkoSYoPvEivkyt3s5DLFui+9PkG9sBxZM5296XuHsbJ8kLxyEE/CaCR+qNAcT2D Kjm6gY43hMTgSVSmEYKo5b6DXDkEHuBBUf9/rLqqxwhpmpr4OamaNvaX7DIRc13HOjbG/odSv/a/4 d4g/GHI5AlS4tPWIh1blL2LUV1ySaHFrkezcnfJmIorTScoucs8R5EUELbYID1pSmZ/Ana3qNyUnw 8Bwd3clUA==; Received: from 108-198-5-147.lightspeed.okcbok.sbcglobal.net ([108.198.5.147]:53904 helo=freyr.lechnology.com) by vern.gendns.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES128-SHA256:128) (Exim 4.89) (envelope-from ) id 1eYN1O-0009GR-WF; Sun, 07 Jan 2018 21:18:43 -0500 From: David Lechner To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Sekhar Nori , Kevin Hilman , Adam Ford , linux-kernel@vger.kernel.org, David Lechner Subject: [PATCH v5 20/44] dt-bindings: clock: Add bindings for TI DA8XX USB PHY clocks Date: Sun, 7 Jan 2018 20:17:19 -0600 Message-Id: <1515377863-20358-21-git-send-email-david@lechnology.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com> References: <1515377863-20358-1-git-send-email-david@lechnology.com> X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - vern.gendns.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - lechnology.com X-Get-Message-Sender-Via: vern.gendns.com: authenticated_id: davidmain+lechnology.com/only user confirmed/virtual account not confirmed X-Authenticated-Sender: vern.gendns.com: davidmain@lechnology.com X-Source: X-Source-Args: X-Source-Dir: Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a new binding for TI DA8XX USB PHY clocks. These clocks are part of a syscon register called CFGCHIP3. Signed-off-by: David Lechner --- .../clock/ti/davinci/da8xx-cfgchip-usb-phy.txt | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-usb-phy.txt diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-usb-phy.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-usb-phy.txt new file mode 100644 index 0000000..8a12e1b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-usb-phy.txt @@ -0,0 +1,55 @@ +Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP USB PHY clocks + +TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of +registers call CFGCHIPn. Some of these registers function as the USB PHY +clocks. This document describes the bindings for those clocks. + +Required properties: +- compatible: shall be one of: + - "ti,da830-usb0-phy-clock" for the USB 2.0 PHY + - "ti,da830-usb1-phy-clock" for the USB 1.1 PHY +- #clock-cells: from common clock binding; shall be set to 0. +- clocks: phandle list of clocks corresponding to clock-names +- clock-names: depends on compatible: + - for "ti,da830-usb0-phy-clock" must be "usb_refclkin", "auxclk", + "usb0_lpsc" + - for "ti,da830-usb1-phy-clock" must be "usb0_phy", "usb_refclkin" + +Optional properties: +- clock-output-names: from common clock binding. + +Parent: + This node must be a child of a "ti,da830-cfgchip" node. + +Assignment: + The assigned-clocks and assigned-clock-parents properties from the + common clock bindings can be used to indicate which parent clock should + be used. Note: for "ti,da830-usb0-phy-clock", only "usb_refclkin" or + "auxclk" can be used as the assigned parent clock ("usb0_lpsc" is not + an actual parent clock and only used internally). + +Examples: + + cfgchip: syscon@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + usb0_phy_clk: usb0-phy-clock { + compatible = "ti,da830-usb0-phy-clock"; + #clock-cells = <0>; + clocks = <&usb_refclkin>, <&pll0_aux_clk>, <&psc1 1>; + clock-names = "usb_refclkin", "auxclk", "usb0_lpsc"; + clock-output-names = "usb0_phy_clk"; + }; + + usb1_phy_clk: usb1-phy-clock { + compatible = "ti,da830-usb1-phy-clock"; + #clock-cells = <0>; + clocks = <&usb0_phy_clk>, <&usb_refclkin>; + clock-names = "usb0_phy", "usb_refclkin"; + clock-output-names = "usb1_phy_clk"; + }; + }; + +Also see: +- Documentation/devicetree/bindings/clock/clock-bindings.txt