From patchwork Wed Dec 2 09:14:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1409535 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=EG8IO6nS; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CmCxX37v6z9sSf for ; Wed, 2 Dec 2020 20:15:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388108AbgLBJPR (ORCPT ); Wed, 2 Dec 2020 04:15:17 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11492 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388089AbgLBJPQ (ORCPT ); Wed, 2 Dec 2020 04:15:16 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 02 Dec 2020 01:14:36 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 2 Dec 2020 09:14:35 +0000 Received: from moonraker.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 2 Dec 2020 09:14:33 +0000 From: Jon Hunter To: "Rafael J . Wysocki" , Viresh Kumar , Thierry Reding CC: , , Sumit Gupta , Jon Hunter Subject: [PATCH 1/4] cpufreq: tegra186: Fix sparse 'incorrect type in assignment' warning Date: Wed, 2 Dec 2020 09:14:16 +0000 Message-ID: <20201202091419.307192-2-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201202091419.307192-1-jonathanh@nvidia.com> References: <20201202091419.307192-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606900476; bh=rDHwvdixeWVuXBgVI8gIlWkmg2C+zDn3XtJjk9Rlc+U=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=EG8IO6nSQHb3gW7HsRU3gukjn2Hi2j2Kcl922MiAhtJ3A6c59g0EC2dXonqzGJw0r g+Zhbq2UlZjwlYR2vJZ2/JQ1jeg6JOzXtVJZ095DqEijuVsWy20yGNVKyPLZq8Rs0J fO3QFdNbdEPXh+e27SqiQ8+rNe8oEh4MA4KX78hgicP1pBL/ID42WMyOQ3NRO6tGin 5Bauk0ioHgmSn4If9G/Wsxs/lZYT894vN6XZhXr9ufRFSpouWeBw0SciEDPK/oi35S bqiUCFzxd8H4MPjJ7cvMT4FUxxgZ3NpUBDrMbUFv7a3ds8oB0icJQhP3z3+g6AgXzk lFURsBglOaIYg== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Sparse warns that the incorrect type is being assigned to the CPUFREQ driver_data variable in the Tegra186 CPUFREQ driver. The Tegra186 CPUFREQ driver is assigned a type of 'void __iomem *' to a pointer of type 'void *' ... drivers/cpufreq/tegra186-cpufreq.c:72:37: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected void *driver_data @@ got void [noderef] __iomem * @@ ... drivers/cpufreq/tegra186-cpufreq.c:87:40: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected void [noderef] __iomem *edvd_reg @@ got void *driver_data @@ The Tegra186 CPUFREQ driver is using the policy->driver_data variable to store and iomem pointer to a Tegra186 CPU register that is used to set the clock speed for the CPU. This is not necessary because the register base address is already stored in the driver data and the offset of the register for each CPU is static. Therefore, fix this by adding a new structure with the register offsets for each CPU and store this in the main driver data structure along with the register base address. Please note that a new structure has been added for storing the register offsets rather than a simple array, because this will permit further clean-ups and simplification of the driver. Signed-off-by: Jon Hunter --- drivers/cpufreq/tegra186-cpufreq.c | 61 ++++++++++++++++++++++-------- 1 file changed, 46 insertions(+), 15 deletions(-) diff --git a/drivers/cpufreq/tegra186-cpufreq.c b/drivers/cpufreq/tegra186-cpufreq.c index 7eb2c56c65de..98b5f32eb0be 100644 --- a/drivers/cpufreq/tegra186-cpufreq.c +++ b/drivers/cpufreq/tegra186-cpufreq.c @@ -12,13 +12,45 @@ #include #include -#define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4) -#define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 -#define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff -#define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 +#define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4)) +#define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4)) +#define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 +#define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff +#define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 + +struct tegra186_cpufreq_cpu { + unsigned int edvd_offset; +}; + +static const struct tegra186_cpufreq_cpu tegra186_cpus[] = { + /* CPU0 - A57 Cluster */ + { + .edvd_offset = EDVD_OFFSET_A57(0) + }, + /* CPU1 - Denver Cluster */ + { + .edvd_offset = EDVD_OFFSET_DENVER(0) + }, + /* CPU2 - Denver Cluster */ + { + .edvd_offset = EDVD_OFFSET_DENVER(1) + }, + /* CPU3 - A57 Cluster */ + { + .edvd_offset = EDVD_OFFSET_A57(1) + }, + /* CPU4 - A57 Cluster */ + { + .edvd_offset = EDVD_OFFSET_A57(2) + }, + /* CPU5 - A57 Cluster */ + { + .edvd_offset = EDVD_OFFSET_A57(3) + }, + +}; struct tegra186_cpufreq_cluster_info { - unsigned long offset; int cpus[4]; unsigned int bpmp_cluster_id; }; @@ -27,13 +59,11 @@ struct tegra186_cpufreq_cluster_info { static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = { /* Denver cluster */ { - .offset = SZ_64K * 7, .cpus = { 1, 2, NO_CPU, NO_CPU }, .bpmp_cluster_id = 0, }, /* A57 cluster */ { - .offset = SZ_64K * 6, .cpus = { 0, 3, 4, 5 }, .bpmp_cluster_id = 1, }, @@ -51,6 +81,7 @@ struct tegra186_cpufreq_data { size_t num_clusters; struct tegra186_cpufreq_cluster *clusters; + const struct tegra186_cpufreq_cpu *cpus; }; static int tegra186_cpufreq_init(struct cpufreq_policy *policy) @@ -71,13 +102,12 @@ static int tegra186_cpufreq_init(struct cpufreq_policy *policy) if (core == ARRAY_SIZE(info->cpus)) continue; - policy->driver_data = - data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core); policy->freq_table = cluster->table; break; } policy->cpuinfo.transition_latency = 300 * 1000; + policy->driver_data = NULL; return 0; } @@ -85,11 +115,12 @@ static int tegra186_cpufreq_init(struct cpufreq_policy *policy) static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { + struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); struct cpufreq_frequency_table *tbl = policy->freq_table + index; - void __iomem *edvd_reg = policy->driver_data; + unsigned int edvd_offset = data->cpus[policy->cpu].edvd_offset; u32 edvd_val = tbl->driver_data; - writel(edvd_val, edvd_reg); + writel(edvd_val, data->regs + edvd_offset); return 0; } @@ -98,16 +129,15 @@ static unsigned int tegra186_cpufreq_get(unsigned int cpu) { struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); struct cpufreq_policy *policy; - void __iomem *edvd_reg; - unsigned int i, freq = 0; + unsigned int i, edvd_offset, freq = 0; u32 ndiv; policy = cpufreq_cpu_get(cpu); if (!policy) return 0; - edvd_reg = policy->driver_data; - ndiv = readl(edvd_reg) & EDVD_CORE_VOLT_FREQ_F_MASK; + edvd_offset = data->cpus[policy->cpu].edvd_offset; + ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK; for (i = 0; i < data->num_clusters; i++) { struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; @@ -240,6 +270,7 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev) return -ENOMEM; data->num_clusters = ARRAY_SIZE(tegra186_clusters); + data->cpus = tegra186_cpus; bpmp = tegra_bpmp_get(&pdev->dev); if (IS_ERR(bpmp)) From patchwork Wed Dec 2 09:14:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1409536 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=IjEUYh9p; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CmCxX5shWz9sPB for ; Wed, 2 Dec 2020 20:15:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388116AbgLBJPT (ORCPT ); Wed, 2 Dec 2020 04:15:19 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:14450 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388113AbgLBJPS (ORCPT ); Wed, 2 Dec 2020 04:15:18 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 02 Dec 2020 01:14:38 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 2 Dec 2020 09:14:38 +0000 Received: from moonraker.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 2 Dec 2020 09:14:36 +0000 From: Jon Hunter To: "Rafael J . Wysocki" , Viresh Kumar , Thierry Reding CC: , , Sumit Gupta , Jon Hunter Subject: [PATCH 2/4] cpufreq: tegra186: Simplify cluster information lookup Date: Wed, 2 Dec 2020 09:14:17 +0000 Message-ID: <20201202091419.307192-3-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201202091419.307192-1-jonathanh@nvidia.com> References: <20201202091419.307192-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606900478; bh=uI21NQ7JlylRAxWbg5pP4myRc1s7fFIpA6E+rzDNIuM=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=IjEUYh9pHDYj6XS1VkW+XCMDuYt5Etd2XZepudOzUNJY5dtCDHYO9jBr8DCb3Mt8w b0Gw/eEyrstrF43/I8uL77DclLanhxLZ5i+++18ulZCljk2XM5TJlPNtMwZCEUWOmH KfRb3Wd9/dXnjTal+0f3O8fpKwgAYewxhGShrJEMVcS2T3rchcggukFAk/RjQCKF1+ 6VncT+eaGImn+2I7NDWys64LW4dB0fUBaN+mZoGeaa6d5JrT1bkrK7/ffx2GMuGhC4 GFpcXWsQkhDX7HDV5G7HI0mv8+9irpY0/jPro6oopjZdYE8IKvZDvV+sBJo5IjzSpQ +SS6g9aJkU2gg== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The CPUFREQ driver framework references each individual CPUs when getting and setting the speed. Tegra186 has 3 clusters of A57 CPUs and 1 cluster of Denver CPUs. Hence, the Tegra186 CPUFREQ driver need to know which cluster a given CPU belongs to. The logic in the Tegra186 driver can be greatly simplified by storing the cluster ID associated with each CPU in the tegra186_cpufreq_cpu structure. This allow us to completely remove the Tegra cluster info structure from the driver and simplifiy the code. Signed-off-by: Jon Hunter --- drivers/cpufreq/tegra186-cpufreq.c | 85 +++++++----------------------- 1 file changed, 20 insertions(+), 65 deletions(-) diff --git a/drivers/cpufreq/tegra186-cpufreq.c b/drivers/cpufreq/tegra186-cpufreq.c index 98b5f32eb0be..e566ea298b59 100644 --- a/drivers/cpufreq/tegra186-cpufreq.c +++ b/drivers/cpufreq/tegra186-cpufreq.c @@ -12,6 +12,7 @@ #include #include +#define TEGRA186_NUM_CLUSTERS 2 #define EDVD_OFFSET_A57(core) ((SZ_64K * 6) + (0x20 + (core) * 0x4)) #define EDVD_OFFSET_DENVER(core) ((SZ_64K * 7) + (0x20 + (core) * 0x4)) #define EDVD_CORE_VOLT_FREQ_F_SHIFT 0 @@ -19,58 +20,44 @@ #define EDVD_CORE_VOLT_FREQ_V_SHIFT 16 struct tegra186_cpufreq_cpu { + unsigned int bpmp_cluster_id; unsigned int edvd_offset; }; static const struct tegra186_cpufreq_cpu tegra186_cpus[] = { /* CPU0 - A57 Cluster */ { + .bpmp_cluster_id = 1, .edvd_offset = EDVD_OFFSET_A57(0) }, /* CPU1 - Denver Cluster */ { + .bpmp_cluster_id = 0, .edvd_offset = EDVD_OFFSET_DENVER(0) }, /* CPU2 - Denver Cluster */ { + .bpmp_cluster_id = 0, .edvd_offset = EDVD_OFFSET_DENVER(1) }, /* CPU3 - A57 Cluster */ { + .bpmp_cluster_id = 1, .edvd_offset = EDVD_OFFSET_A57(1) }, /* CPU4 - A57 Cluster */ { + .bpmp_cluster_id = 1, .edvd_offset = EDVD_OFFSET_A57(2) }, /* CPU5 - A57 Cluster */ { - .edvd_offset = EDVD_OFFSET_A57(3) - }, - -}; - -struct tegra186_cpufreq_cluster_info { - int cpus[4]; - unsigned int bpmp_cluster_id; -}; - -#define NO_CPU -1 -static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = { - /* Denver cluster */ - { - .cpus = { 1, 2, NO_CPU, NO_CPU }, - .bpmp_cluster_id = 0, - }, - /* A57 cluster */ - { - .cpus = { 0, 3, 4, 5 }, .bpmp_cluster_id = 1, + .edvd_offset = EDVD_OFFSET_A57(3) }, }; struct tegra186_cpufreq_cluster { - const struct tegra186_cpufreq_cluster_info *info; struct cpufreq_frequency_table *table; u32 ref_clk_khz; u32 div; @@ -78,8 +65,6 @@ struct tegra186_cpufreq_cluster { struct tegra186_cpufreq_data { void __iomem *regs; - - size_t num_clusters; struct tegra186_cpufreq_cluster *clusters; const struct tegra186_cpufreq_cpu *cpus; }; @@ -87,25 +72,9 @@ struct tegra186_cpufreq_data { static int tegra186_cpufreq_init(struct cpufreq_policy *policy) { struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); - unsigned int i; - - for (i = 0; i < data->num_clusters; i++) { - struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; - const struct tegra186_cpufreq_cluster_info *info = - cluster->info; - int core; - - for (core = 0; core < ARRAY_SIZE(info->cpus); core++) { - if (info->cpus[core] == policy->cpu) - break; - } - if (core == ARRAY_SIZE(info->cpus)) - continue; - - policy->freq_table = cluster->table; - break; - } + unsigned int cluster = data->cpus[policy->cpu].bpmp_cluster_id; + policy->freq_table = data->clusters[cluster].table; policy->cpuinfo.transition_latency = 300 * 1000; policy->driver_data = NULL; @@ -128,8 +97,9 @@ static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy, static unsigned int tegra186_cpufreq_get(unsigned int cpu) { struct tegra186_cpufreq_data *data = cpufreq_get_driver_data(); + struct tegra186_cpufreq_cluster *cluster; struct cpufreq_policy *policy; - unsigned int i, edvd_offset, freq = 0; + unsigned int edvd_offset, cluster_id; u32 ndiv; policy = cpufreq_cpu_get(cpu); @@ -138,24 +108,11 @@ static unsigned int tegra186_cpufreq_get(unsigned int cpu) edvd_offset = data->cpus[policy->cpu].edvd_offset; ndiv = readl(data->regs + edvd_offset) & EDVD_CORE_VOLT_FREQ_F_MASK; - - for (i = 0; i < data->num_clusters; i++) { - struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; - int core; - - for (core = 0; core < ARRAY_SIZE(cluster->info->cpus); core++) { - if (cluster->info->cpus[core] != policy->cpu) - continue; - - freq = (cluster->ref_clk_khz * ndiv) / cluster->div; - goto out; - } - } - -out: + cluster_id = data->cpus[policy->cpu].bpmp_cluster_id; + cluster = &data->clusters[cluster_id]; cpufreq_cpu_put(policy); - return freq; + return (cluster->ref_clk_khz * ndiv) / cluster->div; } static struct cpufreq_driver tegra186_cpufreq_driver = { @@ -171,7 +128,7 @@ static struct cpufreq_driver tegra186_cpufreq_driver = { static struct cpufreq_frequency_table *init_vhint_table( struct platform_device *pdev, struct tegra_bpmp *bpmp, - struct tegra186_cpufreq_cluster *cluster) + struct tegra186_cpufreq_cluster *cluster, unsigned int cluster_id) { struct cpufreq_frequency_table *table; struct mrq_cpu_vhint_request req; @@ -190,7 +147,7 @@ static struct cpufreq_frequency_table *init_vhint_table( memset(&req, 0, sizeof(req)); req.addr = phys; - req.cluster_id = cluster->info->bpmp_cluster_id; + req.cluster_id = cluster_id; memset(&msg, 0, sizeof(msg)); msg.mrq = MRQ_CPU_VHINT; @@ -264,12 +221,11 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev) if (!data) return -ENOMEM; - data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters), + data->clusters = devm_kcalloc(&pdev->dev, TEGRA186_NUM_CLUSTERS, sizeof(*data->clusters), GFP_KERNEL); if (!data->clusters) return -ENOMEM; - data->num_clusters = ARRAY_SIZE(tegra186_clusters); data->cpus = tegra186_cpus; bpmp = tegra_bpmp_get(&pdev->dev); @@ -282,11 +238,10 @@ static int tegra186_cpufreq_probe(struct platform_device *pdev) goto put_bpmp; } - for (i = 0; i < data->num_clusters; i++) { + for (i = 0; i < TEGRA186_NUM_CLUSTERS; i++) { struct tegra186_cpufreq_cluster *cluster = &data->clusters[i]; - cluster->info = &tegra186_clusters[i]; - cluster->table = init_vhint_table(pdev, bpmp, cluster); + cluster->table = init_vhint_table(pdev, bpmp, cluster, i); if (IS_ERR(cluster->table)) { err = PTR_ERR(cluster->table); goto put_bpmp; From patchwork Wed Dec 2 09:14:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1409537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=UG5XlU/I; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CmCxY1r5Mz9sSf for ; Wed, 2 Dec 2020 20:15:45 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388122AbgLBJPV (ORCPT ); Wed, 2 Dec 2020 04:15:21 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11497 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388031AbgLBJPU (ORCPT ); Wed, 2 Dec 2020 04:15:20 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 02 Dec 2020 01:14:40 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 2 Dec 2020 09:14:40 +0000 Received: from moonraker.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 2 Dec 2020 09:14:38 +0000 From: Jon Hunter To: "Rafael J . Wysocki" , Viresh Kumar , Thierry Reding CC: , , Sumit Gupta , Jon Hunter Subject: [PATCH 3/4] cpufreq: tegra194: Remove unnecessary frequency calculation Date: Wed, 2 Dec 2020 09:14:18 +0000 Message-ID: <20201202091419.307192-4-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201202091419.307192-1-jonathanh@nvidia.com> References: <20201202091419.307192-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606900480; bh=IIOwydvHQGBQsUl10GTUpD6i84b6O4uOJA62idcOqfM=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=UG5XlU/I37/BRSYzl4sOsuv3z5QZs1qq4HNgVJFxYLC+xBoV4PLQwsN5qSX1runGc buXruJ9eNLUmJODmT++YC0AyFLV/Ufd9qHZQlOxiPJj1+Qon2TodzxjYYxqomXrLUk RlKNbacorD5llMXHWh/cS9tkfcfhnrIDIvqbMtkA5ZyPcBUsfp1Wb2OMBUzy6mFg+Q FMm2hMLfaUskQhARdm+Q/fx7P13vDp6wVFHr0xylcUT0qGWGvrL2mcSnxM0R40RSLY aNt1daC797IwDazCxlkZTFypa6lYuc38bni7tA4C4nnw5CVsHXynlTRjII37jD5DXo bzGf986WEaThw== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra194 CPUFREQ driver sets the CPUFREQ_NEED_INITIAL_FREQ_CHECK flag which means that the CPUFREQ framework will call the 'get' callback on boot to determine the current frequency of the CPUs. Therefore, it is not necessary for the Tegra194 CPUFREQ driver to internally call the tegra194_get_speed_common() during initialisation to query the current frequency as well. Fix this by removing the call to the tegra194_get_speed_common() during initialisation and simplify the code. Signed-off-by: Jon Hunter --- drivers/cpufreq/tegra194-cpufreq.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c index 79015875f346..a706ba929424 100644 --- a/drivers/cpufreq/tegra194-cpufreq.c +++ b/drivers/cpufreq/tegra194-cpufreq.c @@ -21,7 +21,6 @@ #define KHZ 1000 #define REF_CLK_MHZ 408 /* 408 MHz */ #define US_DELAY 500 -#define US_DELAY_MIN 2 #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ) #define MAX_CNT ~0U @@ -44,7 +43,6 @@ struct tegra194_cpufreq_data { struct tegra_cpu_ctr { u32 cpu; - u32 delay; u32 coreclk_cnt, last_coreclk_cnt; u32 refclk_cnt, last_refclk_cnt; }; @@ -112,7 +110,7 @@ static void tegra_read_counters(struct work_struct *work) val = read_freq_feedback(); c->last_refclk_cnt = lower_32_bits(val); c->last_coreclk_cnt = upper_32_bits(val); - udelay(c->delay); + udelay(US_DELAY); val = read_freq_feedback(); c->refclk_cnt = lower_32_bits(val); c->coreclk_cnt = upper_32_bits(val); @@ -139,7 +137,7 @@ static void tegra_read_counters(struct work_struct *work) * @cpu - logical cpu whose freq to be updated * Returns freq in KHz on success, 0 if cpu is offline */ -static unsigned int tegra194_get_speed_common(u32 cpu, u32 delay) +static unsigned int tegra194_get_speed_common(u32 cpu) { struct read_counters_work read_counters_work; struct tegra_cpu_ctr c; @@ -153,7 +151,6 @@ static unsigned int tegra194_get_speed_common(u32 cpu, u32 delay) * interrupts enabled. */ read_counters_work.c.cpu = cpu; - read_counters_work.c.delay = delay; INIT_WORK_ONSTACK(&read_counters_work.work, tegra_read_counters); queue_work_on(cpu, read_counters_wq, &read_counters_work.work); flush_work(&read_counters_work.work); @@ -209,7 +206,7 @@ static unsigned int tegra194_get_speed(u32 cpu) smp_call_function_single(cpu, get_cpu_cluster, &cl, true); /* reconstruct actual cpu freq using counters */ - rate = tegra194_get_speed_common(cpu, US_DELAY); + rate = tegra194_get_speed_common(cpu); /* get last written ndiv value */ ret = smp_call_function_single(cpu, get_cpu_ndiv, &ndiv, true); @@ -248,9 +245,6 @@ static int tegra194_cpufreq_init(struct cpufreq_policy *policy) if (cl >= data->num_clusters) return -EINVAL; - /* boot freq */ - policy->cur = tegra194_get_speed_common(policy->cpu, US_DELAY_MIN); - /* set same policy for all cpus in a cluster */ for (cpu = (cl * 2); cpu < ((cl + 1) * 2); cpu++) cpumask_set_cpu(cpu, policy->cpus); From patchwork Wed Dec 2 09:14:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 1409539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=laPZy85I; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CmCxk6Gv5z9sPB for ; Wed, 2 Dec 2020 20:15:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387975AbgLBJPy (ORCPT ); Wed, 2 Dec 2020 04:15:54 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:11563 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387755AbgLBJPy (ORCPT ); Wed, 2 Dec 2020 04:15:54 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Wed, 02 Dec 2020 01:14:42 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 2 Dec 2020 09:14:42 +0000 Received: from moonraker.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Wed, 2 Dec 2020 09:14:40 +0000 From: Jon Hunter To: "Rafael J . Wysocki" , Viresh Kumar , Thierry Reding CC: , , Sumit Gupta , Jon Hunter Subject: [PATCH 4/4] cpufreq: tegra194: Rename tegra194_get_speed_common function Date: Wed, 2 Dec 2020 09:14:19 +0000 Message-ID: <20201202091419.307192-5-jonathanh@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201202091419.307192-1-jonathanh@nvidia.com> References: <20201202091419.307192-1-jonathanh@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606900482; bh=S8sJJMoQpyzSm2gQKsnuGora2uy6mUIWNJQuzPmFQqk=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=laPZy85I7Cdd2CB8DCAOXWVuNop35dgr7a2LLpT9X056I0HfG1Q1D6pExk58J4mTZ sEg7i87a28P120ORHRQhAaNrlmlWhh154yBrSWPxJV6ozwxskqYhEVslBjLnBZtFgc 6KtWnXY8aRbQYADy0YpjBf4adWxepYRQc7JdOrJiiy5/22CNChHZ8nqKmbe85gV5E0 pmwwpEzyGDlqbCWXr1dB3NDKRvz3Uc5wZwoPww/0pKuz99ORvOatPUATxGV60nswVt iH85DATGzD985xc9EHD6LaSWWzeOlX+GP9VCFZU2cNhJ9Gh9jQEbZRAvaD8TMB1QMF kVOQD4vLEop3w== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The function tegra194_get_speed_common() uses hardware timers to calculate the current CPUFREQ and so rename this function to be tegra194_calculate_speed() to reflect what it does. Signed-off-by: Jon Hunter --- drivers/cpufreq/tegra194-cpufreq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c index a706ba929424..6a67f36f3b80 100644 --- a/drivers/cpufreq/tegra194-cpufreq.c +++ b/drivers/cpufreq/tegra194-cpufreq.c @@ -137,7 +137,7 @@ static void tegra_read_counters(struct work_struct *work) * @cpu - logical cpu whose freq to be updated * Returns freq in KHz on success, 0 if cpu is offline */ -static unsigned int tegra194_get_speed_common(u32 cpu) +static unsigned int tegra194_calculate_speed(u32 cpu) { struct read_counters_work read_counters_work; struct tegra_cpu_ctr c; @@ -206,7 +206,7 @@ static unsigned int tegra194_get_speed(u32 cpu) smp_call_function_single(cpu, get_cpu_cluster, &cl, true); /* reconstruct actual cpu freq using counters */ - rate = tegra194_get_speed_common(cpu); + rate = tegra194_calculate_speed(cpu); /* get last written ndiv value */ ret = smp_call_function_single(cpu, get_cpu_ndiv, &ndiv, true);