From patchwork Mon Nov 23 20:17:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1405088 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=DL0dnBw7; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cfz4Z4LFDz9sVZ for ; Tue, 24 Nov 2020 07:18:38 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731102AbgKWURV (ORCPT ); Mon, 23 Nov 2020 15:17:21 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:11573 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730857AbgKWURT (ORCPT ); Mon, 23 Nov 2020 15:17:19 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 23 Nov 2020 12:17:22 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Nov 2020 20:17:19 +0000 Received: from skomatineni-linux.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 23 Nov 2020 20:17:18 +0000 From: Sowjanya Komatineni To: , , , CC: , , , , Subject: [PATCH v3 1/6] arm: tegra: Change order of SATA resets for Tegra124 Date: Mon, 23 Nov 2020 12:17:20 -0800 Message-ID: <1606162645-22326-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> References: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606162642; bh=dsJaMW2E8x66lSobB5W6JfCyLdlUss/7lLoDgCHhcrA=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=DL0dnBw79rcFy6VlWnZsJ9TRi7DlZ3P2zNOlRZivGPwfpzmzgV6lzw4Y+YdIzBowx z3W734KQdM4ga6/h0rN5HPOWK1scNTmpMoOuDfZL9o2pGZSF8Cs2EX+E/blvwq01xB PDOPTDDY6V7sLTc6up7toyG3aJSEFiIH/rTA/5D5kCMj04Uf1SBpfoQf47rNc5i9M2 bLntT+6PFMS+fhkw0nVY6FbaGL4ERCEWuXskDOAJ1X4yUB1JNj5zYgxOYlqpjt1iEI akWF0NpxB62vG7fGFvXSVJW5odf9d7F0bODYKZoReUxo3LT1zFd2Otr6ChKIyGR39w VkZPhR0fQgybA== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni --- arch/arm/boot/dts/tegra124.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d7001b2..e61e68a 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -650,9 +650,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; From patchwork Mon Nov 23 20:17:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1405092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=jJu20bAr; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cfz4f3tkdz9sT6 for ; Tue, 24 Nov 2020 07:18:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732417AbgKWURw (ORCPT ); Mon, 23 Nov 2020 15:17:52 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:2123 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731063AbgKWURU (ORCPT ); Mon, 23 Nov 2020 15:17:20 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 23 Nov 2020 12:17:26 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Nov 2020 20:17:20 +0000 Received: from skomatineni-linux.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 23 Nov 2020 20:17:19 +0000 From: Sowjanya Komatineni To: , , , CC: , , , , Subject: [PATCH v3 2/6] arm64: tegra: Change order of SATA resets for Tegra132 and Tegra210 Date: Mon, 23 Nov 2020 12:17:21 -0800 Message-ID: <1606162645-22326-3-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> References: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606162646; bh=zpLEidUhozh9F2rcxc6BWtGsrDvmZrZdbTb8XgzAZWc=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=jJu20bAr9iCxuk5oXpLqsI3uTqMC21ym90OrVf9DOuiOM1fTqhqe/boiOVPf0a8Be xCeKbrGKu7/bJ8Rb5GTxLxGCd4USlXQbRbBsPNxKjV5TG/VejPeMgMqKzr5u6lRUwN M7XeJiKOZ4Z6CulbTjvoc0vA6AplEhcTGrzC8X0sQiy4ql8YY6+HXMPI7xadQfyZO3 rVpqEawrdzvZgfR+GWDZNDjzQ0DeX5hwXpgPF95UgTZS55eF4Yuxqsp/tiI4jC0PpD rI3vrTnBSVt0E+pjjQ5KrjFLaXzG7IPIgzv1V21aQlhDSY6DOE8O/R1qBMkcr8h8Zx RaovJ6A+kSu7w== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org Tegra AHCI dt-binding doc is converted from text based to yaml based. dtbs_check valdiation strictly follows reset-names order specified in yaml dt-binding. Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold. Tegra186 has 2 resets sata and sata-cold. This patch changes order of SATA resets to maintain proper resets order for commonly available resets across Tegra124 thru Tegra186 for dtbs_check to pass. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 6 +++--- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 0ce958a..9928a87 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -629,9 +629,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 6d2a9d2..ffe5da7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -979,9 +979,9 @@ <&tegra_car TEGRA210_CLK_SATA_OOB>; clock-names = "sata", "sata-oob"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; From patchwork Mon Nov 23 20:17:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1405090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=qSSVc4kY; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cfz4c0qtLz9sVW for ; Tue, 24 Nov 2020 07:18:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732355AbgKWURi (ORCPT ); Mon, 23 Nov 2020 15:17:38 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18763 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732697AbgKWURV (ORCPT ); Mon, 23 Nov 2020 15:17:21 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 23 Nov 2020 12:17:22 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Nov 2020 20:17:21 +0000 Received: from skomatineni-linux.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 23 Nov 2020 20:17:20 +0000 From: Sowjanya Komatineni To: , , , CC: , , , , Subject: [PATCH v3 3/6] dt-bindings: ata: tegra: Convert binding documentation to YAML Date: Mon, 23 Nov 2020 12:17:22 -0800 Message-ID: <1606162645-22326-4-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> References: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606162642; bh=wlJFnUwU5HKWWHpUe0MiGg5G/qDVWBP57wxnM35kaw8=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=qSSVc4kYKYDkTWQpF/UI/hfTO7OwRMVz80zW1uHjHYXk6Xy/MArRY5PBeJIMylD/6 sM7CvuaD9y2Gy/ZP9OK6W/CtXwslP2/hsEzJzoySYXusRkVBf85hVIWHJsW98zQVMV sWtLlarcB6vUrlqTaxS0kkD4xVcJIhUVXIXGr/kAJkVvevYsBvIqFwIu99+nCEWucf osXIKBG4mPlds12bK9ziF+NxNsPsvbkO2IHKHK3oR4T5uL8NtoM9J7JqyiuVQpdbWj cPqsFRRhCDtc1NLQ0t1cE9AasiVGKRPvzpVNRItit0IPTR3A13fWWsiIlbfaTbcvHc TGIyWoMwi5DoQ== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch converts text based dt-binding document to YAML based dt-binding document. Signed-off-by: Sowjanya Komatineni Reviewed-by: Rob Herring --- .../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 138 +++++++++++++++++++++ .../bindings/ata/nvidia,tegra124-ahci.txt | 44 ------- 2 files changed, 138 insertions(+), 44 deletions(-) create mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml delete mode 100644 Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml new file mode 100644 index 0000000..3c15aea --- /dev/null +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra AHCI SATA Controller + +maintainers: + - Thierry Reding + - Jonathan Hunter + +properties: + compatible: + enum: + - nvidia,tegra124-ahci + - nvidia,tegra132-ahci + - nvidia,tegra210-ahci + + reg: + minItems: 2 + maxItems: 3 + items: + - description: AHCI registers + - description: SATA configuration and IPFS registers + - description: SATA AUX registers + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: sata + - const: sata-oob + + clocks: + maxItems: 2 + + reset-names: + items: + - const: sata + - const: sata-cold + - const: sata-oob + + resets: + maxItems: 3 + + phy-names: + items: + - const: sata-0 + + phys: + maxItems: 1 + + hvdd-supply: + description: SATA HVDD regulator supply. + + vddio-supply: + description: SATA VDDIO regulator supply. + + avdd-supply: + description: SATA AVDD regulator supply. + + target-5v-supply: + description: SATA 5V power regulator supply. + + target-12v-supply: + description: SATA 12V power regulator supply. + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - reset-names + - resets + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-ahci + - nvidia,tegra132-ahci + then: + properties: + reg: + maxItems: 2 + reset-names: + minItems: 3 + resets: + minItems: 3 + required: + - phys + - phy-names + - hvdd-supply + - vddio-supply + - avdd-supply + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-ahci + then: + properties: + reg: + minItems: 3 + reset-names: + minItems: 3 + resets: + minItems: 3 + +additionalProperties: true + +examples: + - | + #include + #include + #include + + sata@70020000 { + compatible = "nvidia,tegra210-ahci"; + reg = <0x70027000 0x00002000>, /* AHCI */ + <0x70020000 0x00007000>, /* SATA */ + <0x70001100 0x00010000>; /* SATA AUX */ + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_SATA>, + <&tegra_car TEGRA210_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + resets = <&tegra_car 124>, + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; + }; diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt b/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt deleted file mode 100644 index 12ab2f7..0000000 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra124-ahci.txt +++ /dev/null @@ -1,44 +0,0 @@ -Tegra SoC SATA AHCI controller - -Required properties : -- compatible : Must be one of: - - Tegra124 : "nvidia,tegra124-ahci" - - Tegra132 : "nvidia,tegra132-ahci", "nvidia,tegra124-ahci" - - Tegra210 : "nvidia,tegra210-ahci" -- reg : Should contain 2 entries: - - AHCI register set (SATA BAR5) - - SATA register set -- interrupts : Defines the interrupt used by SATA -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - sata - - sata-oob -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - sata - - sata-oob - - sata-cold -- phys : Must contain an entry for each entry in phy-names. - See ../phy/phy-bindings.txt for details. -- phy-names : Must include the following entries: - - For Tegra124 and Tegra132: - - sata-phy : XUSB PADCTL SATA PHY -- For Tegra124 and Tegra132: - - hvdd-supply : Defines the SATA HVDD regulator - - vddio-supply : Defines the SATA VDDIO regulator - - avdd-supply : Defines the SATA AVDD regulator - - target-5v-supply : Defines the SATA 5V power regulator - - target-12v-supply : Defines the SATA 12V power regulator - -Optional properties: -- reg : - - AUX register set -- clock-names : - - cml1 : - cml1 clock should be defined here if the PHY driver - doesn't manage them. If it does, they should not be. -- phy-names : - - For T210: - - sata-phy From patchwork Mon Nov 23 20:17:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1405079 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=SA4t3Q7J; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cfz3W6BYJz9sVH for ; Tue, 24 Nov 2020 07:17:43 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387565AbgKWURX (ORCPT ); Mon, 23 Nov 2020 15:17:23 -0500 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:2130 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733206AbgKWURW (ORCPT ); Mon, 23 Nov 2020 15:17:22 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 23 Nov 2020 12:17:28 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Nov 2020 20:17:22 +0000 Received: from skomatineni-linux.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 23 Nov 2020 20:17:21 +0000 From: Sowjanya Komatineni To: , , , CC: , , , , Subject: [PATCH v3 4/6] dt-binding: ata: tegra: Add dt-binding documentation for Tegra186 Date: Mon, 23 Nov 2020 12:17:23 -0800 Message-ID: <1606162645-22326-5-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> References: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606162648; bh=HuoDnHcnGhEevhf1Zh/7gdjVQApYfl/WHCoySUA+VnE=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=SA4t3Q7JCHtrQp4YzKIBDBPjjJyWdGfYwF0yD+B6co/GZ7KAqALhkl3EiYHlYdQEB EPxMNZvbuZtMdUEGD9whFDtljTJaIv9A6qWDR9onlSorSmiPKoY9YTcE9k1nmAfE+i a3IbOiM4T3j70CHkK0bk82GVRUPVj0PcMmExTui/4d0PZYnjQ/OmCx6vNKEcwCXBdm Qh5JynvFhCxb8kP245gnRjflO7pJcnW7JRzwg/OI10++LL5ouav4S9d2N6T95E2uZj dsfdeyc/f+zJ2xCy4YbzzJVqomv7QeGOU4oMtMGbTwalvqXkLp7QfFtFh78jMHupZ3 O4qUUePh20V0w== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch adds dt-bindings documentation for Tegra186 AHCI controller. Reviewed-by: Rob Herring Signed-off-by: Sowjanya Komatineni --- .../devicetree/bindings/ata/nvidia,tegra-ahci.yaml | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml index 3c15aea..a75e9a8 100644 --- a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml +++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml @@ -16,6 +16,7 @@ properties: - nvidia,tegra124-ahci - nvidia,tegra132-ahci - nvidia,tegra210-ahci + - nvidia,tegra186-ahci reg: minItems: 2 @@ -37,14 +38,31 @@ properties: maxItems: 2 reset-names: + minItems: 2 items: - const: sata - const: sata-cold - const: sata-oob resets: + minItems: 2 maxItems: 3 + iommus: + maxItems: 1 + + interconnect-names: + items: + - const: dma-mem + - const: write + + interconnects: + maxItems: 2 + + power-domains: + items: + - description: SAX power-domain + phy-names: items: - const: sata-0 @@ -114,6 +132,26 @@ allOf: resets: minItems: 3 + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-ahci + then: + properties: + reg: + minItems: 3 + reset-names: + maxItems: 2 + resets: + maxItems: 2 + required: + - iommus + - interconnect-names + - interconnects + - power-domains + additionalProperties: true examples: From patchwork Mon Nov 23 20:17:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1405078 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=I5X2+23L; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cfz3V0663z9sRR for ; Tue, 24 Nov 2020 07:17:42 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387777AbgKWUR0 (ORCPT ); Mon, 23 Nov 2020 15:17:26 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:11577 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387571AbgKWURX (ORCPT ); Mon, 23 Nov 2020 15:17:23 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 23 Nov 2020 12:17:26 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Nov 2020 20:17:23 +0000 Received: from skomatineni-linux.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 23 Nov 2020 20:17:22 +0000 From: Sowjanya Komatineni To: , , , CC: , , , , Subject: [PATCH v3 5/6] arm64: tegra: Enable AHCI on Jetson TX2 Date: Mon, 23 Nov 2020 12:17:24 -0800 Message-ID: <1606162645-22326-6-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> References: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606162646; bh=qVTpNTARpxFPRZwBVNChWjl+Ht3cqycld42DMDClpBs=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=I5X2+23LuVOcHvu3ahfFCKT6NskdiMsc4LFNB0FYVOnasfSFqFoHsWQSIvTc7iUnH T7aecwbTeL99wqyTXiwXfu0HmjR8SOCVbg34IzF53mx+qZKwr7q3hX7oNZBuoVcR+j wjsHve3ETOPQzChOabFl97IvrPFomFkfQXwrNcj1jTtel/TGkvNq58z8tjxqlLLIIJ Ormuzk7BMg8WEeevkULSlui1RtsMkNN70Wla0C2ftSPELRG7SGcIvakcCGcNbk3enN josDE3TfTvt/wbtgqsgjkT/t32LY+5OK6YNDLVywLFXNnyENYepuxTf2zlVldwPyKL Tp4wCg45ADWRA== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch enables AHCI on Jetson TX2. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 4 ++++ arch/arm64/boot/dts/nvidia/tegra186.dtsi | 28 ++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index c28d51c..6fd2e05 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -285,6 +285,10 @@ }; }; + sata@3507000 { + status = "okay"; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 98544d1..a303f45 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -1503,6 +1503,34 @@ }; }; + sata@3507000 { + compatible = "nvidia,tegra186-ahci"; + reg = <0x0 0x03507000 0x0 0x00002000>, /* AHCI */ + <0x0 0x03500000 0x0 0x00007000>, /* SATA */ + <0x0 0x03A90000 0x0 0x00010000>; /* SATA AUX */ + interrupts = ; + + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_SAX>; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_SATAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_SATAW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu TEGRA186_SID_SATA>; + + clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + clock-names = "sata", "sata-oob"; + assigned-clocks = <&bpmp TEGRA186_CLK_SATA>, + <&bpmp TEGRA186_CLK_SATA_OOB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>, + <&bpmp TEGRA186_CLK_PLLP>; + assigned-clock-rates = <102000000>, + <204000000>; + resets = <&bpmp TEGRA186_RESET_SATA>, + <&bpmp TEGRA186_RESET_SATACOLD>; + reset-names = "sata", "sata-cold"; + status = "disabled"; + }; + bpmp: bpmp { compatible = "nvidia,tegra186-bpmp"; interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, From patchwork Mon Nov 23 20:17:25 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1405080 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-ide-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=FHZPdjZ8; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cfz3X3MpCz9sVL for ; Tue, 24 Nov 2020 07:17:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730556AbgKWURc (ORCPT ); Mon, 23 Nov 2020 15:17:32 -0500 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:18767 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387772AbgKWURY (ORCPT ); Mon, 23 Nov 2020 15:17:24 -0500 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Mon, 23 Nov 2020 12:17:25 -0800 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Nov 2020 20:17:24 +0000 Received: from skomatineni-linux.nvidia.com (172.20.13.39) by mail.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 23 Nov 2020 20:17:23 +0000 From: Sowjanya Komatineni To: , , , CC: , , , , Subject: [PATCH v3 6/6] ata: ahci_tegra: Add AHCI support for Tegra186 Date: Mon, 23 Nov 2020 12:17:25 -0800 Message-ID: <1606162645-22326-7-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> References: <1606162645-22326-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1606162645; bh=bqvYhM4gfczmD1UkOCBSQi6kCpayixLg2a8u43aYS8U=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=FHZPdjZ84by4HdXtwgk5Lr5yBT3/sA4zHoUMvk22MvFk17s5t7Ar5SitfedtyOtgO lHrGjobBWNSV74rd8cEqYmzjYLdY5289JE1gwe77shWA0zyc4bZp+o8/Dloo6ggJqh 8Xzn9TD0E9jy+cIoz4kIUM3d4mS+ilqT0OgX1/OU6Diaf0AXWEqN4DYY+JzuT7/TfZ f68BlUWy4jk6gTQ6Q4XO8f3oVfXtqlcNu3SB8Q9sutN77pQXR+XKSgn2/YFo+xvsch vhOStQ2Xw8GZHMjyqOQ4SJhZrpEdUAfTs+vCmtcManh33eiTltxV9diXSJkNb3WYAS HHCVK/3OrxcCA== Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org This patch adds support for AHCI-compliant Serial ATA controller on Tegra186 SoC. Tegra186 does not have sata-oob reset. Tegra186 SATA_NVOOB register filed COMMA_CNT position and width are different compared to Tegra210 and prior. So, this patch adds a flag has_sata_oob_rst and tegra_ahci_regs to SoC specific strcuture tegra_ahci_soc and updated their implementation accordingly. Signed-off-by: Sowjanya Komatineni --- drivers/ata/ahci_tegra.c | 60 +++++++++++++++++++++++++++++++++++++----------- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/drivers/ata/ahci_tegra.c b/drivers/ata/ahci_tegra.c index cb55ebc1..56612af 100644 --- a/drivers/ata/ahci_tegra.c +++ b/drivers/ata/ahci_tegra.c @@ -59,8 +59,6 @@ #define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN BIT(22) #define T_SATA0_NVOOB 0x114 -#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16) -#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16) #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24) #define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24) #define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26) @@ -154,11 +152,18 @@ struct tegra_ahci_ops { int (*init)(struct ahci_host_priv *hpriv); }; +struct tegra_ahci_regs { + unsigned int nvoob_comma_cnt_mask; + unsigned int nvoob_comma_cnt_val; +}; + struct tegra_ahci_soc { const char *const *supply_names; u32 num_supplies; bool supports_devslp; + bool has_sata_oob_rst; const struct tegra_ahci_ops *ops; + const struct tegra_ahci_regs *regs; }; struct tegra_ahci_priv { @@ -240,11 +245,13 @@ static int tegra_ahci_power_on(struct ahci_host_priv *hpriv) if (ret) return ret; - ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA, - tegra->sata_clk, - tegra->sata_rst); - if (ret) - goto disable_regulators; + if (!tegra->pdev->dev.pm_domain) { + ret = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SATA, + tegra->sata_clk, + tegra->sata_rst); + if (ret) + goto disable_regulators; + } reset_control_assert(tegra->sata_oob_rst); reset_control_assert(tegra->sata_cold_rst); @@ -330,10 +337,10 @@ static int tegra_ahci_controller_init(struct ahci_host_priv *hpriv) writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA_CFG_PHY_0); val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); - val &= ~(T_SATA0_NVOOB_COMMA_CNT_MASK | + val &= ~(tegra->soc->regs->nvoob_comma_cnt_mask | T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK | T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK); - val |= (T_SATA0_NVOOB_COMMA_CNT | + val |= (tegra->soc->regs->nvoob_comma_cnt_val | T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH | T_SATA0_NVOOB_SQUELCH_FILTER_MODE); writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_NVOOB); @@ -449,15 +456,35 @@ static const struct tegra_ahci_ops tegra124_ahci_ops = { .init = tegra124_ahci_init, }; +static const struct tegra_ahci_regs tegra124_ahci_regs = { + .nvoob_comma_cnt_mask = GENMASK(30, 28), + .nvoob_comma_cnt_val = (7 << 28), +}; + static const struct tegra_ahci_soc tegra124_ahci_soc = { .supply_names = tegra124_supply_names, .num_supplies = ARRAY_SIZE(tegra124_supply_names), .supports_devslp = false, + .has_sata_oob_rst = true, .ops = &tegra124_ahci_ops, + .regs = &tegra124_ahci_regs, }; static const struct tegra_ahci_soc tegra210_ahci_soc = { .supports_devslp = false, + .has_sata_oob_rst = true, + .regs = &tegra124_ahci_regs, +}; + +static const struct tegra_ahci_regs tegra186_ahci_regs = { + .nvoob_comma_cnt_mask = GENMASK(23, 16), + .nvoob_comma_cnt_val = (7 << 16), +}; + +static const struct tegra_ahci_soc tegra186_ahci_soc = { + .supports_devslp = false, + .has_sata_oob_rst = false, + .regs = &tegra186_ahci_regs, }; static const struct of_device_id tegra_ahci_of_match[] = { @@ -469,6 +496,10 @@ static const struct of_device_id tegra_ahci_of_match[] = { .compatible = "nvidia,tegra210-ahci", .data = &tegra210_ahci_soc }, + { + .compatible = "nvidia,tegra186-ahci", + .data = &tegra186_ahci_soc + }, {} }; MODULE_DEVICE_TABLE(of, tegra_ahci_of_match); @@ -518,10 +549,13 @@ static int tegra_ahci_probe(struct platform_device *pdev) return PTR_ERR(tegra->sata_rst); } - tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, "sata-oob"); - if (IS_ERR(tegra->sata_oob_rst)) { - dev_err(&pdev->dev, "Failed to get sata-oob reset\n"); - return PTR_ERR(tegra->sata_oob_rst); + if (tegra->soc->has_sata_oob_rst) { + tegra->sata_oob_rst = devm_reset_control_get(&pdev->dev, + "sata-oob"); + if (IS_ERR(tegra->sata_oob_rst)) { + dev_err(&pdev->dev, "Failed to get sata-oob reset\n"); + return PTR_ERR(tegra->sata_oob_rst); + } } tegra->sata_cold_rst = devm_reset_control_get(&pdev->dev, "sata-cold");