From patchwork Fri Nov 20 20:38:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 1404115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.a=rsa-sha256 header.s=google header.b=X8TXokEn; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4Cd7gy2SVTz9sSs for ; Sat, 21 Nov 2020 07:39:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731626AbgKTUix (ORCPT ); Fri, 20 Nov 2020 15:38:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33278 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731606AbgKTUix (ORCPT ); Fri, 20 Nov 2020 15:38:53 -0500 Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4623FC061A04 for ; Fri, 20 Nov 2020 12:38:53 -0800 (PST) Received: by mail-pg1-x543.google.com with SMTP id t37so8220086pga.7 for ; Fri, 20 Nov 2020 12:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=s3JFM6+R/fz9a6e/9WK19OMBhtmUak5nMtuY/8voL+8=; b=X8TXokEnPDbqhWscmro+RZhPfPL/eX8RNpMrmVCnik6AQoW841E6pfgKfCGAs8naBS FJLSFKhFmvRa2VmZ+LEDOXPhwILF7O4L9oDutWeWhZH3zBcCW4pcAxTmy1/VER7mXwd2 CbVY2FGEU9CJpUBP+OzeRuDCBT8VyzdO3Jddc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=s3JFM6+R/fz9a6e/9WK19OMBhtmUak5nMtuY/8voL+8=; b=jkZyRwqAzERMcJjWhUuhY3rj0hVgobH8SFYG4hz+RC0QrzohxQHBtNcTWzBCeTBlOD j9oLSS47QDgTjXZUXFdyx1JP4mRgUvtSWw+EDiZOcGywOn+dUWM1xzG03F9fd1baqQmn 6cpsmtgcWzz6cz7eXR3sH3xJ/Mvrn+j9ofe/aq4/qUwRhOAcwwMuYrm3DXmCJPtbxsvf S14Gb/yvM51mqs9zE/oLsqVEaMl5H/OAbzOauOxCOtCg2v99bLsnJrlpP8poTCzOejHk EqUD59oKcR7Aqvj80R/a7LIwVGR3sNyGobQH7QTbBD5hZKi7BwwSJg79QKzEFQnpSZGF uImw== X-Gm-Message-State: AOAM530+D2SUtrYV6brPKVJQ2w57uCsTLgiAz4dUYMLEPEeoJvt0RbCG Y/I4quCce4DiG1qiueqLBB6yhg== X-Google-Smtp-Source: ABdhPJyCb06pnuP8D6Cf41I+031AQMEbTnmOzn7yWU2AlmC8OFb17e4hnV/cP3Dv4H4OrXVUCdkSAw== X-Received: by 2002:a17:90a:4410:: with SMTP id s16mr12814484pjg.173.1605904732749; Fri, 20 Nov 2020 12:38:52 -0800 (PST) Received: from stbsrv-and-01.and.broadcom.net ([192.19.231.250]) by smtp.gmail.com with ESMTPSA id gx24sm4838688pjb.38.2020.11.20.12.38.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Nov 2020 12:38:51 -0800 (PST) From: Jim Quinlan To: Philipp Zabel , Hans de Goede , Jens Axboe , bcm-kernel-feedback-list@broadcom.com, james.quinlan@broadcom.com Cc: Nicolas Saenz Julienne , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Florian Fainelli , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-pci@vger.kernel.org (open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v3 2/2] PCI: brcmstb: use reset/rearm instead of deassert/assert Date: Fri, 20 Nov 2020 15:38:39 -0500 Message-Id: <20201120203840.35139-3-james.quinlan@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201120203840.35139-1-james.quinlan@broadcom.com> References: <20201120203840.35139-1-james.quinlan@broadcom.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Brcmstb PCIe RC uses a reset control "rescal" for certain chips. This reset implements a "pulse reset" so it matches more the reset/rearm calls instead of the deassert/assert calls. Also, add reset_control calls in suspend/resume functions. Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index bea86899bd5d..b9745ac2ee0b 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1138,6 +1138,7 @@ static int brcm_pcie_suspend(struct device *dev) brcm_pcie_turn_off(pcie); ret = brcm_phy_stop(pcie); + reset_control_rearm(pcie->rescal); clk_disable_unprepare(pcie->clk); return ret; @@ -1153,9 +1154,13 @@ static int brcm_pcie_resume(struct device *dev) base = pcie->base; clk_prepare_enable(pcie->clk); + ret = reset_control_reset(pcie->rescal); + if (ret) + goto err0; + ret = brcm_phy_start(pcie); if (ret) - goto err; + goto err1; /* Take bridge out of reset so we can access the SERDES reg */ pcie->bridge_sw_init_set(pcie, 0); @@ -1170,14 +1175,16 @@ static int brcm_pcie_resume(struct device *dev) ret = brcm_pcie_setup(pcie); if (ret) - goto err; + goto err1; if (pcie->msi) brcm_msi_set_regs(pcie->msi); return 0; -err: +err1: + reset_control_rearm(pcie->rescal); +err0: clk_disable_unprepare(pcie->clk); return ret; } @@ -1187,7 +1194,7 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie) brcm_msi_remove(pcie); brcm_pcie_turn_off(pcie); brcm_phy_stop(pcie); - reset_control_assert(pcie->rescal); + reset_control_rearm(pcie->rescal); clk_disable_unprepare(pcie->clk); } @@ -1262,13 +1269,13 @@ static int brcm_pcie_probe(struct platform_device *pdev) return PTR_ERR(pcie->rescal); } - ret = reset_control_deassert(pcie->rescal); + ret = reset_control_reset(pcie->rescal); if (ret) dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); ret = brcm_phy_start(pcie); if (ret) { - reset_control_assert(pcie->rescal); + reset_control_rearm(pcie->rescal); clk_disable_unprepare(pcie->clk); return ret; }