From patchwork Mon Oct 26 06:54:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1387490 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=BxocTS86; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CKQZT62Vzz9sTf for ; Mon, 26 Oct 2020 17:55:13 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1770796AbgJZGzN (ORCPT ); Mon, 26 Oct 2020 02:55:13 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18151 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1768361AbgJZGzN (ORCPT ); Mon, 26 Oct 2020 02:55:13 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Sun, 25 Oct 2020 23:54:51 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Oct 2020 06:55:11 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 26 Oct 2020 06:55:08 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH 1/4] PCI: tegra: Fix ASPM-L1SS advertisement disable code Date: Mon, 26 Oct 2020 12:24:56 +0530 Message-ID: <20201026065459.28509-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201026065459.28509-1-vidyas@nvidia.com> References: <20201026065459.28509-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603695291; bh=/DUL5KI3q62bzSd7mI3FJUQl1oNiuiFR8PzvH9Fi7Hw=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=BxocTS86r6UQCOJvcheF7vbGzAt17YNLqzqRr4cHaIPGI3gMqv3+E+JHttqz3lx0U 7ouqlGShrt0JT4r06+5Rm4bFXFHof2RxwXiB9SthU1ZGBo+jPOe8dLIVJbhDz8jgpG kUW7+Cd3Gv5jj2q5xErFAyTzCTc0hHDmfoLQx2KB4xdVG8W8Xl54sUlvjEaU7SN9bu u/+CbJLHAzwwfNhdJU38Vdlv6p6LKhKCrQBFOzxO4ncHbC7qhM/JX5Tpmpl0spH+Mu bjwThcvZOVaU9AwLyLOelJjmRVzJUdq68dOTB3vDI47UfY2VeYjWc2XqnPW6qYwRXi f8+VCPUmOjhwQ== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org If the absence of CLKREQ# signal is indicated by the absence of "supports-clkreq" in the device-tree node, current driver is disabling the advertisement of ASPM-L1 Sub-States *before* the ASPM-L1 Sub-States offset is correctly initialized. Since default value of the ASPM-L1SS offset is zero, this is causing the Vendor-ID wrongly programmed to 0x10d2 instead of Nvidia's 0x10de thereby the quirks applicable for Tegra194 are not being applied. This patch fixes this issue by refactoring the code that disables the ASPM-L1SS advertisement. Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index aa511ec0d800..b172b1d49713 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -896,6 +896,12 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) init_host_aspm(pcie); + /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ + if (!pcie->supports_clkreq) { + disable_aspm_l11(pcie); + disable_aspm_l12(pcie); + } + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); @@ -1400,12 +1406,6 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); - /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */ - if (!pcie->supports_clkreq) { - disable_aspm_l11(pcie); - disable_aspm_l12(pcie); - } - return ret; fail_phy: From patchwork Mon Oct 26 06:54:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1387493 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=sQhFAsNW; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CKQZg4hFVz9sTf for ; Mon, 26 Oct 2020 17:55:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1770805AbgJZGzS (ORCPT ); Mon, 26 Oct 2020 02:55:18 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:12598 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1768361AbgJZGzS (ORCPT ); Mon, 26 Oct 2020 02:55:18 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Sun, 25 Oct 2020 23:55:26 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Oct 2020 06:55:17 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 26 Oct 2020 06:55:13 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH 2/4] PCI: tegra: Map configuration space as strongly ordered Date: Mon, 26 Oct 2020 12:24:57 +0530 Message-ID: <20201026065459.28509-3-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201026065459.28509-1-vidyas@nvidia.com> References: <20201026065459.28509-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603695326; bh=Z/hMbqdt0AIcQEkXcN6GBgOo7FXu0Cx8OGl4g1fRQt4=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=sQhFAsNW/heuKE1HBgNmY48ZKkdPkmLzZsXDA4rutOwh9DKs0D9p8CUsHBnq6Soa9 /oVZC76nF1POmiW2ZcpoNA2xCKYA7fi4pzqMyZxaM3UcNMskX9kis64WUu+hSu+7Ji 9cCdI62uE7FY2Q2vRW2VwU84M/DxWn4CDC0Nhd9fU0x1skfK43FsGr9bwmgEWnbFDz 3T68nZhJ8hMkoAGITwf8r3m0R/fkw9pX2/rfBnPqqJrF7sg22Jw7hy3e9O/Y4AVwM2 uZqL1oAWMBVuF9mCL7IAqkJFH+1u6YolRzvFgkgT5f02HHR/ho1+t8CK7+SNlhtQw5 oxhBxh6zWFXUA== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org As specified in the comment for pci_remap_cfgspace() define in arch/arm64/include/asm/io.h file, PCIe configuration space should be mapped as strongly ordered. Hence changing to dev_pci_remap_cfgspace() from devm_ioremap_resource() for mapping DBI space as that is nothing but the root port's own configuration space. Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index b172b1d49713..7a0c64436861 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2108,7 +2108,9 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) } pcie->dbi_res = dbi_res; - pci->dbi_base = devm_ioremap_resource(dev, dbi_res); + pci->dbi_base = devm_pci_remap_cfgspace(dev, + dbi_res->start, + resource_size(dbi_res)); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); From patchwork Mon Oct 26 06:54:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1387494 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=p6A2s80K; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CKQZh1Wwkz9sV0 for ; Mon, 26 Oct 2020 17:55:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1770814AbgJZGzX (ORCPT ); Mon, 26 Oct 2020 02:55:23 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:12606 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1768361AbgJZGzX (ORCPT ); Mon, 26 Oct 2020 02:55:23 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Sun, 25 Oct 2020 23:55:31 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Oct 2020 06:55:22 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 26 Oct 2020 06:55:19 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH 3/4] PCI: tegra: Set DesignWare IP version Date: Mon, 26 Oct 2020 12:24:58 +0530 Message-ID: <20201026065459.28509-4-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201026065459.28509-1-vidyas@nvidia.com> References: <20201026065459.28509-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603695331; bh=GFmNysVeN0rKBbKQ9g02PVNLmRmdooLteOZK929w+3Y=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=p6A2s80KeReTaNcTk9j45dFxPHi6ELkDsT7irTb3tltzzLmgh7Fab219E836U8QRi /ZKsPduBXYPEiDG4n0f2ViXzuGXODz7jceiHsQytoD9+k5EiUxOqa2N+dcbqtTO22Z 3s32KWbXHkepQxxHDgsqIQuTUUu0edAYMxlvKkAonsY5tAqFejs4FF+0ZOIzOlhU/7 W7D3leV8eRcsjNGbgl5t56xPA8Ovzxa4aNqBhV5tPoFwfMqXgHnZ1dHbOQ5nd6GTJ7 eOdbzotpi4SdeG7dgs6/VIoNlBdSSouwOiARNOgLeTnGLKnIbDbXoI74hJ+nz7B75d Flktexb8Lrk0A== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Set the DesignWare IP version for Tegra194 to 0x490A. This would be used by the DesigWare sub-system to do any version specific configuration (Ex:- TD bit programming for ECRC). Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7a0c64436861..253d91033bc3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2011,6 +2011,7 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev) pci->ops = &tegra_dw_pcie_ops; pci->n_fts[0] = N_FTS_VAL; pci->n_fts[1] = FTS_VAL; + pci->version = 0x490A; pp = &pci->pp; pcie->dev = &pdev->dev; From patchwork Mon Oct 26 06:54:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1387496 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=N9n11gZB; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CKQZn2Tzbz9sV0 for ; Mon, 26 Oct 2020 17:55:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1770823AbgJZGz3 (ORCPT ); Mon, 26 Oct 2020 02:55:29 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18194 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1768361AbgJZGz2 (ORCPT ); Mon, 26 Oct 2020 02:55:28 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Sun, 25 Oct 2020 23:55:07 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Oct 2020 06:55:27 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 26 Oct 2020 06:55:24 +0000 From: Vidya Sagar To: , , , , , , , CC: , , , , , , Subject: [PATCH 4/4] PCI: tegra: Handle error conditions properly Date: Mon, 26 Oct 2020 12:24:59 +0530 Message-ID: <20201026065459.28509-5-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201026065459.28509-1-vidyas@nvidia.com> References: <20201026065459.28509-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603695307; bh=HrV4xUNlix0+NHaugkAxqshy+cP+yr3y7m2Ah0m5Bm4=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=N9n11gZBT59QymATtceA9DjmvE/3DqzMVKCho1o57vf2Rn3jWDpwl0/Bsqui1XJ7S XhEzWZ7Ws+jARojcHgpdGbZ/H2Q0+S20r4GzLQdWYFgDDpCU+9E3rVKwZyO9j9f2SK jeuWrfV4H2aLJmQwvbIvS7slQJ++oFVBVZO9utB4+f3h2a4YnzSf2U+XEg9naWPBn1 zW0HkCJUbIc/5jxDZn2GBIMcklZtcrMOYvtnZ+MhUWDJgJUh29mE02f5pqu7CZy+RH Y71qTQmNHhMhvo9Oz2pMK+13NOuku05BmbtommHXbjhQwp8E5JtHnlf/xHwpgFPorG 9W7f5vchmwRbw== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Currently the driver checks for error value of different APIs during the uninitialization sequence. It just returns from there if there is any error observed for one of those calls. Comparatively it is better to continue the uninitialization sequence irrespective of whether some of them are returning error. That way, it is more closer to complete uninitialization. It also adds checking return value for error for a cleaner exit path. Signed-off-by: Vidya Sagar --- drivers/pci/controller/dwc/pcie-tegra194.c | 45 ++++++++++------------ 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 253d91033bc3..8c08998b9ce1 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1422,43 +1422,32 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie, return ret; } -static int __deinit_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie) { int ret; ret = reset_control_assert(pcie->core_rst); - if (ret) { - dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", - ret); - return ret; - } + if (ret) + dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret); tegra_pcie_disable_phy(pcie); ret = reset_control_assert(pcie->core_apb_rst); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); - return ret; - } clk_disable_unprepare(pcie->core_clk); ret = regulator_disable(pcie->pex_ctl_supply); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); - return ret; - } tegra_pcie_disable_slot_regulators(pcie); ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false); - if (ret) { + if (ret) dev_err(pcie->dev, "Failed to disable controller %d: %d\n", pcie->cid, ret); - return ret; - } - - return ret; } static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) @@ -1482,7 +1471,8 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) return 0; fail_host_init: - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); + return ret; } static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie) @@ -1551,13 +1541,12 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) appl_writel(pcie, data, APPL_PINMUX); } -static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) +static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { tegra_pcie_downstream_dev_to_D0(pcie); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); - - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); } static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) @@ -1590,7 +1579,11 @@ static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie) goto fail_pm_get_sync; } - tegra_pcie_init_controller(pcie); + ret = tegra_pcie_init_controller(pcie); + if (ret < 0) { + dev_err(dev, "Failed to initialize controller: %d\n", ret); + goto fail_pm_get_sync; + } pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); if (!pcie->link_state) { @@ -2238,8 +2231,9 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) PORT_LOGIC_MSI_CTRL_INT_0_EN); tegra_pcie_downstream_dev_to_D0(pcie); tegra_pcie_dw_pme_turnoff(pcie); + tegra_pcie_unconfig_controller(pcie); - return __deinit_controller(pcie); + return 0; } static int tegra_pcie_dw_resume_noirq(struct device *dev) @@ -2267,7 +2261,8 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) return 0; fail_host_init: - return __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); + return ret; } static int tegra_pcie_dw_resume_early(struct device *dev) @@ -2305,7 +2300,7 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) disable_irq(pcie->pci.pp.msi_irq); tegra_pcie_dw_pme_turnoff(pcie); - __deinit_controller(pcie); + tegra_pcie_unconfig_controller(pcie); } static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = {