From patchwork Mon Oct 26 06:39:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1387482 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=hXGW2UXA; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CKQD26V5Hz9s0b for ; Mon, 26 Oct 2020 17:39:14 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1770488AbgJZGjN (ORCPT ); Mon, 26 Oct 2020 02:39:13 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:16774 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1770486AbgJZGjM (ORCPT ); Mon, 26 Oct 2020 02:39:12 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Sun, 25 Oct 2020 23:38:51 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Oct 2020 06:39:09 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 26 Oct 2020 06:39:05 +0000 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH 1/2] dt-bindings: Fix entry name for I/O High Voltage property Date: Mon, 26 Oct 2020 12:09:01 +0530 Message-ID: <20201026063902.14744-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603694331; bh=HgUBHWCd2Nt7H938VkNrABLwzGofvKL5fDnjmwSsXZ4=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:X-NVConfidentiality: MIME-Version:Content-Type; b=hXGW2UXAjYe+nif59UbIhnSrorYC7Ft/vbP79id79sDHO6HD5pdNR2fV1Z3aeIX8k CVb/Ty7TspQS5Tf94O3jjht2CFVDhQ9iZBJzE68ts3IT6M2K218kBvHUXGh+Nw+DaH aE7BzgAyOMqrdiCl8yDEOZWD0vg9W8KXWtYYTrB+VAKT9jTDAz+siXXLXrn88hAfmx lhthG4oqbvxDXl8QTTKNOi2q4yo03kH9vOVy7+ZY4fGTb4zqDoX1IZKe53tYW+1n2s H+FneRCaWmiwycwVNqRA4sRoOKdabbjuIYh2cIK8tcEpkK0S/h26zP6iIfv553VMOt 6N3L5c8nuTSOA== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Correct the name of the I/O High Voltage Property from 'nvidia,io-high-voltage' to 'nvidia,io-hv'. Fixes: 2585a584f844 ("pinctrl: Add Tegra194 pinctrl DT bindings") Signed-off-by: Vidya Sagar Acked-by: Rob Herring --- .../devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt index 8763f448c376..90d38f710635 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.txt @@ -99,7 +99,7 @@ Example: nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; }; From patchwork Mon Oct 26 06:39:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 1387486 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=KvgFGXHq; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CKQDB02fpz9sTf for ; Mon, 26 Oct 2020 17:39:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1770502AbgJZGjU (ORCPT ); Mon, 26 Oct 2020 02:39:20 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:16782 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1770486AbgJZGjT (ORCPT ); Mon, 26 Oct 2020 02:39:19 -0400 Received: from hqmail.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, AES256-SHA) id ; Sun, 25 Oct 2020 23:38:58 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Oct 2020 06:39:15 +0000 Received: from vidyas-desktop.nvidia.com (10.124.1.5) by mail.nvidia.com (172.20.187.18) with Microsoft SMTP Server id 15.0.1473.3 via Frontend Transport; Mon, 26 Oct 2020 06:39:11 +0000 From: Vidya Sagar To: , , , , , , CC: , , , , , , , Subject: [PATCH 2/2] arm64: tegra: Fix DT binding for IO High Voltage entry Date: Mon, 26 Oct 2020 12:09:02 +0530 Message-ID: <20201026063902.14744-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201026063902.14744-1-vidyas@nvidia.com> References: <20201026063902.14744-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1603694338; bh=LI104L2D+SwIdxtDq4b7FINXu6Attxn2TxYNi16Z+hs=; h=From:To:CC:Subject:Date:Message-ID:X-Mailer:In-Reply-To: References:X-NVConfidentiality:MIME-Version:Content-Type; b=KvgFGXHqjXKF3QrUmrjMr7L68sJocNnR4O74HcMFCJm2HJbwBGND/QBsnmnJvKjj3 1G217TVgLY3/aa3VorJJRmk7BKomsT5enSNh0EKau2z9aDRYDhCd6K4ZPk15Ua+x4E 0LeMmMl4P3GnwtWVE0KJEzmOZ7lyerxD7EEF2EgsrklRypIAnP9TrwUJ170Dofstp6 oTe4fv3clsi9rFTENyUfs8K0NhPddU3HDZrbzvo3WkGW7evdoBqeIlo4Z20I+hW/nf DvvLhe/sMwxluMxvSR6qoMZXRSEe20MwOPwRk5yOEGPcOPmhx4PJxRz7veTOsqarLh SA83ZMLPKW86A== Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Fix the device-tree entry that represents I/O High Voltage property by replacing 'nvidia,io-high-voltage' with 'nvidia,io-hv' as the former entry is deprecated. Fixes: dbb72e2c305b ("arm64: tegra: Add configuration for PCIe C5 sideband signals") Signed-off-by: Vidya Sagar --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 48160f48003a..5007a2a8647c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -155,7 +155,7 @@ nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; }; @@ -167,7 +167,7 @@ nvidia,schmitt = ; nvidia,lpdr = ; nvidia,enable-input = ; - nvidia,io-high-voltage = ; + nvidia,io-hv = ; nvidia,tristate = ; nvidia,pull = ; };