From patchwork Mon Sep 28 15:13:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372727 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R4Y58vjz9sSs for ; Tue, 29 Sep 2020 01:18:53 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726420AbgI1PSx (ORCPT ); Mon, 28 Sep 2020 11:18:53 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14321 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726621AbgI1PSx (ORCPT ); Mon, 28 Sep 2020 11:18:53 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id BE5F65DC023556F0FCCF; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:10 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 01/20] dt-bindings: arm: hisilicon: split the dt-bindings of each controller into a separate file Date: Mon, 28 Sep 2020 23:13:05 +0800 Message-ID: <20200928151324.2134-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Split the devicetree bindings of each Hisilicon controller from hisilicon.txt into a separate file, the file name is the compatible name attach the .txt file name extension. All Hi6220 dedicated controllers are grouped into subdirectory "hi3620". All HiPxx dedicated controllers are grouped into subdirectory "hipxx" Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 + .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 ++ .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ++ .../controller/hisilicon,hi6220-aoctrl.txt | 18 ++ .../controller/hisilicon,hi6220-mediactrl.txt | 18 ++ .../controller/hisilicon,hi6220-pmctrl.txt | 18 ++ .../controller/hisilicon,hi6220-sramctrl.txt | 16 ++ .../controller/hisilicon,hi6220-sysctrl.txt | 19 ++ .../controller/hisilicon,hip01-sysctrl.txt | 19 ++ .../controller/hisilicon,hip04-bootwrapper.txt | 9 + .../controller/hisilicon,hip04-fabric.txt | 5 + .../controller/hisilicon,pcie-sas-subctrl.txt | 15 ++ .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 + .../controller/hisilicon,peri-subctrl.txt | 16 ++ .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ++ .../bindings/arm/hisilicon/hisilicon.txt | 262 --------------------- 16 files changed, 235 insertions(+), 262 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt new file mode 100644 index 000000000000000..ceffac537671668 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt @@ -0,0 +1,8 @@ +Hisilicon CPU controller + +Required properties: +- compatible : "hisilicon,cpuctrl" +- reg : Register address and size + +The clock registers and power registers of secondary cores are defined +in CPU controller, especially in HIX5HD2 SoC. diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt new file mode 100644 index 000000000000000..4d1c6abf03f6f97 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt @@ -0,0 +1,15 @@ +Hisilicon HiP05/HiP06 DSA sub system controller + +Required properties: +- compatible : "hisilicon,dsa-subctrl", "syscon"; +- reg : Register address and size + +The DSA sub system controller is shared by peripheral controllers in +HiP05 or HiP06 Soc to implement some basic configurations. + +Example: + /* for HiP05 dsa sub system */ + pcie_sas: system_controller@a0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0xa0000000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt new file mode 100644 index 000000000000000..0d5282f4670658d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt @@ -0,0 +1,21 @@ +Hisilicon Hi3798CV200 Peripheral Controller + +The Hi3798CV200 Peripheral Controller controls peripherals, queries +their status, and configures some functions of peripherals. + +Required properties: +- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" + and "simple-mfd". +- reg: Register address and size of Peripheral Controller. +- #address-cells: Should be 1. +- #size-cells: Should be 1. + +Examples: + + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt new file mode 100644 index 000000000000000..5a723c1d45f4a17 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Always ON domain controller + +Required properties: +- compatible : "hisilicon,hi6220-aoctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power always +on domain for mobile platform. + +Example: + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0x0 0xf7800000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt new file mode 100644 index 000000000000000..dcfdcbcb6455771 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Media domain controller + +Required properties: +- compatible : "hisilicon,hi6220-mediactrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this system controller to control the multimedia +domain(e.g. codec, G3D ...) for mobile platform. + +Example: + /*for Hi6220*/ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0x0 0xf4410000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt new file mode 100644 index 000000000000000..972842f07b5a2ce --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt @@ -0,0 +1,18 @@ +Hisilicon Hi6220 Power Management domain controller + +Required properties: +- compatible : "hisilicon,hi6220-pmctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, some clock registers are define + under this controller and this property must be present. + +Hisilicon designs this system controller to control the power management +domain for mobile platform. + +Example: + /*for Hi6220*/ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0x0 0xf7032000 0x0 0x1000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt new file mode 100644 index 000000000000000..086b7acccc5edc4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt @@ -0,0 +1,16 @@ +Hisilicon Hi6220 SRAM controller + +Required properties: +- compatible : "hisilicon,hi6220-sramctrl", "syscon" +- reg : Register address and size + +Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several +SRAM banks for power management, modem, security, etc. Further, use "syscon" +managing the common sram which can be shared by multiple modules. + +Example: + /*for Hi6220*/ + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0x0 0xfff80000 0x0 0x12000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt new file mode 100644 index 000000000000000..07e318eda254f52 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon Hi6220 system controller + +Required properties: +- compatible : "hisilicon,hi6220-sysctrl" +- reg : Register address and size +- #clock-cells: should be set to 1, many clock registers are defined + under this controller and this property must be present. + +Hisilicon designs this controller as one of the system controllers, +its main functions are the same as Hisilicon system controller, but +the register offset of some core modules are different. + +Example: + /*for Hi6220*/ + sys_ctrl: sys_ctrl@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0x0 0xf7030000 0x0 0x2000>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt new file mode 100644 index 000000000000000..db2dfdce799db91 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt @@ -0,0 +1,19 @@ +Hisilicon HiP01 system controller + +Required properties: +- compatible : "hisilicon,hip01-sysctrl" +- reg : Register address and size + +The HiP01 system controller is mostly compatible with hisilicon +system controller,but it has some specific control registers for +HIP01 SoC family, such as slave core boot, and also some same +registers located at different offset. + +Example: + + /* for hip01-ca9x2 */ + sysctrl: system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt new file mode 100644 index 000000000000000..b0d53333f4fdae1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt @@ -0,0 +1,9 @@ +Bootwrapper boot method (software protocol on SMP): + +Required Properties: +- compatible: "hisilicon,hip04-bootwrapper"; +- boot-method: Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt new file mode 100644 index 000000000000000..40453d02f2024bd --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt @@ -0,0 +1,5 @@ +Fabric: + +Required Properties: +- compatible: "hisilicon,hip04-fabric"; +- reg: Address and size of Fabric diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt new file mode 100644 index 000000000000000..1ef086bda81a3f5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt @@ -0,0 +1,15 @@ +Hisilicon HiP05/HiP06 PCIe-SAS sub system controller + +Required properties: +- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; +- reg : Register address and size + +The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in +HiP05 or HiP06 Soc to implement some basic configurations. + +Example: + /* for HiP05 PCIe-SAS sub system */ + pcie_sas: system_controller@b0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0xb0000000 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt new file mode 100644 index 000000000000000..deec777bc3a850a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt @@ -0,0 +1,13 @@ +PCTRL: Peripheral misc control register + +Required Properties: +- compatible: "hisilicon,pctrl" +- reg: Address and size of pctrl. + +Example: + + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt new file mode 100644 index 000000000000000..b96c2896078b914 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt @@ -0,0 +1,16 @@ +Hisilicon HiP05/HiP06 PERI sub system controller + +Required properties: +- compatible : "hisilicon,peri-subctrl", "syscon"; +- reg : Register address and size + +The PERI sub system controller is shared by peripheral controllers in +HiP05 or HiP06 Soc to implement some basic configurations. The peripheral +controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 sub peri system */ + peri_c_subctrl: syscon@80000000 { + compatible = "hisilicon,peri-subctrl", "syscon"; + reg = <0x0 0x80000000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt new file mode 100644 index 000000000000000..963f7f1ca7a2f0c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt @@ -0,0 +1,25 @@ +Hisilicon system controller + +Required properties: +- compatible : "hisilicon,sysctrl" +- reg : Register address and size + +Optional properties: +- smp-offset : offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go +- resume-offset : offset in sysctrl for notifying cpu0 when resume +- reboot-offset : offset in sysctrl for system reboot + +Example: + + /* for Hi3620 */ + sysctrl: system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index a97f643e7d1c760..ffe760a636b5e7f 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -55,265 +55,3 @@ Required root node properties: HiP07 D05 Board Required root node properties: - compatible = "hisilicon,hip07-d05"; - -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; - ------------------------------------------------------------------------ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; - - -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; - ------------------------------------------------------------------------ -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; - -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; - -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; - ------------------------------------------------------------------------ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. - ------------------------------------------------------------------------ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; - ------------------------------------------------------------------------ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric - ------------------------------------------------------------------------ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size From patchwork Mon Sep 28 15:13:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372723 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R492kyQz9sVT for ; Tue, 29 Sep 2020 01:18:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726876AbgI1PSa (ORCPT ); Mon, 28 Sep 2020 11:18:30 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14316 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726420AbgI1PR3 (ORCPT ); Mon, 28 Sep 2020 11:17:29 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id ACD45155813EB3A581B5; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:10 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 02/20] dt-bindings: arm: hisilicon: convert Hisilicon board/soc bindings to json-schema Date: Mon, 28 Sep 2020 23:13:06 +0800 Message-ID: <20200928151324.2134-3-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert Hisilicon SoC bindings to DT schema format using json-schema. Signed-off-by: Zhen Lei Reviewed-by: Rob Herring --- .../bindings/arm/hisilicon/hisilicon.txt | 57 -------------------- .../bindings/arm/hisilicon/hisilicon.yaml | 62 ++++++++++++++++++++++ 2 files changed, 62 insertions(+), 57 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt deleted file mode 100644 index ffe760a636b5e7f..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ /dev/null @@ -1,57 +0,0 @@ -Hisilicon Platforms Device Tree Bindings ----------------------------------------------------- -Hi3660 SoC -Required root node properties: - - compatible = "hisilicon,hi3660"; - -HiKey960 Board -Required root node properties: - - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; - -Hi3670 SoC -Required root node properties: - - compatible = "hisilicon,hi3670"; - -HiKey970 Board -Required root node properties: - - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; - -Hi3798cv200 SoC -Required root node properties: - - compatible = "hisilicon,hi3798cv200"; - -Hi3798cv200 Poplar Board -Required root node properties: - - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; - -Hi4511 Board -Required root node properties: - - compatible = "hisilicon,hi3620-hi4511"; - -Hi6220 SoC -Required root node properties: - - compatible = "hisilicon,hi6220"; - -HiKey Board -Required root node properties: - - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; - -HiP01 ca9x2 Board -Required root node properties: - - compatible = "hisilicon,hip01-ca9x2"; - -HiP04 D01 Board -Required root node properties: - - compatible = "hisilicon,hip04-d01"; - -HiP05 D02 Board -Required root node properties: - - compatible = "hisilicon,hip05-d02"; - -HiP06 D03 Board -Required root node properties: - - compatible = "hisilicon,hip06-d03"; - -HiP07 D05 Board -Required root node properties: - - compatible = "hisilicon,hip07-d05"; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml new file mode 100644 index 000000000000000..6d17309c7c84308 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Platforms Device Tree Bindings + +maintainers: + - Wei Xu + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Hi3660 based boards. + items: + - const: hisilicon,hi3660-hikey960 + - const: hisilicon,hi3660 + + - description: Hi3670 based boards. + items: + - const: hisilicon,hi3670-hikey970 + - const: hisilicon,hi3670 + + - description: Hi3798cv200 based boards. + items: + - const: hisilicon,hi3798cv200-poplar + - const: hisilicon,hi3798cv200 + + - description: Hi4511 Board + items: + - const: hisilicon,hi3620-hi4511 + + - description: Hi6220 based boards. + items: + - const: hisilicon,hi6220-hikey + - const: hisilicon,hi6220 + + - description: HiP01 based boards. + items: + - const: hisilicon,hip01-ca9x2 + - const: hisilicon,hip01 + + - description: HiP04 D01 Board + items: + - const: hisilicon,hip04-d01 + + - description: HiP05 D02 Board + items: + - const: hisilicon,hip05-d02 + + - description: HiP06 D03 Board + items: + - const: hisilicon,hip06-d03 + + - description: HiP07 D05 Board + items: + - const: hisilicon,hip07-d05 +... From patchwork Mon Sep 28 15:13:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372724 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R4D6rVLz9sVY for ; Tue, 29 Sep 2020 01:18:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726614AbgI1PR3 (ORCPT ); Mon, 28 Sep 2020 11:17:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14317 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726424AbgI1PR0 (ORCPT ); Mon, 28 Sep 2020 11:17:26 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B64F0E4EC2F8D1B921FD; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:11 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 03/20] dt-bindings: arm: hisilicon: add binding for SD5203 SoC Date: Mon, 28 Sep 2020 23:13:07 +0800 Message-ID: <20200928151324.2134-4-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Hisilicon SD5203 SoC. Signed-off-by: Zhen Lei --- Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml index 6d17309c7c84308..3337eebc61da812 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml @@ -59,4 +59,8 @@ properties: - description: HiP07 D05 Board items: - const: hisilicon,hip07-d05 + + - description: SD5203 Board + items: + - const: hisilicon,sd5203 ... From patchwork Mon Sep 28 15:13:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372725 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R4F5bnRz9sVT for ; Tue, 29 Sep 2020 01:18:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726605AbgI1PR3 (ORCPT ); Mon, 28 Sep 2020 11:17:29 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14314 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726409AbgI1PR1 (ORCPT ); Mon, 28 Sep 2020 11:17:27 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id A787EF68131FF3540F79; Mon, 28 Sep 2020 23:17:19 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:13 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 07/20] dt-bindings: arm: hisilicon: convert system controller bindings to json-schema Date: Mon, 28 Sep 2020 23:13:11 +0800 Message-ID: <20200928151324.2134-8-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon system controller and its variants binding to DT schema format using json-schema. All of them are grouped into one yaml file, to help users understand differences and avoid repeated descriptions. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-sysctrl.txt | 19 ---- .../controller/hisilicon,hip01-sysctrl.txt | 19 ---- .../arm/hisilicon/controller/hisilicon,sysctrl.txt | 25 ----- .../hisilicon/controller/hisilicon,sysctrl.yaml | 115 +++++++++++++++++++++ .../bindings/arm/hisilicon/hi3519-sysctrl.txt | 14 --- 5 files changed, 115 insertions(+), 77 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt deleted file mode 100644 index 07e318eda254f52..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon Hi6220 system controller - -Required properties: -- compatible : "hisilicon,hi6220-sysctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this controller as one of the system controllers, -its main functions are the same as Hisilicon system controller, but -the register offset of some core modules are different. - -Example: - /*for Hi6220*/ - sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt deleted file mode 100644 index db2dfdce799db91..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip01-sysctrl.txt +++ /dev/null @@ -1,19 +0,0 @@ -Hisilicon HiP01 system controller - -Required properties: -- compatible : "hisilicon,hip01-sysctrl" -- reg : Register address and size - -The HiP01 system controller is mostly compatible with hisilicon -system controller,but it has some specific control registers for -HIP01 SoC family, such as slave core boot, and also some same -registers located at different offset. - -Example: - - /* for hip01-ca9x2 */ - sysctrl: system-controller@10000000 { - compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; - reg = <0x10000000 0x1000>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt deleted file mode 100644 index 963f7f1ca7a2f0c..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.txt +++ /dev/null @@ -1,25 +0,0 @@ -Hisilicon system controller - -Required properties: -- compatible : "hisilicon,sysctrl" -- reg : Register address and size - -Optional properties: -- smp-offset : offset in sysctrl for notifying slave cpu booting - cpu 1, reg; - cpu 2, reg + 0x4; - cpu 3, reg + 0x8; - If reg value is not zero, cpun exit wfi and go -- resume-offset : offset in sysctrl for notifying cpu0 when resume -- reboot-offset : offset in sysctrl for system reboot - -Example: - - /* for Hi3620 */ - sysctrl: system-controller@fc802000 { - compatible = "hisilicon,sysctrl"; - reg = <0xfc802000 0x1000>; - smp-offset = <0x31c>; - resume-offset = <0x308>; - reboot-offset = <0x4>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml new file mode 100644 index 000000000000000..37b214e0a401d7d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,sysctrl.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,sysctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon system controller + +maintainers: + - Wei Xu + +description: | + The Hisilicon system controller is used on many Hisilicon boards, it can be + used to assist the slave core startup, reboot the system, etc. + + There are some variants of the Hisilicon system controller, such as HiP01, + Hi3519, Hi6220 system controller, each of them is mostly compatible with the + Hisilicon system controller, but some same registers located at different + offset. In addition, the HiP01 system controller has some specific control + registers for HIP01 SoC family, such as slave core boot. + + The compatible names of each system controller are as follows: + Hisilicon system controller --> hisilicon,sysctrl + HiP01 system controller --> hisilicon,hip01-sysctrl + Hi6220 system controller --> hisilicon,hi6220-sysctrl + Hi3519 system controller --> hisilicon,hi3519-sysctrl + +allOf: + - if: + properties: + compatible: + contains: + const: hisilicon,hi6220-sysctrl + then: + required: + - '#clock-cells' + +properties: + compatible: + oneOf: + - items: + - const: hisilicon,sysctrl + - items: + - const: hisilicon,sysctrl + - const: syscon + - items: + - const: hisilicon,hip01-sysctrl + - const: hisilicon,sysctrl + - items: + - const: hisilicon,hi6220-sysctrl + - const: syscon + - items: + - const: hisilicon,hi3519-sysctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + smp-offset: + description: | + offset in sysctrl for notifying slave cpu booting + cpu 1, reg; + cpu 2, reg + 0x4; + cpu 3, reg + 0x8; + If reg value is not zero, cpun exit wfi and go + $ref: /schemas/types.yaml#/definitions/uint32 + + resume-offset: + description: offset in sysctrl for notifying cpu0 when resume + $ref: /schemas/types.yaml#/definitions/uint32 + + reboot-offset: + description: offset in sysctrl for system reboot + $ref: /schemas/types.yaml#/definitions/uint32 + + '#clock-cells': + description: the number of cells occupied by one clock ID. + const: 1 + +required: + - compatible + - reg + +examples: + - | + /* Hisilicon system controller */ + system-controller@fc802000 { + compatible = "hisilicon,sysctrl"; + reg = <0xfc802000 0x1000>; + smp-offset = <0x31c>; + resume-offset = <0x308>; + reboot-offset = <0x4>; + }; + + /* HiP01 system controller */ + system-controller@10000000 { + compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl"; + reg = <0x10000000 0x1000>; + reboot-offset = <0x4>; + }; + + /* Hi6220 system controller */ + system-controller@f7030000 { + compatible = "hisilicon,hi6220-sysctrl", "syscon"; + reg = <0xf7030000 0x2000>; + #clock-cells = <1>; + }; + + /* Hi3519 system controller */ + system-controller@12010000 { + compatible = "hisilicon,hi3519-sysctrl", "syscon"; + reg = <0x12010000 0x1000>; + }; +... diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt deleted file mode 100644 index 8defacc44dd5b9e..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Hisilicon Hi3519 System Controller Block - -This bindings use the following binding: -Documentation/devicetree/bindings/mfd/syscon.yaml - -Required properties: -- compatible: "hisilicon,hi3519-sysctrl". -- reg: the register region of this block - -Examples: -sysctrl: system-controller@12010000 { - compatible = "hisilicon,hi3519-sysctrl", "syscon"; - reg = <0x12010000 0x1000>; -}; From patchwork Mon Sep 28 15:13:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372722 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R4746svz9sTM for ; Tue, 29 Sep 2020 01:18:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726863AbgI1PSZ (ORCPT ); Mon, 28 Sep 2020 11:18:25 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:37822 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726565AbgI1PRa (ORCPT ); Mon, 28 Sep 2020 11:17:30 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E62479A315EEB3B5ABEE; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:14 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 08/20] dt-bindings: arm: hisilicon: convert hisilicon,peri-subctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:12 +0800 Message-ID: <20200928151324.2134-9-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 PERI subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,peri-subctrl.txt | 16 ---------- .../controller/hisilicon,peri-subctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt deleted file mode 100644 index b96c2896078b914..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.txt +++ /dev/null @@ -1,16 +0,0 @@ -Hisilicon HiP05/HiP06 PERI sub system controller - -Required properties: -- compatible : "hisilicon,peri-subctrl", "syscon"; -- reg : Register address and size - -The PERI sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. The peripheral -controllers include mdio, ddr, iic, uart, timer and so on. - -Example: - /* for HiP05 sub peri system */ - peri_c_subctrl: syscon@80000000 { - compatible = "hisilicon,peri-subctrl", "syscon"; - reg = <0x0 0x80000000 0x0 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml new file mode 100644 index 000000000000000..838b1a2a2c8a9a1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,peri-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 PERI subsystem controller + +maintainers: + - Wei Xu + +description: | + The PERI sub system controller is shared by peripheral controllers in + HiP05 or HiP06 Soc to implement some basic configurations. The peripheral + controllers include mdio, ddr, iic, uart, timer and so on. + +properties: + compatible: + items: + - const: hisilicon,peri-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +examples: + - | + /* for HiP05 sub peri system */ + peri_c_subctrl: syscon@80000000 { + compatible = "hisilicon,peri-subctrl", "syscon"; + reg = <0x80000000 0x10000>; + }; +... From patchwork Mon Sep 28 15:13:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372716 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3b3xqhz9sVY for ; Tue, 29 Sep 2020 01:18:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726798AbgI1PR7 (ORCPT ); Mon, 28 Sep 2020 11:17:59 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14760 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726691AbgI1PRu (ORCPT ); Mon, 28 Sep 2020 11:17:50 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C5BB7C5288583ED04631; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:14 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 09/20] dt-bindings: arm: hisilicon: convert hisilicon,pcie-sas-subctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:13 +0800 Message-ID: <20200928151324.2134-10-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,pcie-sas-subctrl.txt | 15 --------- .../controller/hisilicon,pcie-sas-subctrl.yaml | 37 ++++++++++++++++++++++ 2 files changed, 37 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt deleted file mode 100644 index 1ef086bda81a3f5..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.txt +++ /dev/null @@ -1,15 +0,0 @@ -Hisilicon HiP05/HiP06 PCIe-SAS sub system controller - -Required properties: -- compatible : "hisilicon,pcie-sas-subctrl", "syscon"; -- reg : Register address and size - -The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 PCIe-SAS sub system */ - pcie_sas: system_controller@b0000000 { - compatible = "hisilicon,pcie-sas-subctrl", "syscon"; - reg = <0xb0000000 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml new file mode 100644 index 000000000000000..2de875ae781cf8a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pcie-sas-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller + +maintainers: + - Wei Xu + +description: | + The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in + HiP05 or HiP06 Soc to implement some basic configurations. + +properties: + compatible: + items: + - const: hisilicon,pcie-sas-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for HiP05 PCIe-SAS sub system */ + pcie_sas: system_controller@b0000000 { + compatible = "hisilicon,pcie-sas-subctrl", "syscon"; + reg = <0xb0000000 0x10000>; + }; +... From patchwork Mon Sep 28 15:13:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372721 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R434BGLz9sTM for ; Tue, 29 Sep 2020 01:18:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726865AbgI1PS0 (ORCPT ); Mon, 28 Sep 2020 11:18:26 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14759 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726629AbgI1PRb (ORCPT ); Mon, 28 Sep 2020 11:17:31 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B8AABE3B29F1C90710DA; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:15 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 10/20] dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:14 +0800 Message-ID: <20200928151324.2134-11-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon CPU controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------- .../hisilicon/controller/hisilicon,cpuctrl.yaml | 28 ++++++++++++++++++++++ 2 files changed, 28 insertions(+), 8 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt deleted file mode 100644 index ceffac537671668..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt +++ /dev/null @@ -1,8 +0,0 @@ -Hisilicon CPU controller - -Required properties: -- compatible : "hisilicon,cpuctrl" -- reg : Register address and size - -The clock registers and power registers of secondary cores are defined -in CPU controller, especially in HIX5HD2 SoC. diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml new file mode 100644 index 000000000000000..05b97e0bc35b090 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.yaml @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,cpuctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon CPU controller + +maintainers: + - Wei Xu + +description: | + The clock registers and power registers of secondary cores are defined + in CPU controller, especially in HIX5HD2 SoC. + +properties: + compatible: + items: + - const: hisilicon,cpuctrl + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg +... From patchwork Mon Sep 28 15:13:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372717 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3c3Hcgz9ryj for ; Tue, 29 Sep 2020 01:18:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726802AbgI1PSA (ORCPT ); Mon, 28 Sep 2020 11:18:00 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14323 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726694AbgI1PRg (ORCPT ); Mon, 28 Sep 2020 11:17:36 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id AB312D69C965B10A16DB; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:16 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 11/20] dt-bindings: arm: hisilicon: convert hisilicon,pctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:15 +0800 Message-ID: <20200928151324.2134-12-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon peripheral misc control register binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 --------- .../arm/hisilicon/controller/hisilicon,pctrl.yaml | 34 ++++++++++++++++++++++ 2 files changed, 34 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt deleted file mode 100644 index deec777bc3a850a..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.txt +++ /dev/null @@ -1,13 +0,0 @@ -PCTRL: Peripheral misc control register - -Required Properties: -- compatible: "hisilicon,pctrl" -- reg: Address and size of pctrl. - -Example: - - /* for Hi3620 */ - pctrl: pctrl@fca09000 { - compatible = "hisilicon,pctrl"; - reg = <0xfca09000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml new file mode 100644 index 000000000000000..8b00e9c222594f4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,pctrl.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,pctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral misc control register + +maintainers: + - Wei Xu + +description: Peripheral misc control register + +properties: + compatible: + items: + - const: hisilicon,pctrl + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for Hi3620 */ + pctrl: pctrl@fca09000 { + compatible = "hisilicon,pctrl"; + reg = <0xfca09000 0x1000>; + }; +... From patchwork Mon Sep 28 15:13:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372710 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R361t70z9sSJ for ; Tue, 29 Sep 2020 01:17:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726722AbgI1PRg (ORCPT ); Mon, 28 Sep 2020 11:17:36 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14758 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726667AbgI1PRf (ORCPT ); Mon, 28 Sep 2020 11:17:35 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B43DB21DEAD72E83E50D; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:16 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 12/20] dt-bindings: arm: hisilicon: convert hisilicon,hi3798cv200-perictrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:16 +0800 Message-ID: <20200928151324.2134-13-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi3798cv200-perictrl.txt | 21 ---------- .../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++++++++++++++++++++++ 2 files changed, 45 insertions(+), 21 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt deleted file mode 100644 index 0d5282f4670658d..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.txt +++ /dev/null @@ -1,21 +0,0 @@ -Hisilicon Hi3798CV200 Peripheral Controller - -The Hi3798CV200 Peripheral Controller controls peripherals, queries -their status, and configures some functions of peripherals. - -Required properties: -- compatible: Should contain "hisilicon,hi3798cv200-perictrl", "syscon" - and "simple-mfd". -- reg: Register address and size of Peripheral Controller. -- #address-cells: Should be 1. -- #size-cells: Should be 1. - -Examples: - - perictrl: peripheral-controller@8a20000 { - compatible = "hisilicon,hi3798cv200-perictrl", "syscon", - "simple-mfd"; - reg = <0x8a20000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml new file mode 100644 index 000000000000000..4e547017e368393 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi3798cv200-perictrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi3798CV200 Peripheral Controller + +maintainers: + - Wei Xu + +description: | + The Hi3798CV200 Peripheral Controller controls peripherals, queries + their status, and configures some functions of peripherals. + +properties: + compatible: + items: + - const: hisilicon,hi3798cv200-perictrl + - const: syscon + - const: simple-mfd + + reg: + description: Register address and size + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + +examples: + - | + perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; +... From patchwork Mon Sep 28 15:13:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372719 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3r4XQCz9sVJ for ; Tue, 29 Sep 2020 01:18:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726466AbgI1PSI (ORCPT ); Mon, 28 Sep 2020 11:18:08 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14761 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726615AbgI1PRe (ORCPT ); Mon, 28 Sep 2020 11:17:34 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C1308A9E82A37A76BA32; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:17 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 13/20] dt-bindings: arm: hisilicon: convert hisilicon,dsa-subctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:17 +0800 Message-ID: <20200928151324.2134-14-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon HiP05/HiP06 DSA subsystem controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 --------- .../controller/hisilicon,dsa-subctrl.yaml | 37 ++++++++++++++++++++++ 2 files changed, 37 insertions(+), 15 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt deleted file mode 100644 index 4d1c6abf03f6f97..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.txt +++ /dev/null @@ -1,15 +0,0 @@ -Hisilicon HiP05/HiP06 DSA sub system controller - -Required properties: -- compatible : "hisilicon,dsa-subctrl", "syscon"; -- reg : Register address and size - -The DSA sub system controller is shared by peripheral controllers in -HiP05 or HiP06 Soc to implement some basic configurations. - -Example: - /* for HiP05 dsa sub system */ - pcie_sas: system_controller@a0000000 { - compatible = "hisilicon,dsa-subctrl", "syscon"; - reg = <0xa0000000 0x10000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml new file mode 100644 index 000000000000000..3e18fd8debd92f3 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,dsa-subctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon HiP05/HiP06 DSA subsystem controller + +maintainers: + - Wei Xu + +description: | + The DSA sub system controller is shared by peripheral controllers in + HiP05 or HiP06 Soc to implement some basic configurations. + +properties: + compatible: + items: + - const: hisilicon,dsa-subctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for HiP05 dsa sub system */ + pcie_sas: system_controller@a0000000 { + compatible = "hisilicon,dsa-subctrl", "syscon"; + reg = <0xa0000000 0x10000>; + }; +... From patchwork Mon Sep 28 15:13:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372714 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3T0dh9z9sVL for ; Tue, 29 Sep 2020 01:17:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726693AbgI1PRz (ORCPT ); Mon, 28 Sep 2020 11:17:55 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14322 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726672AbgI1PRh (ORCPT ); Mon, 28 Sep 2020 11:17:37 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id AFFD115277287867032E; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:17 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 14/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-fabric bindings to json-schema Date: Mon, 28 Sep 2020 23:13:18 +0800 Message-ID: <20200928151324.2134-15-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Fabric controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hip04-fabric.txt | 5 ----- .../controller/hisilicon,hip04-fabric.yaml | 26 ++++++++++++++++++++++ 2 files changed, 26 insertions(+), 5 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt deleted file mode 100644 index 40453d02f2024bd..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.txt +++ /dev/null @@ -1,5 +0,0 @@ -Fabric: - -Required Properties: -- compatible: "hisilicon,hip04-fabric"; -- reg: Address and size of Fabric diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml new file mode 100644 index 000000000000000..47a2ec6a4704f4c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hip04-fabric.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Fabric controller + +maintainers: + - Wei Xu + +description: Hisilicon Fabric controller + +properties: + compatible: + items: + - const: hisilicon,hip04-fabric + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg +... From patchwork Mon Sep 28 15:13:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372709 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R2x2Cd5z9sSn for ; Tue, 29 Sep 2020 01:17:29 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726567AbgI1PR2 (ORCPT ); Mon, 28 Sep 2020 11:17:28 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:37818 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726566AbgI1PR1 (ORCPT ); Mon, 28 Sep 2020 11:17:27 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id E11FCAB5BEF7581E3E4D; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:18 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 15/20] dt-bindings: arm: hisilicon: convert hisilicon,hip04-bootwrapper bindings to json-schema Date: Mon, 28 Sep 2020 23:13:19 +0800 Message-ID: <20200928151324.2134-16-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Bootwrapper boot method binding to DT schema format using json-schema. The property boot-method contains two groups of physical address range information: bootwrapper and relocation. The "uint32-array" type is not suitable for it, because the field "address" and "size" may occupy one or two cells respectively. Use "minItems: 1" and "maxItems: 2" to allow it can be written in "" or ", " format. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hip04-bootwrapper.txt | 9 ------ .../controller/hisilicon,hip04-bootwrapper.yaml | 32 ++++++++++++++++++++++ 2 files changed, 32 insertions(+), 9 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt deleted file mode 100644 index b0d53333f4fdae1..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.txt +++ /dev/null @@ -1,9 +0,0 @@ -Bootwrapper boot method (software protocol on SMP): - -Required Properties: -- compatible: "hisilicon,hip04-bootwrapper"; -- boot-method: Address and size of boot method. - [0]: bootwrapper physical address - [1]: bootwrapper size - [2]: relocation physical address - [3]: relocation size diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml new file mode 100644 index 000000000000000..d88ef8487879fc1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hip04-bootwrapper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bootwrapper boot method + +maintainers: + - Wei Xu + +description: Bootwrapper boot method (software protocol on SMP) + +properties: + compatible: + items: + - const: hisilicon,hip04-bootwrapper + + boot-method: + description: | + Address and size of boot method. + [0]: bootwrapper physical address + [1]: bootwrapper size + [2]: relocation physical address + [3]: relocation size + minItems: 1 + maxItems: 2 + +required: + - compatible + - boot-method +... From patchwork Mon Sep 28 15:13:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372720 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3t0Qz1z9sSt for ; Tue, 29 Sep 2020 01:18:18 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726684AbgI1PSR (ORCPT ); Mon, 28 Sep 2020 11:18:17 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:14762 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726617AbgI1PRb (ORCPT ); Mon, 28 Sep 2020 11:17:31 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id BCCC113061393D79571E; Mon, 28 Sep 2020 23:17:24 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 16/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-aoctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:20 +0800 Message-ID: <20200928151324.2134-17-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Power Always ON domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-aoctrl.txt | 18 ---------- .../controller/hisilicon,hi6220-aoctrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt deleted file mode 100644 index 5a723c1d45f4a17..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Always ON domain controller - -Required properties: -- compatible : "hisilicon,hi6220-aoctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power always -on domain for mobile platform. - -Example: - /*for Hi6220*/ - ao_ctrl: ao_ctrl@f7800000 { - compatible = "hisilicon,hi6220-aoctrl", "syscon"; - reg = <0x0 0xf7800000 0x0 0x2000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml new file mode 100644 index 000000000000000..6939fe85e1895f6 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-aoctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Power Always ON domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the power always + on domain for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-aoctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /*for Hi6220*/ + ao_ctrl: ao_ctrl@f7800000 { + compatible = "hisilicon,hi6220-aoctrl", "syscon"; + reg = <0xf7800000 0x2000>; + #clock-cells = <1>; + }; +... From patchwork Mon Sep 28 15:13:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372718 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3q5CHzz9sSt for ; Tue, 29 Sep 2020 01:18:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726823AbgI1PSJ (ORCPT ); Mon, 28 Sep 2020 11:18:09 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14257 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726684AbgI1PRe (ORCPT ); Mon, 28 Sep 2020 11:17:34 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id C5873411824F303FF16B; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 17/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-mediactrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:21 +0800 Message-ID: <20200928151324.2134-18-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Media domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-mediactrl.txt | 18 ---------- .../controller/hisilicon,hi6220-mediactrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt deleted file mode 100644 index dcfdcbcb6455771..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Media domain controller - -Required properties: -- compatible : "hisilicon,hi6220-mediactrl" -- reg : Register address and size -- #clock-cells: should be set to 1, many clock registers are defined - under this controller and this property must be present. - -Hisilicon designs this system controller to control the multimedia -domain(e.g. codec, G3D ...) for mobile platform. - -Example: - /*for Hi6220*/ - media_ctrl: media_ctrl@f4410000 { - compatible = "hisilicon,hi6220-mediactrl", "syscon"; - reg = <0x0 0xf4410000 0x0 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml new file mode 100644 index 000000000000000..d6edbe8773a103b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-mediactrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Media domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the multimedia + domain(e.g. codec, G3D ...) for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-mediactrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /* for Hi6220 */ + media_ctrl: media_ctrl@f4410000 { + compatible = "hisilicon,hi6220-mediactrl", "syscon"; + reg = <0xf4410000 0x1000>; + #clock-cells = <1>; + }; +... From patchwork Mon Sep 28 15:13:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372715 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3Z0nDTz9sVV for ; Tue, 29 Sep 2020 01:18:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726729AbgI1PRg (ORCPT ); Mon, 28 Sep 2020 11:17:36 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14259 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726686AbgI1PRf (ORCPT ); Mon, 28 Sep 2020 11:17:35 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D00FCE9BE18A85133902; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:19 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 18/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-pmctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:22 +0800 Message-ID: <20200928151324.2134-19-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 Power Management domain controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-pmctrl.txt | 18 ---------- .../controller/hisilicon,hi6220-pmctrl.yaml | 42 ++++++++++++++++++++++ 2 files changed, 42 insertions(+), 18 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt deleted file mode 100644 index 972842f07b5a2ce..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -Hisilicon Hi6220 Power Management domain controller - -Required properties: -- compatible : "hisilicon,hi6220-pmctrl" -- reg : Register address and size -- #clock-cells: should be set to 1, some clock registers are define - under this controller and this property must be present. - -Hisilicon designs this system controller to control the power management -domain for mobile platform. - -Example: - /*for Hi6220*/ - pm_ctrl: pm_ctrl@f7032000 { - compatible = "hisilicon,hi6220-pmctrl", "syscon"; - reg = <0x0 0xf7032000 0x0 0x1000>; - #clock-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml new file mode 100644 index 000000000000000..978a6920d69c217 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-pmctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 Power Management domain controller + +maintainers: + - Wei Xu + +description: | + Hisilicon designs this system controller to control the power management + domain for mobile platform. + +properties: + compatible: + items: + - const: hisilicon,hi6220-pmctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +examples: + - | + /* for Hi6220 */ + pm_ctrl: pm_ctrl@f7032000 { + compatible = "hisilicon,hi6220-pmctrl", "syscon"; + reg = <0xf7032000 0x1000>; + #clock-cells = <1>; + }; +... From patchwork Mon Sep 28 15:13:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372712 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3N1xYDz9sTv for ; Tue, 29 Sep 2020 01:17:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726573AbgI1PRu (ORCPT ); Mon, 28 Sep 2020 11:17:50 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14260 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726693AbgI1PRi (ORCPT ); Mon, 28 Sep 2020 11:17:38 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D4BB6B6F12FD7EBCC3EA; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:20 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 19/20] dt-bindings: arm: hisilicon: convert hisilicon,hi6220-sramctrl bindings to json-schema Date: Mon, 28 Sep 2020 23:13:23 +0800 Message-ID: <20200928151324.2134-20-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hi6220 SRAM controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../controller/hisilicon,hi6220-sramctrl.txt | 16 --------- .../controller/hisilicon,hi6220-sramctrl.yaml | 38 ++++++++++++++++++++++ 2 files changed, 38 insertions(+), 16 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt deleted file mode 100644 index 086b7acccc5edc4..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.txt +++ /dev/null @@ -1,16 +0,0 @@ -Hisilicon Hi6220 SRAM controller - -Required properties: -- compatible : "hisilicon,hi6220-sramctrl", "syscon" -- reg : Register address and size - -Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several -SRAM banks for power management, modem, security, etc. Further, use "syscon" -managing the common sram which can be shared by multiple modules. - -Example: - /*for Hi6220*/ - sram: sram@fff80000 { - compatible = "hisilicon,hi6220-sramctrl", "syscon"; - reg = <0x0 0xfff80000 0x0 0x12000>; - }; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml new file mode 100644 index 000000000000000..4ac1e14420ecfe7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/controller/hisilicon,hi6220-sramctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi6220 SRAM controller + +maintainers: + - Wei Xu + +description: | + Hisilicon's SoCs use SRAM for consistency purpose; on Hi6220 there have + several SRAM banks for power management, modem, security, etc. Further, use + "syscon" managing the common sram which can be shared by multiple modules. + +properties: + compatible: + items: + - const: hisilicon,hi6220-sramctrl + - const: syscon + + reg: + description: Register address and size + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + /* for Hi6220 */ + sram: sram@fff80000 { + compatible = "hisilicon,hi6220-sramctrl", "syscon"; + reg = <0xfff80000 0x12000>; + }; +... From patchwork Mon Sep 28 15:13:24 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen (ThunderTown)" X-Patchwork-Id: 1372711 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=huawei.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0R3M3rKfz9sT6 for ; Tue, 29 Sep 2020 01:17:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726651AbgI1PRi (ORCPT ); Mon, 28 Sep 2020 11:17:38 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:14258 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726685AbgI1PRi (ORCPT ); Mon, 28 Sep 2020 11:17:38 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id CB0E52C6F86EFDA2BF55; Mon, 28 Sep 2020 23:17:29 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Mon, 28 Sep 2020 23:17:21 +0800 From: Zhen Lei To: Wei Xu , Rob Herring , "Jonathan Cameron" , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei , Libin , Kefeng Wang Subject: [PATCH v4 20/20] dt-bindings: arm: hisilicon: convert LPC controller bindings to json-schema Date: Mon, 28 Sep 2020 23:13:24 +0800 Message-ID: <20200928151324.2134-21-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200928151324.2134-1-thunder.leizhen@huawei.com> References: <20200928151324.2134-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller binding to DT schema format using json-schema. Signed-off-by: Zhen Lei --- .../arm/hisilicon/hisilicon-low-pin-count.txt | 33 ------------ .../arm/hisilicon/hisilicon-low-pin-count.yaml | 61 ++++++++++++++++++++++ 2 files changed, 61 insertions(+), 33 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt deleted file mode 100644 index 10bd35f9207f2ee..000000000000000 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hip06 Low Pin Count device - Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which - provides I/O access to some legacy ISA devices. - Hip06 is based on arm64 architecture where there is no I/O space. So, the - I/O ports here are not CPU addresses, and there is no 'ranges' property in - LPC device node. - -Required properties: -- compatible: value should be as follows: - (a) "hisilicon,hip06-lpc" - (b) "hisilicon,hip07-lpc" -- #address-cells: must be 2 which stick to the ISA/EISA binding doc. -- #size-cells: must be 1 which stick to the ISA/EISA binding doc. -- reg: base memory range where the LPC register set is mapped. - -Note: - The node name before '@' must be "isa" to represent the binding stick to the - ISA/EISA binding specification. - -Example: - -isa@a01b0000 { - compatible = "hisilicon,hip06-lpc"; - #address-cells = <2>; - #size-cells = <1>; - reg = <0x0 0xa01b0000 0x0 0x1000>; - - ipmi0: bt@e4 { - compatible = "ipmi-bt"; - device_type = "ipmi"; - reg = <0x01 0xe4 0x04>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml new file mode 100644 index 000000000000000..83ca10adce71b62 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon-low-pin-count.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/hisilicon/hisilicon-low-pin-count.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hip06 Low Pin Count device + +maintainers: + - Wei Xu + +description: | + Hisilicon Hip06 SoCs implement a Low Pin Count (LPC) controller, which + provides I/O access to some legacy ISA devices. + Hip06 is based on arm64 architecture where there is no I/O space. So, the + I/O ports here are not CPU addresses, and there is no 'ranges' property in + LPC device node. + +properties: + $nodename: + pattern: '^isa@[0-9a-f]+$' + description: | + The node name before '@' must be "isa" to represent the binding stick + to the ISA/EISA binding specification. + + compatible: + enum: + - hisilicon,hip06-lpc + - hisilicon,hip07-lpc + + reg: + description: base memory range where the LPC register set is mapped. + maxItems: 1 + + '#address-cells': + description: must be 2 which stick to the ISA/EISA binding doc. + const: 2 + + '#size-cells': + description: must be 1 which stick to the ISA/EISA binding doc. + const: 1 + +required: + - compatible + - reg + +examples: + - | + isa@a01b0000 { + compatible = "hisilicon,hip06-lpc"; + #address-cells = <2>; + #size-cells = <1>; + reg = <0xa01b0000 0x1000>; + + ipmi0: bt@e4 { + compatible = "ipmi-bt"; + device_type = "ipmi"; + reg = <0x01 0xe4 0x04>; + }; + }; +...