From patchwork Mon Sep 28 13:09:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenbin Mei X-Patchwork-Id: 1372634 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=ejd1jfvl; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0NGX2lLNz9sSt for ; Mon, 28 Sep 2020 23:12:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726636AbgI1NMI (ORCPT ); Mon, 28 Sep 2020 09:12:08 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:42469 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726420AbgI1NMI (ORCPT ); Mon, 28 Sep 2020 09:12:08 -0400 X-UUID: b79edfd489db467abf4ced38fa12a981-20200928 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=RmF0tm+UMBd9q3YMcUDVZlTLEPODEY6oE6ZT2KlT9JA=; b=ejd1jfvlIikH4CDriUlbweejVmrTIZTNlSQoG/9sj4iSCrHZH85qJLhhm0ZdWm2EGIjBd+nmTs38/BUi/mPVIMa41bNgLX1GhYdvzdEyPV6oyETG7CIWjF776YoDmTG+7dLzhiN1GRVidpGCEK4UWCOXGeT7JrtVSsZwR5xu7qU=; X-UUID: b79edfd489db467abf4ced38fa12a981-20200928 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1235327967; Mon, 28 Sep 2020 21:12:00 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Sep 2020 21:11:58 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Sep 2020 21:11:58 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , , , , , , , Wenbin Mei Subject: [PATCH v2 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema Date: Mon, 28 Sep 2020 21:09:15 +0800 Message-ID: <20200928130918.32326-2-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200928130918.32326-1-wenbin.mei@mediatek.com> References: <20200928130918.32326-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the mtk-sd binding to DT schema format using json-schema. Signed-off-by: Wenbin Mei Reviewed-by: Ulf Hansson --- .../devicetree/bindings/mmc/mtk-sd.txt | 75 -------- .../devicetree/bindings/mmc/mtk-sd.yaml | 165 ++++++++++++++++++ 2 files changed, 165 insertions(+), 75 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt deleted file mode 100644 index 26a8f320a156..000000000000 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ /dev/null @@ -1,75 +0,0 @@ -* MTK MMC controller - -The MTK MSDC can act as a MMC controller -to support MMC, SD, and SDIO types of memory cards. - -This file documents differences between the core properties in mmc.txt -and the properties used by the msdc driver. - -Required properties: -- compatible: value should be either of the following. - "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135 - "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 - "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 - "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516 - "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779 - "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 - "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 - "mediatek,mt7622-mmc": for MT7622 SoC - "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC - "mediatek,mt7620-mmc", for MT7621 SoC (and others) - -- reg: physical base address of the controller and length -- interrupts: Should contain MSDC interrupt number -- clocks: Should contain phandle for the clock feeding the MMC controller -- clock-names: Should contain the following: - "source" - source clock (required) - "hclk" - HCLK which used for host (required) - "source_cg" - independent source clock gate (required for MT2712) - "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3) -- pinctrl-names: should be "default", "state_uhs" -- pinctrl-0: should contain default/high speed pin ctrl -- pinctrl-1: should contain uhs mode pin ctrl -- vmmc-supply: power to the Core -- vqmmc-supply: power to the IO - -Optional properties: -- assigned-clocks: PLL of the source clock -- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock -- hs400-ds-delay: HS400 DS delay setting -- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting. - This field has total 32 stages. - The value is an integer from 0 to 31. -- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting - This field has total 32 stages. - The value is an integer from 0 to 31. -- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection - If present,HS400 command responses are sampled on rising edges. - If not present,HS400 command responses are sampled on falling edges. -- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc - error caused by stop clock(fifo full) - Valid range = [0:0x7]. if not present, default value is 0. - applied to compatible "mediatek,mt2701-mmc". -- resets: Phandle and reset specifier pair to softreset line of MSDC IP. -- reset-names: Should be "hrst". - -Examples: -mmc0: mmc@11230000 { - compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc"; - reg = <0 0x11230000 0 0x108>; - interrupts = ; - vmmc-supply = <&mt6397_vemc_3v3_reg>; - vqmmc-supply = <&mt6397_vio18_reg>; - clocks = <&pericfg CLK_PERI_MSDC30_0>, - <&topckgen CLK_TOP_MSDC50_0_H_SEL>; - clock-names = "source", "hclk"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_pins_default>; - pinctrl-1 = <&mmc0_pins_uhs>; - assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; - hs400-ds-delay = <0x14015>; - mediatek,hs200-cmd-int-delay = <26>; - mediatek,hs400-cmd-int-delay = <14>; - mediatek,hs400-cmd-resp-sel-rising; -}; diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml new file mode 100644 index 000000000000..2d5ab1411cd5 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -0,0 +1,165 @@ +# MTK-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MTK MSDC Storage Host Controller Binding + +maintainers: + - Ulf Hansson + +allOf: + - $ref: mmc-controller.yaml# + +properties: + compatible: + oneOf: + - const: mediatek,mt8135-mmc + - const: mediatek,mt8173-mmc + - const: mediatek,mt8183-mmc + - const: mediatek,mt8516-mmc + - const: mediatek,mt6779-mmc + - const: mediatek,mt2701-mmc + - const: mediatek,mt2712-mmc + - const: mediatek,mt7622-mmc + - items: + - const: mediatek,mt7623-mmc + - const: mediatek,mt2701-mmc + - const: mediatek,mt7620-mmc + + reg: + description: + physical base address of the controller and length. + minItems: 1 + maxItems: 2 + + interrupts: + description: + Should contain MSDC interrupt number. + maxItems: 1 + + clocks: + description: + Should contain phandle for the clock feeding the MMC controller. + minItems: 2 + maxItems: 4 + items: + - description: source clock (required). + - description: HCLK which used for host (required). + - description: independent source clock gate (required for MT2712). + - description: bus clock used for internal register access (required for MT2712 MSDC0/3). + + clock-names: + minItems: 2 + maxItems: 4 + items: + - const: source + - const: hclk + - const: source_cg + - const: bus_clk + + pinctrl-names: + items: + - const: default + - const: state_uhs + + pinctrl-0: + description: + should contain default/high speed pin ctrl. + maxItems: 1 + + pinctrl-1: + description: + should contain uhs mode pin ctrl. + maxItems: 1 + + vmmc-supply: + description: + power to the Core. + + vqmmc-supply: + description: + power to the IO. + + assigned-clocks: + description: + PLL of the source clock. + + assigned-clock-parents: + description: + parent of source clock, used for HS400 mode to get 400Mhz source clock. + + hs400-ds-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + HS400 DS delay setting. + + mediatek,hs200-cmd-int-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + HS200 command internal delay setting. + This field has total 32 stages. + The value is an integer from 0 to 31. + + mediatek,hs400-cmd-int-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + HS400 command internal delay setting. + This field has total 32 stages. + The value is an integer from 0 to 31. + + mediatek,hs400-cmd-resp-sel-rising: + $ref: /schemas/types.yaml#/definitions/flag + description: + HS400 command response sample selection. + If present, HS400 command responses are sampled on rising edges. + If not present, HS400 command responses are sampled on falling edges. + + mediatek,latch-ck: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Some SoCs do not support enhance_rx, need set correct latch-ck to avoid + data crc error caused by stop clock(fifo full) Valid range = [0:0x7]. + if not present, default value is 0. + applied to compatible "mediatek,mt2701-mmc". + + resets: + maxItems: 1 + + reset-names: + const: hrst + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + #include + #include + mmc0: mmc@11230000 { + compatible = "mediatek,mt8173-mmc"; + reg = <0x11230000 0x1000>; + interrupts = ; + vmmc-supply = <&mt6397_vemc_3v3_reg>; + vqmmc-supply = <&mt6397_vio18_reg>; + clocks = <&pericfg CLK_PERI_MSDC30_0>, + <&topckgen CLK_TOP_MSDC50_0_H_SEL>; + clock-names = "source", "hclk"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + hs400-ds-delay = <0x14015>; + mediatek,hs200-cmd-int-delay = <26>; + mediatek,hs400-cmd-int-delay = <14>; + mediatek,hs400-cmd-resp-sel-rising; + }; + +... From patchwork Mon Sep 28 13:09:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wenbin Mei X-Patchwork-Id: 1372632 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=HvKeEfGO; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4C0NGJ3X6Zz9sSC for ; Mon, 28 Sep 2020 23:12:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726600AbgI1NMH (ORCPT ); Mon, 28 Sep 2020 09:12:07 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:58431 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726406AbgI1NMH (ORCPT ); Mon, 28 Sep 2020 09:12:07 -0400 X-UUID: cc9ed33b293a4a838e9619e13d966e25-20200928 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=DtzmUqahNr9vlnFcH4gqWuTWGefpuIcJc/bsggr42oY=; b=HvKeEfGOz1iBh+8MqCmHBCX4FKeEF9yAl+Vv9xh4MNbQ/5kcXRjuUqOFRSJZIt5+uh9+wnbxfeb07nMhEyeYvKEhfB4s0AHXWNHdRRXILjzsYt5wAHE8WPwcbLoqWXVFJUzN5ZvyUspmbXN3YsoWUGMl5/gqfLLRQkE8CL8Ryyg=; X-UUID: cc9ed33b293a4a838e9619e13d966e25-20200928 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.14 Build 0819 with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2016316891; Mon, 28 Sep 2020 21:12:01 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 28 Sep 2020 21:11:59 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 28 Sep 2020 21:11:59 +0800 From: Wenbin Mei To: Ulf Hansson , Rob Herring CC: Chaotian Jing , Matthias Brugger , , , , , , , Wenbin Mei Subject: [PATCH v2 2/4] mmc: dt-bindings: add support for MT8192 SoC Date: Mon, 28 Sep 2020 21:09:16 +0800 Message-ID: <20200928130918.32326-3-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200928130918.32326-1-wenbin.mei@mediatek.com> References: <20200928130918.32326-1-wenbin.mei@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT8192 mmc host ip is compatible with MT8183. Add support for this. Signed-off-by: Wenbin Mei Reviewed-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 2d5ab1411cd5..f12a44f3e6c4 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -18,6 +18,9 @@ properties: - const: mediatek,mt8135-mmc - const: mediatek,mt8173-mmc - const: mediatek,mt8183-mmc + - items: + - const: mediatek,mt8192-mmc + - const: mediatek,mt8183-mmc - const: mediatek,mt8516-mmc - const: mediatek,mt6779-mmc - const: mediatek,mt2701-mmc @@ -43,21 +46,29 @@ properties: description: Should contain phandle for the clock feeding the MMC controller. minItems: 2 - maxItems: 4 + maxItems: 8 items: - description: source clock (required). - description: HCLK which used for host (required). - description: independent source clock gate (required for MT2712). - description: bus clock used for internal register access (required for MT2712 MSDC0/3). + - description: msdc subsys clock gate (required for MT8192). + - description: peripheral bus clock gate (required for MT8192). + - description: AXI bus clock gate (required for MT8192). + - description: AHB bus clock gate (required for MT8192). clock-names: minItems: 2 - maxItems: 4 + maxItems: 8 items: - const: source - const: hclk - const: source_cg - const: bus_clk + - const: sys_cg + - const: pclk_cg + - const: axi_cg + - const: ahb_cg pinctrl-names: items: