From patchwork Sun Sep 20 14:16:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 1367896 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sartura.hr Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sartura-hr.20150623.gappssmtp.com header.i=@sartura-hr.20150623.gappssmtp.com header.a=rsa-sha256 header.s=20150623 header.b=kVPF78Lk; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BvV5C63Zmz9sTR for ; Mon, 21 Sep 2020 00:17:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726495AbgITORQ (ORCPT ); Sun, 20 Sep 2020 10:17:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726473AbgITORN (ORCPT ); Sun, 20 Sep 2020 10:17:13 -0400 Received: from mail-ej1-x642.google.com (mail-ej1-x642.google.com [IPv6:2a00:1450:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0760C0613CE for ; Sun, 20 Sep 2020 07:17:12 -0700 (PDT) Received: by mail-ej1-x642.google.com with SMTP id z23so14151978ejr.13 for ; Sun, 20 Sep 2020 07:17:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sartura-hr.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+JO/vRiLXpeB8VcV6Xg2lUUCdaWgeJtk26slYXjrIcM=; b=kVPF78Lk6Cp5dE4yxE87CaAATTpMf17aqwpZaTTnmiLSX0XkfcIL9ku0G6wo8pc166 DGt1S/I0bMCHEkimHAljEcD9pkcWumWyW8f+RTO2PIAoHuoU8HmKeLaCkS85z4DXIb51 dz3WxxhdsSzcMCeFCfn4C02zrN9R1BG4joHupNJLMlKdjw1BdL826vw2qXRVJuvCHDTy 26tCpafQffvGyRIw2fdZWeDjWi3gWBn/GhFhxLEVmZ7ZZo/qsQdOmZzcZjqXPFGNtaxw Mx2OJyups3Xvm9BWOobx1WmN9l9LFIzJ3x8jVGG1rKZXIsbLmO4cifR9u41li6yMOAau uwAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+JO/vRiLXpeB8VcV6Xg2lUUCdaWgeJtk26slYXjrIcM=; b=pm1fyd2X+KovYc8ynftV29YCBLGPzc5cCTOBkNuUJbkbBoGs7YnNNdyVj2CqZCx5jU 2O+o4rEyJXFgBVDZwJ9trd7PVEKgJPnq7dpF87azlRymAVSOn0S7QTSBJNUojk+nprLj 3YHRJT1W8Edpo2xKczhmbbAKV1RLT9mORs9S9gYT4edKI+fWoBcIbGTtO+am1nRtYI9G mrU18bGk9uj8Ek7uyLeraR3b3PuMHg9ncrmFBZTp4qGjJ+aAi3yOhMHhH+4g9SyW2zJK dMPItAwbhi3uOVYx0HN7BMGZg8mZpJNWVfXOmIeA0wgnDk/4hotsaxAGr49d715VlS4D +Nuw== X-Gm-Message-State: AOAM531LbIKaZT5AgH1xI7Pyl290mcWBv2PLJZC4xLrPTFWQDcvo3UQ3 s6zWof4jyiFSXPECTB7KIQILUQ== X-Google-Smtp-Source: ABdhPJwe7XrfvJeQ3xYFqReAUWmjkfls9M9MEc+Z4rWAC/WljKmLvF8sx3ECxUnfsYw9CqLQpwelwQ== X-Received: by 2002:a17:906:fb15:: with SMTP id lz21mr33165218ejb.185.1600611431475; Sun, 20 Sep 2020 07:17:11 -0700 (PDT) Received: from localhost.localdomain ([88.207.4.31]) by smtp.googlemail.com with ESMTPSA id g11sm6631594edt.88.2020.09.20.07.17.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2020 07:17:10 -0700 (PDT) From: Robert Marko To: andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko , Luka Perkov , Florian Fainelli Subject: [PATCH v4 1/2] net: mdio-ipq4019: change defines to upper case Date: Sun, 20 Sep 2020 16:16:52 +0200 Message-Id: <20200920141653.357493-2-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200920141653.357493-1-robert.marko@sartura.hr> References: <20200920141653.357493-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org In the commit adding the IPQ4019 MDIO driver, defines for timeout and sleep partially used lower case. Lets change it to upper case in line with the rest of driver defines. Signed-off-by: Robert Marko Cc: Luka Perkov Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli --- drivers/net/phy/mdio-ipq4019.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/mdio-ipq4019.c b/drivers/net/phy/mdio-ipq4019.c index 1ce81ff2f41d..64b169e5a699 100644 --- a/drivers/net/phy/mdio-ipq4019.c +++ b/drivers/net/phy/mdio-ipq4019.c @@ -21,8 +21,8 @@ #define MDIO_CMD_ACCESS_CODE_READ 0 #define MDIO_CMD_ACCESS_CODE_WRITE 1 -#define ipq4019_MDIO_TIMEOUT 10000 -#define ipq4019_MDIO_SLEEP 10 +#define IPQ4019_MDIO_TIMEOUT 10000 +#define IPQ4019_MDIO_SLEEP 10 struct ipq4019_mdio_data { void __iomem *membase; @@ -35,7 +35,7 @@ static int ipq4019_mdio_wait_busy(struct mii_bus *bus) return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy, (busy & MDIO_CMD_ACCESS_BUSY) == 0, - ipq4019_MDIO_SLEEP, ipq4019_MDIO_TIMEOUT); + IPQ4019_MDIO_SLEEP, IPQ4019_MDIO_TIMEOUT); } static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) From patchwork Sun Sep 20 14:16:53 2020 Content-Type: text/plain; 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Sun, 20 Sep 2020 07:17:12 -0700 (PDT) From: Robert Marko To: andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, kuba@kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko , Luka Perkov Subject: [PATCH v4 2/2] net: mdio-ipq4019: add Clause 45 support Date: Sun, 20 Sep 2020 16:16:53 +0200 Message-Id: <20200920141653.357493-3-robert.marko@sartura.hr> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200920141653.357493-1-robert.marko@sartura.hr> References: <20200920141653.357493-1-robert.marko@sartura.hr> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org While up-streaming the IPQ4019 driver it was thought that the controller had no Clause 45 support, but it actually does and its activated by writing a bit to the mode register. So lets add it as newer SoC-s use the same controller and Clause 45 compliant PHY-s. Signed-off-by: Robert Marko Cc: Luka Perkov Reviewed-by: Andrew Lunn --- Changes since v3: * Rename MDIO_MODE_BIT to MDIO_MODE_C45 Changes since v2: * Fix missed reverse christmas tree Changes since v1: * Maintain reverse christmas tree drivers/net/phy/mdio-ipq4019.c | 103 ++++++++++++++++++++++++++++----- 1 file changed, 89 insertions(+), 14 deletions(-) diff --git a/drivers/net/phy/mdio-ipq4019.c b/drivers/net/phy/mdio-ipq4019.c index 64b169e5a699..25c25ea6da66 100644 --- a/drivers/net/phy/mdio-ipq4019.c +++ b/drivers/net/phy/mdio-ipq4019.c @@ -12,6 +12,7 @@ #include #include +#define MDIO_MODE_REG 0x40 #define MDIO_ADDR_REG 0x44 #define MDIO_DATA_WRITE_REG 0x48 #define MDIO_DATA_READ_REG 0x4c @@ -20,6 +21,12 @@ #define MDIO_CMD_ACCESS_START BIT(8) #define MDIO_CMD_ACCESS_CODE_READ 0 #define MDIO_CMD_ACCESS_CODE_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_ADDR 0 +#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_READ 2 + +/* 0 = Clause 22, 1 = Clause 45 */ +#define MDIO_MODE_C45 BIT(8) #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 @@ -41,19 +48,44 @@ static int ipq4019_mdio_wait_busy(struct mii_bus *bus) static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) { struct ipq4019_mdio_data *priv = bus->priv; + unsigned int data; unsigned int cmd; - /* Reject clause 45 */ - if (regnum & MII_ADDR_C45) - return -EOPNOTSUPP; - if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; - /* issue the phy address and reg */ - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + /* Clause 45 support */ + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + /* Enter Clause 45 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data |= MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and mmd */ + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); + + /* issue reg */ + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; + } else { + /* Enter Clause 22 mode */ + data = readl(priv->membase + MDIO_MODE_REG); - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; + data &= ~MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ; + } /* issue read command */ writel(cmd, priv->membase + MDIO_CMD_REG); @@ -62,6 +94,15 @@ static int ipq4019_mdio_read(struct mii_bus *bus, int mii_id, int regnum) if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; + if (regnum & MII_ADDR_C45) { + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ; + + writel(cmd, priv->membase + MDIO_CMD_REG); + + if (ipq4019_mdio_wait_busy(bus)) + return -ETIMEDOUT; + } + /* Read and return data */ return readl(priv->membase + MDIO_DATA_READ_REG); } @@ -70,23 +111,57 @@ static int ipq4019_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value) { struct ipq4019_mdio_data *priv = bus->priv; + unsigned int data; unsigned int cmd; - /* Reject clause 45 */ - if (regnum & MII_ADDR_C45) - return -EOPNOTSUPP; - if (ipq4019_mdio_wait_busy(bus)) return -ETIMEDOUT; - /* issue the phy address and reg */ - writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + /* Clause 45 support */ + if (regnum & MII_ADDR_C45) { + unsigned int mmd = (regnum >> 16) & 0x1F; + unsigned int reg = regnum & 0xFFFF; + + /* Enter Clause 45 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data |= MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and mmd */ + writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG); + + /* issue reg */ + writel(reg, priv->membase + MDIO_DATA_WRITE_REG); + + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR; + + writel(cmd, priv->membase + MDIO_CMD_REG); + + if (ipq4019_mdio_wait_busy(bus)) + return -ETIMEDOUT; + } else { + /* Enter Clause 22 mode */ + data = readl(priv->membase + MDIO_MODE_REG); + + data &= ~MDIO_MODE_C45; + + writel(data, priv->membase + MDIO_MODE_REG); + + /* issue the phy address and reg */ + writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG); + } /* issue write data */ writel(value, priv->membase + MDIO_DATA_WRITE_REG); - cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; /* issue write command */ + if (regnum & MII_ADDR_C45) + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE; + else + cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE; + writel(cmd, priv->membase + MDIO_CMD_REG); /* Wait write complete */