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[81.134.41.189]) by smtp.gmail.com with ESMTPSA id e132sm8672157wmd.40.2017.12.23.16.36.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Dec 2017 16:36:18 -0800 (PST) Received: by Jamess-MacBook.local (Postfix, from userid 501) id 07567200BBF3D4; Sun, 24 Dec 2017 00:36:17 +0000 (GMT) From: James Clarke To: gcc-patches@gcc.gnu.org Cc: James Clarke Subject: [PATCH v2] PR rtl-optimization/83565: Fix 32-bit rotate on ia64 Date: Sun, 24 Dec 2017 00:36:13 +0000 Message-Id: <20171224003613.91791-1-jrtc27@jrtc27.com> In-Reply-To: <20171224003153.91119-1-jrtc27@debian.org> References: <20171224003153.91119-1-jrtc27@debian.org> On ia64, 32-bit rotates are implemented by copying the lower 32 bits of a register into the upper half, then performing a right shift. However, depending on the bit pattern in question, this can leave the upper 32 bits as non-zero, despite being only a 32-bit unsigned result. Therefore add an extra zero_extract to mask these out. gcc/ PR rtl-optimization/83565 * gcc/config/ia64/ia64.md ("*rotrsi3_internal"): Mask out higher 32 bits from the shift result. ("*rotlsi3_internal"): Likewise --- [Resent because git send-email messed about with the headers, adding a second From: with a different email address, presumably since I ran git send-email from a directory with .git/config containing a user.email setting...] gcc/config/ia64/ia64.md | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) -- 1.7.10.4 diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index b7cd52b..8198b54 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -3329,7 +3329,10 @@ (ior:DI (zero_extend:DI (match_dup 1)) (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) (set (match_dup 3) - (lshiftrt:DI (match_dup 3) (match_dup 2)))] + (lshiftrt:DI (match_dup 3) (match_dup 2))) + (set (match_dup 3) + (zero_extract:DI (match_dup 3) + (const_int 32) (const_int 0)))] "operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));") (define_expand "rotlsi3" @@ -3358,7 +3361,10 @@ (ior:DI (zero_extend:DI (match_dup 1)) (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32)))) (set (match_dup 3) - (lshiftrt:DI (match_dup 3) (match_dup 2)))] + (lshiftrt:DI (match_dup 3) (match_dup 2))) + (set (match_dup 3) + (zero_extract:DI (match_dup 3) + (const_int 32) (const_int 0)))] { operands[3] = gen_rtx_REG (DImode, REGNO (operands[0])); operands[2] = GEN_INT (32 - INTVAL (operands[2]));