From patchwork Fri Sep 11 10:17:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 1362376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=8.43.85.97; helo=sourceware.org; envelope-from=gcc-patches-bounces@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BnsCG3B47z9sTN for ; Fri, 11 Sep 2020 20:18:01 +1000 (AEST) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2C4F4398603D; Fri, 11 Sep 2020 10:17:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from esa3.mentor.iphmx.com (esa3.mentor.iphmx.com [68.232.137.180]) by sourceware.org (Postfix) with ESMTPS id 9F377384C005 for ; Fri, 11 Sep 2020 10:17:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 9F377384C005 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=Andrew_Stubbs@mentor.com IronPort-SDR: b0zQijzw1+qy8JJYN0EqtOqQwGbFX7ppDawdFkUWQUXbDtNFw6YI0Qr95lHcazWukGLRQV+U1E mZeL+uy2QL4VRGTb4OkMvP+OT828l8AI5Id8QA+lkaPYQJdLX/fvOMzK+ciNijkkKK88Mmdpyl qsTgYkQhIsin9fSyjsFjjhSnMExz5ndfAZeZVtL7FFB2nSSqVrETxej2wfqOpale3QNzGGs2Zj ETkA4bsmUWFYspzbbVW4SCffM4K7m1iQTjNhKm2NI19ifg+EZ7SiiJATh4+8PI5w50JMQwvNsN 5XY= X-IronPort-AV: E=Sophos;i="5.76,414,1592899200"; d="scan'208";a="52786774" Received: from orw-gwy-01-in.mentorg.com ([192.94.38.165]) by esa3.mentor.iphmx.com with ESMTP; 11 Sep 2020 02:17:55 -0800 IronPort-SDR: LjxFVkP0jZVg+XbWdW4oJ2lvVP0ibYtAez7HtWcOrpz/ZzAY41dr+hL1/IGs0H1YjKetvNsM3c apM8gaWjLJKJ4ThskyfZe4lpLf32TktlJtoSGiMSUp0JxzM8nUSBOWBp76FEBqleteHYT92D6U 7X/eYz+zDwHnRkGuJwfN9WQWxXMEGDq4T5jBOC89bsbKOWsfp80i3vSQpaJ5V3p9EwZNU2sH1K IhV+wTCWEt2FZvpRJM2vA2xnXu21HWxpzOl2ps29QuT7nmRjIig49s1qoEBSvr7+fsiIO8DRy7 T9Y= From: Andrew Stubbs Subject: [committed] amdgcn: align TImode registers To: "gcc-patches@gcc.gnu.org" Message-ID: Date: Fri, 11 Sep 2020 11:17:50 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 Content-Language: en-GB X-Originating-IP: [137.202.0.90] X-ClientProxiedBy: SVR-IES-MBX-03.mgc.mentorg.com (139.181.222.3) To svr-ies-mbx-01.mgc.mentorg.com (139.181.222.1) X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces@gcc.gnu.org Sender: "Gcc-patches" This patch fixes an execution failure in which the compiler would corrupt TImode values due to missed early clobber problems with partially overlapping register allocations. In fact, adding early clobber constraints does not fix the issue because IRA doesn't check that for move instructions properly in all circumstances anyway (the constraint causes an ICE in postreload). This patch fixes the problem by ensuring that TImode values are always aligned to 4-register boundaries, meaning that inputs and outputs will either overlap completely, or not at all, neither of which have early-clobber issues. This is an artificial restriction the hardware not present in hardware , but it is the same solution we use for DImode values where we had a lot of the same problems. With the patch I see the following new test passes: PASS: gfortran.dg/PR95331.f90 -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test PASS: gfortran.dg/PR95331.f90 -O3 -g execution test PASS: gfortran.dg/gamma_5.f90 -O0 execution test PASS: gfortran.dg/gamma_5.f90 -O1 execution test PASS: gfortran.dg/gamma_5.f90 -O2 execution test PASS: gfortran.dg/gamma_5.f90 -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test PASS: gfortran.dg/gamma_5.f90 -O3 -g execution test PASS: gfortran.dg/gamma_5.f90 -Os execution test PASS: gfortran.dg/intrinsic_pack_1.f90 -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test PASS: gfortran.dg/intrinsic_pack_1.f90 -O3 -g execution test PASS: gfortran.dg/optional_absent_5.f90 -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions execution test PASS: gfortran.dg/optional_absent_5.f90 -O3 -g execution test Andrew amdgcn: align TImode registers This prevents execution failures caused by partially overlapping input and output registers. This is the same solution already used for DImode. gcc/ChangeLog: * config/gcn/gcn.c (gcn_hard_regno_mode_ok): Align TImode registers. * config/gcn/gcn.md: Assert that TImode registers do not early clobber. diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c index 8b3c4544dd5..84d1fd9a354 100644 --- a/gcc/config/gcn/gcn.c +++ b/gcc/config/gcn/gcn.c @@ -475,7 +475,8 @@ gcn_hard_regno_mode_ok (unsigned int regno, machine_mode mode) return (vgpr_1reg_mode_p (mode) || (!((regno - FIRST_VGPR_REG) & 1) && vgpr_2reg_mode_p (mode)) /* TImode is used by DImode compare_and_swap. */ - || mode == TImode); + || (mode == TImode + && !((regno - FIRST_VGPR_REG) & 3))); return false; } diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md index aeb25fbb931..0e73fea93cf 100644 --- a/gcc/config/gcn/gcn.md +++ b/gcc/config/gcn/gcn.md @@ -677,6 +677,8 @@ (define_insn_and_split "*movti_insn" (set (match_dup 4) (match_dup 5)) (set (match_dup 6) (match_dup 7))] { + gcc_assert (rtx_equal_p (operands[0], operands[1]) + || !reg_overlap_mentioned_p (operands[0], operands[1])); operands[6] = gcn_operand_part (TImode, operands[0], 3); operands[7] = gcn_operand_part (TImode, operands[1], 3); operands[4] = gcn_operand_part (TImode, operands[0], 2);