From patchwork Wed Aug 26 18:37:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352080 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF4Q3y4Hz9sTg for ; Thu, 27 Aug 2020 04:38:46 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=AEGv9T30; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BcF4Q1hkxzDqSg for ; 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Wed, 26 Aug 2020 18:37:56 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07QIbqTq31916346 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 26 Aug 2020 18:37:52 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8CB496E053 for ; Wed, 26 Aug 2020 18:37:55 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3A92B6E052 for ; Wed, 26 Aug 2020 18:37:55 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:37:55 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:39 -0400 Message-Id: <20200826183749.143980-2-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxscore=0 clxscore=1015 bulkscore=0 impostorscore=0 suspectscore=3 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 01/11] Add functions to initialize and start an ultravisor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Power 9 introduces a mode called ultravisor mode. init_uv looks for uv-src-address in the device tree and copies the image to the address specified in "reg". start_ultravisor is called in load_and_boot_kernel with the pointer to the system fdt. Every thread is sent to the ultravisor image and returns with UV mode off. A minimal ultravisor could disable UV and PEF, instructions in commit "skiboot.tcl: ultravisor support." [ maddy: Initial implementation] [Signed-off-by: Madhavan Srinivasan [ santosh: Initial implementation] Signed-off-by: Santosh Sivaraj Signed-off-by: Ryan Grimm --- asm/misc.S | 21 ++++++++++ core/init.c | 7 +++- hw/Makefile.inc | 2 +- hw/ultravisor.c | 93 ++++++++++++++++++++++++++++++++++++++++++++ include/processor.h | 7 ++++ include/ultravisor.h | 35 +++++++++++++++++ 6 files changed, 162 insertions(+), 3 deletions(-) create mode 100644 hw/ultravisor.c create mode 100644 include/ultravisor.h diff --git a/asm/misc.S b/asm/misc.S index 03344897..30f67872 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -306,3 +306,24 @@ exit_uv_mode: mtspr SPR_USRR0,%r4 PPC_INST_URFID +/* + * start_uv register usage: + * + * r3 : UV entry addr + * r4 : system fdt + */ +.global enter_uv +enter_uv: + mflr %r0 + std %r0,16(%r1) + sync + /* flush caches, etc */ + icbi 0,%r3 + sync + isync + mtctr %r3 + mr %r3,%r4 + bctrl /* branch to UV here */ + ld %r0,16(%r1) + mtlr %r0 + blr diff --git a/core/init.c b/core/init.c index d82eebee..91754962 100644 --- a/core/init.c +++ b/core/init.c @@ -47,6 +47,7 @@ #include #include #include +#include enum proc_gen proc_gen; unsigned int pcie_max_link_speed; @@ -603,6 +604,8 @@ void __noreturn load_and_boot_kernel(bool is_reboot) abort(); } + start_ultravisor(fdt); + op_display(OP_LOG, OP_MOD_INIT, 0x000C); mem_dump_free(); @@ -1370,8 +1373,8 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Add the list of interrupts going to OPAL */ add_opal_interrupts(); - /* Disable protected execution facility in BML */ - cpu_disable_pef(); + /* Initialize the ultravisor */ + init_uv(); /* Now release parts of memory nodes we haven't used ourselves... */ mem_region_release_unused(); diff --git a/hw/Makefile.inc b/hw/Makefile.inc index a7f450cf..f5408735 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -9,7 +9,7 @@ HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o -HW_OBJS += ocmb.o +HW_OBJS += ocmb.o ultravisor.o HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc diff --git a/hw/ultravisor.c b/hw/ultravisor.c new file mode 100644 index 00000000..1be47ec5 --- /dev/null +++ b/hw/ultravisor.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2018-2019 IBM Corp. */ + +#include +#include +#include +#include +#include +#include +#include + +static struct dt_node *uv_fw_node; +static uint64_t uv_base_addr; +bool uv_present; + +static void cpu_start_ultravisor(void *fdt) +{ + uint64_t uv_entry = 0; + + if (dt_find_property(uv_fw_node, "uv-entry")) + uv_entry = dt_prop_get_u64(uv_fw_node, "uv-entry"); + + prlog(PR_DEBUG, "UV: Starting on CPU 0x%04x\n", this_cpu()->pir); + enter_uv(uv_base_addr + uv_entry, fdt); +} + +int start_ultravisor(void *fdt) +{ + struct cpu_thread *cpu; + struct cpu_job **jobs; + int i = 0; + + if (!uv_base_addr || !fdt) { + prlog(PR_DEBUG, "UV: uv_base_addr 0x%llx or fdt %p not set\n", + uv_base_addr, fdt); + return OPAL_INTERNAL_ERROR; + } + + jobs = zalloc(sizeof(struct cpu_job *) * cpu_max_pir); + + prlog(PR_DEBUG, "UV: Starting @0x%016llx fdt %p\n", + uv_base_addr, fdt); + + for_each_available_cpu(cpu) { + if (cpu == this_cpu()) + continue; + jobs[i++] = cpu_queue_job(cpu, "start_ultravisor", + cpu_start_ultravisor, fdt); + } + + cpu_start_ultravisor(fdt); + + uv_present = true; + + while (i > 0) + cpu_wait_job(jobs[--i], true); + + free(jobs); + + return OPAL_SUCCESS; +} + +void init_uv() +{ + uint64_t uv_dt_src, uv_fw_sz; + struct dt_node *reserved_mem; + + if (!is_msr_bit_set(MSR_S)) { + prlog(PR_DEBUG, "UV: S bit not set\n"); + return; + } + + uv_fw_node = dt_find_compatible_node(dt_root, NULL, "ibm,uv-firmware"); + if (!uv_fw_node) { + prlog(PR_DEBUG, "UV: No ibm,uv-firmware node found, disabling pef\n"); + cpu_disable_pef(); + return; + } + + reserved_mem = dt_find_by_path(dt_root, "/reserved-memory/ibm,uv-firmware"); + if (!reserved_mem) { + prerror("UV: No reserved memory for ibm,uv-firmware found\n"); + return; + } + + uv_dt_src = dt_get_address(reserved_mem, 0, &uv_fw_sz); + uv_base_addr = dt_get_address(uv_fw_node, 0, NULL); + + prlog(PR_INFO, "UV: Copying 0x%llx bytes to protected memory 0x%llx from 0x%llx\n", + uv_fw_sz, uv_base_addr, uv_dt_src); + + memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); +} diff --git a/include/processor.h b/include/processor.h index ddec6c04..cb81aabb 100644 --- a/include/processor.h +++ b/include/processor.h @@ -397,6 +397,13 @@ static inline void st_le32(uint32_t *addr, uint32_t val) asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr)); } +static inline bool is_msr_bit_set(uint64_t bit) +{ + if (mfmsr() & bit) + return true; + return false; +} + #endif /* __TEST__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/ultravisor.h b/include/ultravisor.h new file mode 100644 index 00000000..05edb53e --- /dev/null +++ b/include/ultravisor.h @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2018-2019 IBM Corp. */ + +#ifndef __ULTRAVISOR_H +#define __ULTRAVISOR_H + +#include +#include +#include + +/* + * enter_uv: Each thread enters ultravisor and exits with S=0 + * @entry: Offset into ultravisor image for threads to jump to + * @fdt: Flattened system device tree + * + * All threads sent here by skiboot from C code + * + * return value: 0 on success, non-zero on failure + */ +extern int enter_uv(uint64_t entry, void *fdt); + +/* + * start_ultravisor: Start the ultravisor on all threads + * @fdt: Flattened system device tree + * + * return value: 0 on success, non-zero on failure + */ +int start_ultravisor(void *fdt); + +/* Set when ultravisor started, so code knows to make a ucall */ +extern bool uv_present; + +void init_uv(void); + +#endif /* __ULTRAVISOR_H */ From patchwork Wed Aug 26 18:37:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352082 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF5Q0lv7z9sTS for ; Thu, 27 Aug 2020 04:39:38 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=KIq8pMs2; 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Wed, 26 Aug 2020 18:38:01 GMT Received: from b01cxnp22035.gho.pok.ibm.com (b01cxnp22035.gho.pok.ibm.com [9.57.198.25]) by ppma04wdc.us.ibm.com with ESMTP id 332ujev10s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 26 Aug 2020 18:38:01 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22035.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07QIc1aM52035902 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 26 Aug 2020 18:38:01 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2F170B2064 for ; Wed, 26 Aug 2020 18:38:01 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 01ED5B205F for ; Wed, 26 Aug 2020 18:38:00 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:00 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:40 -0400 Message-Id: <20200826183749.143980-3-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 suspectscore=13 mlxlogscore=999 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 02/11] skiboot.tcl: ultravisor support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This tcl code turns on the S bit in MSR and sets up SMFCTRL and SIM_CTRL if MAMBO_ENABLE_SMF is set. Skiboot will run its exit_uv_mode function because there's no ibm,utlravisor device tree node. If ULTRA_IMAGE is set, it loads the image at 0xc0000000 and sets up the ibm,ultravisor device tree node. This can be tested using this (hacked) skiboot as the ultravisor image with: export SKIBOOT=skiboot.lid export ULTRA_IMAGE=$SKIBOOT export ULTRA_ENTRY=$(grep exit_uv_mode skiboot.map|cut -f1 -d " ") export MAMBO_ENABLE_SMF=1 Although you need to hack up exit_uv_mode to ignore the fdt pointer and treat as primary thread. Signed-off-by: Ryan Grimm --- external/mambo/skiboot.tcl | 74 +++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/external/mambo/skiboot.tcl b/external/mambo/skiboot.tcl index 6003fcbe..c823985a 100644 --- a/external/mambo/skiboot.tcl +++ b/external/mambo/skiboot.tcl @@ -56,6 +56,16 @@ if { ![info exists env(SKIBOOT_ZIMAGE)] } { } mconfig payload PAYLOAD $env(SKIBOOT_ZIMAGE) +mconfig enable_smf MAMBO_ENABLE_SMF none + +mconfig ultra_image ULTRA_IMAGE none + +mconfig ultra_src_addr ULTRA_SRC_ADDR 0xc0000000; + +mconfig spr_urmor ULTRA_URMOR 0xe0000000 + +mconfig ultra_entry ULTRA_ENTRY 0; + mconfig linux_cmdline LINUX_CMDLINE "" # Paylod: Memory location for a Linux style ramdisk/initrd @@ -140,6 +150,11 @@ if { $default_config == "P9" } { if { $mconf(numa) } { myconf config memory_region_id_shift 45 } + + if { $mconf(enable_smf) != "none" } { + myconf config processor/initial/SMFCTRL 0x8000000000000002 + myconf config processor/initial/SIM_CTRL1 0x4228100404004000 + } } if { $mconf(numa) } { @@ -507,12 +522,16 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } { mysim mcm 0 cpu $c thread $t set spr pir $pir lappend irqreg $pir incr pir + if { $mconf(enable_smf) != "none" } { + mysim mcm 0 cpu $c thread $t set spr msr 0x9000000000400000 + } } mysim of addprop $cpu_node array "ibm,ppc-interrupt-server#s" irqreg } #Add In-Memory Collection Counter nodes -if { $default_config == "P9" } { +#if { $default_config == "P9" && $mconf(enable_ultra) == "none" } { +if { $default_config == "P9" && $mconf(ultra_image) == "none" } { #Add the base node "imc-counters" set imc_c [mysim of addchild $root_node "imc-counters" ""] mysim of addprop $imc_c string "compatible" "ibm,opal-in-memory-counters" @@ -669,6 +688,59 @@ if { [info exists env(SKIBOOT_ENABLE_MAMBO_STB)] } { } } +if {$mconf(ultra_image) != "none"} { + set uv_node [ mysim of addchild $root_node "ibm,ultravisor" "" ] + mysim of addprop $uv_node string "compatible" "ibm,ultravisor" + mysim of addprop $uv_node int "#address-cells" 2 + mysim of addprop $uv_node int "#size-cells" 2 + + set uv_fw_node [ mysim of addchild $uv_node "firmware" "" ] + mysim of addprop $uv_fw_node string "compatible" "ibm,uv-firmware" + set uv_entry $mconf(ultra_entry) + set uv_entry_prop [ list [expr $uv_entry >> 32] [expr $uv_entry & 0xffffffff] ] + mysim of addprop $uv_fw_node array "uv-entry" uv_entry_prop + + set range [list] + lappend range $mconf(spr_urmor) + lappend range [expr [mysim display memory_size] - $mconf(spr_urmor)] + mysim of addprop $uv_fw_node array64 "secure-memory-ranges" range + + + set start $mconf(spr_urmor) + + if {[file exists $mconf(ultra_image)]} { + set ultra_file $mconf(ultra_image) + } else { + puts "ERROR: Could not find ultra: $mconf(ultra_image)" + exit + } + + set ultra_size [file size $ultra_file] + set reg [list [expr $start >> 32] [expr $start & 0xffffffff] [expr $ultra_size >> 32] [expr $ultra_size & 0xffffffff]] + mysim of addprop $uv_fw_node array "reg" reg + + #secure-memory node + set start_hex [format %x $start] + set size [expr [mysim display memory_size] - $mconf(spr_urmor)] + set secure_mem_node [mysim of addchild $root_node "secure-memory@$start_hex" ""] + mysim of addprop $secure_mem_node string "compatible" "ibm,secure-memory" + set reg [list [expr $start >> 32] [expr $start & 0xffffffff] [expr $size >> 32] [expr $size & 0xffffffff]] + mysim of addprop $secure_mem_node array "reg" reg + mysim of addprop $secure_mem_node string "device_type" "secure-memory" + set associativity [list 4 0 0 0 0] + mysim of addprop $secure_mem_node "array" "ibm,associativity" associativity + set chip_id [format %x 0] + mysim of addprop $secure_mem_node array "ibm,chip-id" chip_id + + set src_addr $mconf(ultra_src_addr) + mysim memory fread $src_addr $ultra_size $ultra_file + + set uv_firmware [mysim of addchild $reserved_memory "ibm,uv-firmware" ""] + set reg [list $src_addr $ultra_size] + mysim of addprop $uv_firmware array64 "reg" reg + mysim of addprop $uv_firmware empty "name" "ibm,uv-firmware" +} + # Kernel command line args, appended to any from the device tree # e.g.: of::set_bootargs "xmon" # From patchwork Wed Aug 26 18:37:41 2020 Content-Type: text/plain; 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Wed, 26 Aug 2020 18:38:07 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07QIc6Ih49348956 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 26 Aug 2020 18:38:06 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9D4EC28058 for ; Wed, 26 Aug 2020 18:38:06 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7BE3C2805A for ; Wed, 26 Aug 2020 18:38:06 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:06 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:41 -0400 Message-Id: <20200826183749.143980-4-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 mlxscore=0 adultscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 bulkscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 03/11] Add memcons support for ultravisor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan The ultravisor console buffer is provided at offset 0x01100000 from the skiboot base. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj --- hw/ultravisor.c | 13 +++++++++++++ include/console.h | 3 +++ include/debug_descriptor.h | 1 + include/mem-map.h | 16 ++++++++++------ 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 1be47ec5..467f0ca6 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -8,11 +8,21 @@ #include #include #include +#include +#include static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; bool uv_present; +struct memcons uv_memcons __section(".data.memcons") = { + .magic = MEMCONS_MAGIC, + .obuf_phys = INMEM_UV_CON_START, + .ibuf_phys = INMEM_UV_CON_START + INMEM_UV_CON_OUT_LEN, + .obuf_size = INMEM_UV_CON_OUT_LEN, + .ibuf_size = INMEM_UV_CON_IN_LEN, +}; + static void cpu_start_ultravisor(void *fdt) { uint64_t uv_entry = 0; @@ -90,4 +100,7 @@ void init_uv() uv_fw_sz, uv_base_addr, uv_dt_src); memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); + + dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons); + debug_descriptor.uv_memcons_phys = (u64)&uv_memcons; } diff --git a/include/console.h b/include/console.h index 02fc7a4b..47ffe7fd 100644 --- a/include/console.h +++ b/include/console.h @@ -28,9 +28,12 @@ struct memcons { }; extern struct memcons memcons; +extern struct memcons uv_memcons; #define INMEM_CON_IN_LEN 16 #define INMEM_CON_OUT_LEN (INMEM_CON_LEN - INMEM_CON_IN_LEN) +#define INMEM_UV_CON_IN_LEN 16 +#define INMEM_UV_CON_OUT_LEN (INMEM_UV_CON_LEN - INMEM_UV_CON_IN_LEN) /* Console driver */ struct con_ops { diff --git a/include/debug_descriptor.h b/include/debug_descriptor.h index 3ac487b0..dfcf2686 100644 --- a/include/debug_descriptor.h +++ b/include/debug_descriptor.h @@ -20,6 +20,7 @@ struct debug_descriptor { /* Memory console */ __be64 memcons_phys; + __be64 uv_memcons_phys; __be32 memcons_tce; __be32 memcons_obuf_tce; __be32 memcons_ibuf_tce; diff --git a/include/mem-map.h b/include/mem-map.h index 15ec09ea..2384684b 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -91,16 +91,20 @@ #define INMEM_CON_START (SKIBOOT_BASE + 0x01000000) #define INMEM_CON_LEN 0x100000 -/* This is the location of HBRT console buffer at base + 17M */ -#define HBRT_CON_START (SKIBOOT_BASE + 0x01100000) +/* This is the location of our ultravisor console buffer at base + 17M */ +#define INMEM_UV_CON_START (SKIBOOT_BASE + 0x01100000) +#define INMEM_UV_CON_LEN 0x100000 + +/* This is the location of HBRT console buffer at base + 18M */ +#define HBRT_CON_START (SKIBOOT_BASE + 0x01200000) #define HBRT_CON_LEN 0x100000 -/* Tell FSP to put the init data at base + 20M, allocate 8M */ -#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01200000) +/* Tell FSP to put the init data at base + 19M, allocate 8M */ +#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01300000) #define SPIRA_HEAP_SIZE 0x00800000 /* This is our PSI TCE table. It's 256K entries on P8 */ -#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000) +#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01c00000) #define PSI_TCE_TABLE_SIZE 0x00200000UL /* This is our dump result table after MPIPL. Hostboot will write to this @@ -119,7 +123,7 @@ * * (Ensure this has at least a 64k alignment) */ -#define SKIBOOT_SIZE 0x01c10000 +#define SKIBOOT_SIZE 0x01e00000 /* We start laying out the CPU stacks from here, indexed by PIR * each stack is STACK_SIZE in size (naturally aligned power of From patchwork Wed Aug 26 18:37:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352084 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF6P0KN3z9sRK for ; Thu, 27 Aug 2020 04:40:29 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; 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Wed, 26 Aug 2020 18:38:12 GMT Received: from b01cxnp23033.gho.pok.ibm.com (b01cxnp23033.gho.pok.ibm.com [9.57.198.28]) by ppma04wdc.us.ibm.com with ESMTP id 332ujev11t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 26 Aug 2020 18:38:12 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07QIcCVY32965088 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 26 Aug 2020 18:38:12 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 37B47B2064 for ; Wed, 26 Aug 2020 18:38:12 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0A081B2065 for ; Wed, 26 Aug 2020 18:38:12 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:11 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:42 -0400 Message-Id: <20200826183749.143980-5-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=990 suspectscore=13 impostorscore=0 malwarescore=0 adultscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 mlxscore=0 spamscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 04/11] Add ultra call support for skiboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan A new type of system call called the ultra call is used to get the services of the ultravisor. This ultracall support is needed in skiboot to access the xscoms which are in the secure memory area. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj [ andmike: ABI change to switch from r0 to r3 ] Signed-off-by: Michael Anderson --- asm/misc.S | 29 +++++++++++++++++++++++++++++ include/ultravisor.h | 11 +++++++++++ 2 files changed, 40 insertions(+) diff --git a/asm/misc.S b/asm/misc.S index 30f67872..5119304a 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -275,6 +275,8 @@ enter_p9_pm_state: * PEF and bring it out of UV mode. All threads will then be running in HV * mode and the only way to re-enable UV mode is with a reboot. * + * Power9 hardware requires [h]srr1 to be set explicitly. + * * r3 = 1 if primary thread * 0 if secondary thread */ @@ -327,3 +329,30 @@ enter_uv: ld %r0,16(%r1) mtlr %r0 blr + +.global ucall +ucall: + mflr %r0 + stdu %r1,-STACK_FRAMESIZE(%r1) + std %r0,STACK_LR(%r1) + mfcr %r0 + stw %r0,STACK_CR(%r1) + std %r4,STACK_GPR4(%r1) /* Save ret buffer */ + mr %r4,%r5 + mr %r5,%r6 + mr %r6,%r7 + mr %r7,%r8 + mr %r8,%r9 + mr %r9,%r10 + sc 2 /* invoke the ultravisor */ + ld %r12,STACK_GPR4(%r1) + std %r4, 0(%r12) + std %r5, 8(%r12) + std %r6, 16(%r12) + std %r7, 24(%r12) + lwz %r0,STACK_CR(%r1) + mtcrf 0xff,%r0 + ld %r0,STACK_LR(%r1) + mtlr %r0 + addi %r1,%r1,STACK_FRAMESIZE + blr /* return r3 = status */ diff --git a/include/ultravisor.h b/include/ultravisor.h index 05edb53e..623b81d4 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -32,4 +32,15 @@ extern bool uv_present; void init_uv(void); +/* + * ucall: Make an ultracall + * @opcode: The ultracall to make + * @retbuf: Buffer to store up to 4 return arguments + * + * This call supports up to 6 arguments and 4 return arguments. Use + * UCALL_BUFSIZE to size the return argument buffer. + */ +#define UCALL_BUFSIZE 4 +extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); + #endif /* __ULTRAVISOR_H */ From patchwork Wed Aug 26 18:37:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352085 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF6m48yKz9sTK for ; Thu, 27 Aug 2020 04:40:48 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; 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Wed, 26 Aug 2020 18:38:17 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:43 -0400 Message-Id: <20200826183749.143980-6-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=806 clxscore=1015 mlxscore=0 malwarescore=0 suspectscore=1 adultscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 05/11] xscoms: read/write xscoms using ucall X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan xscom registers are in the secure memory area when secure mode is enabled. These registers cannot be accessed directly and need to use ultravisor services using ultracall. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj [ linuxram: Set uv_present just after starting UV ] Signed-off-by: Ram Pai [ grimm: Don't check MSR in xscom read/write ] Signed-off-by: Ryan Grimm --- include/ultravisor.h | 21 +++++++++++++++++++++ include/xscom.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/include/ultravisor.h b/include/ultravisor.h index 623b81d4..84217d66 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * enter_uv: Each thread enters ultravisor and exits with S=0 @@ -43,4 +44,24 @@ void init_uv(void); #define UCALL_BUFSIZE 4 extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); +#define UV_READ_SCOM 0xF114 +#define UV_WRITE_SCOM 0xF118 + +static inline int uv_xscom_read(u64 partid, u64 pcb_addr, u64 *val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + long rc; + + rc = ucall(UV_READ_SCOM, retbuf, partid, pcb_addr); + *val = retbuf[0]; + return rc; +} + +static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + + return ucall(UV_WRITE_SCOM, retbuf, partid, pcb_addr, val); +} + #endif /* __ULTRAVISOR_H */ diff --git a/include/xscom.h b/include/xscom.h index bd8bb89a..67a845fd 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * SCOM "partID" definitions: @@ -174,9 +175,13 @@ extern void _xscom_unlock(void); /* Targeted SCOM access */ static inline int xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val) { + if (uv_present) + return uv_xscom_read(partid, pcb_addr, val); return _xscom_read(partid, pcb_addr, val, true); } static inline int xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) { + if (uv_present) + return uv_xscom_write(partid, pcb_addr, val); return _xscom_write(partid, pcb_addr, val, true); } extern int xscom_write_mask(uint32_t partid, uint64_t pcb_addr, uint64_t val, uint64_t mask); From patchwork Wed Aug 26 18:37:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352086 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF7D3Nffz9sRK for ; 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Wed, 26 Aug 2020 18:38:23 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:23 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:44 -0400 Message-Id: <20200826183749.143980-7-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=3 bulkscore=0 spamscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 mlxlogscore=912 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260137 Subject: [Skiboot] [PATCH v8 06/11] core/mem_region.c: Implement local free X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Ryan Grimm --- core/mem_region.c | 32 ++++++++++++++++++++++++++++++++ include/mem_region-malloc.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/core/mem_region.c b/core/mem_region.c index 36de2d09..aefea8d2 100644 --- a/core/mem_region.c +++ b/core/mem_region.c @@ -920,6 +920,38 @@ restart: return p; } +void __local_free(void *p, const char *location) +{ + struct mem_region *region; + struct alloc_hdr *hdr; + + if (!p) + return; + + lock(&mem_region_lock); + + list_for_each(®ions, region, list) { + /* local_alloc doesn't use heap */ + if (region == &skiboot_heap) + continue; + + if (p >= region_start(region) && + (p < (region_start(region) + region->len))) { + hdr = p - sizeof(*hdr); + + if (hdr->free) + bad_header(region, hdr, "re-freed", location); + + lock(®ion->free_list_lock); + make_free(region, (struct free_hdr *)hdr, location, false); + unlock(®ion->free_list_lock); + } + + } + + unlock(&mem_region_lock); +} + struct mem_region *find_mem_region(const char *name) { struct mem_region *region; diff --git a/include/mem_region-malloc.h b/include/mem_region-malloc.h index 271311b2..cf64eb25 100644 --- a/include/mem_region-malloc.h +++ b/include/mem_region-malloc.h @@ -28,4 +28,7 @@ void *__local_alloc(unsigned int chip, size_t size, size_t align, #define local_alloc(chip_id, size, align) \ __local_alloc((chip_id), (size), (align), __location__) +void __local_free(void *ptr, const char *location); +#define local_free(ptr) __local_free(ptr, __location__); + #endif /* __MEM_REGION_MALLOC_H */ From patchwork Wed Aug 26 18:37:45 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352087 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF7X51L3z9sRK for ; Thu, 27 Aug 2020 04:41:28 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256 header.s=pp1 header.b=S+iYEW6X; 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Wed, 26 Aug 2020 18:38:30 GMT Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by ppma03dal.us.ibm.com with ESMTP id 332uttvww3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 26 Aug 2020 18:38:30 +0000 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07QIcT9q51577136 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 26 Aug 2020 18:38:29 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 810D1112061 for ; Wed, 26 Aug 2020 18:38:29 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 53F33112063 for ; Wed, 26 Aug 2020 18:38:29 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:29 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:45 -0400 Message-Id: <20200826183749.143980-8-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=3 bulkscore=0 spamscore=0 priorityscore=1501 mlxscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 mlxlogscore=999 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260137 Subject: [Skiboot] [PATCH v8 07/11] Load the ultravisor from flash and decompress X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The ultravisor, labeled UVISOR is preloaded from the PNOR in main_cpu_entry after the kernel is preloaded. This also works on FSP-based systems with an ultra.lid on the FSP. Skiboot decompresses it later in init_uv. Signed-off-by: Santosh Sivaraj Signed-off-by: Ryan Grimm --- core/flash.c | 1 + core/init.c | 1 + hw/fsp/fsp.c | 2 + hw/ultravisor.c | 95 +++++++++++++++++++++++++++++++++++++++----- include/platform.h | 1 + include/ultravisor.h | 3 ++ 6 files changed, 93 insertions(+), 10 deletions(-) diff --git a/core/flash.c b/core/flash.c index de748641..bc44a4e5 100644 --- a/core/flash.c +++ b/core/flash.c @@ -45,6 +45,7 @@ static struct { { RESOURCE_ID_INITRAMFS,RESOURCE_SUBID_NONE, "ROOTFS" }, { RESOURCE_ID_CAPP, RESOURCE_SUBID_SUPPORTED, "CAPP" }, { RESOURCE_ID_IMA_CATALOG, RESOURCE_SUBID_SUPPORTED, "IMA_CATALOG" }, + { RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, "UVISOR" }, { RESOURCE_ID_VERSION, RESOURCE_SUBID_NONE, "VERSION" }, { RESOURCE_ID_KERNEL_FW, RESOURCE_SUBID_NONE, "BOOTKERNFW" }, }; diff --git a/core/init.c b/core/init.c index 91754962..77dfb36f 100644 --- a/core/init.c +++ b/core/init.c @@ -1319,6 +1319,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) preload_capp_ucode(); start_preload_kernel(); + uv_preload_image(); /* Catalog decompression routine */ imc_decompress_catalog(); diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 70452cf9..7b564f93 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -114,6 +114,7 @@ static u64 fsp_hir_timeout; #define KERNEL_LID_PHYP 0x80a00701 #define KERNEL_LID_OPAL 0x80f00101 #define INITRAMFS_LID_OPAL 0x80f00102 +#define ULTRA_LID_OPAL 0x80f00105 /* * We keep track on last logged values for some things to print only on @@ -2381,6 +2382,7 @@ static struct { } fsp_lid_map[] = { { RESOURCE_ID_KERNEL, RESOURCE_SUBID_NONE, KERNEL_LID_OPAL }, { RESOURCE_ID_INITRAMFS,RESOURCE_SUBID_NONE, INITRAMFS_LID_OPAL }, + { RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, ULTRA_LID_OPAL }, { RESOURCE_ID_IMA_CATALOG,IMA_CATALOG_NIMBUS, 0x80f00103 }, { RESOURCE_ID_CAPP, CAPP_IDX_MURANO_DD20, 0x80a02002 }, { RESOURCE_ID_CAPP, CAPP_IDX_MURANO_DD21, 0x80a02001 }, diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 467f0ca6..34c16404 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -10,11 +10,16 @@ #include #include #include +#include +#include static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; bool uv_present; +static char *uv_image = NULL; +static size_t uv_image_size; + struct memcons uv_memcons __section(".data.memcons") = { .magic = MEMCONS_MAGIC, .obuf_phys = INMEM_UV_CON_START, @@ -70,10 +75,44 @@ int start_ultravisor(void *fdt) return OPAL_SUCCESS; } +static int uv_decompress_image(void) +{ + struct xz_decompress uv_xz; + uint64_t uv_fw_size; + + if (!uv_image) { + prerror("UV: Preload hasn't started yet! Aborting.\n"); + return OPAL_INTERNAL_ERROR; + } + + if (wait_for_resource_loaded(RESOURCE_ID_UV_IMAGE, + RESOURCE_SUBID_NONE) != OPAL_SUCCESS) { + prerror("UV: Ultravisor image load failed\n"); + return OPAL_INTERNAL_ERROR; + } + + uv_xz.dst = (void *)dt_get_address(uv_fw_node, 0, &uv_fw_size); + uv_xz.dst_size = uv_fw_size; + uv_xz.src_size = uv_image_size; + uv_xz.src = uv_image; + + if (stb_is_container((void*)uv_xz.src, uv_xz.src_size)) + uv_xz.src = uv_xz.src + SECURE_BOOT_HEADERS_SIZE; + + xz_start_decompress(&uv_xz); + if ((uv_xz.status != OPAL_PARTIAL) && (uv_xz.status != OPAL_SUCCESS)) { + prerror("UV: XZ decompression failed status 0x%x\n", uv_xz.status); + return OPAL_INTERNAL_ERROR; + } + + return OPAL_SUCCESS; +} + void init_uv() { uint64_t uv_dt_src, uv_fw_sz; struct dt_node *reserved_mem; + int ret; if (!is_msr_bit_set(MSR_S)) { prlog(PR_DEBUG, "UV: S bit not set\n"); @@ -84,23 +123,59 @@ void init_uv() if (!uv_fw_node) { prlog(PR_DEBUG, "UV: No ibm,uv-firmware node found, disabling pef\n"); cpu_disable_pef(); - return; + goto err; } - reserved_mem = dt_find_by_path(dt_root, "/reserved-memory/ibm,uv-firmware"); - if (!reserved_mem) { - prerror("UV: No reserved memory for ibm,uv-firmware found\n"); - return; - } + /* If decompress fails, look for reserved memory by Mambo tcl or cronus BML */ + ret = uv_decompress_image(); + if (ret) { + reserved_mem = dt_find_by_path(dt_root, "/reserved-memory/ibm,uv-firmware"); + if (!reserved_mem) { + prerror("UV: No reserved memory for ibm,uv-firmware found\n"); + return; + } - uv_dt_src = dt_get_address(reserved_mem, 0, &uv_fw_sz); - uv_base_addr = dt_get_address(uv_fw_node, 0, NULL); + uv_dt_src = dt_get_address(reserved_mem, 0, &uv_fw_sz); + uv_base_addr = dt_get_address(uv_fw_node, 0, NULL); - prlog(PR_INFO, "UV: Copying 0x%llx bytes to protected memory 0x%llx from 0x%llx\n", + prlog(PR_INFO, "UV: Copying 0x%llx bytes to protected memory 0x%llx from 0x%llx\n", uv_fw_sz, uv_base_addr, uv_dt_src); - memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); + memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); + } dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons); debug_descriptor.uv_memcons_phys = (u64)&uv_memcons; +err: + local_free(uv_image); +} + +/* + * Preload the UV image from PNOR partition + * + * uv_image is allocated locally to the chip and freed here if preload fails + * or free in init_uv + */ +void uv_preload_image(void) +{ + struct proc_chip *chip = next_chip(NULL); + int ret; + + prlog(PR_DEBUG, "UV: Preload starting\n"); + + uv_image_size = MAX_COMPRESSED_UV_IMAGE_SIZE; + uv_image = local_alloc(chip->id, uv_image_size, uv_image_size); + if (!uv_image) { + prerror("UV: Memory allocation failed\n"); + return; + } + memset(uv_image, 0, uv_image_size); + + ret = start_preload_resource(RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, + uv_image, &uv_image_size); + + if (ret != OPAL_SUCCESS) { + local_free(uv_image); + prerror("UV: platform load failed: %d\n", ret); + } } diff --git a/include/platform.h b/include/platform.h index ef93278b..57b2eeef 100644 --- a/include/platform.h +++ b/include/platform.h @@ -17,6 +17,7 @@ enum resource_id { RESOURCE_ID_INITRAMFS, RESOURCE_ID_CAPP, RESOURCE_ID_IMA_CATALOG, + RESOURCE_ID_UV_IMAGE, RESOURCE_ID_VERSION, RESOURCE_ID_KERNEL_FW, }; diff --git a/include/ultravisor.h b/include/ultravisor.h index 84217d66..8048cb76 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -64,4 +64,7 @@ static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) return ucall(UV_WRITE_SCOM, retbuf, partid, pcb_addr, val); } +#define MAX_COMPRESSED_UV_IMAGE_SIZE 0x40000 /* 256 Kilobytes */ +void uv_preload_image(void); + #endif /* __ULTRAVISOR_H */ From patchwork Wed Aug 26 18:37:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352108 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcFjh4DqQz9sSP for ; Thu, 27 Aug 2020 05:07:36 +1000 (AEST) Authentication-Results: ozlabs.org; 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Wed, 26 Aug 2020 18:38:34 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:34 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:46 -0400 Message-Id: <20200826183749.143980-9-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_12:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=1 spamscore=0 mlxlogscore=999 impostorscore=0 priorityscore=1501 mlxscore=0 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260141 Subject: [Skiboot] [PATCH v8 08/11] hdata/memory.c: Parse HDAT for secure memory X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The secure memory ranges are provided by the hostboot through HDAT. Skiboot parses HDAT and creates secure-memory@ device tree nodes. The secure-memory nodes set dev_type to "secure-memory" so the kernel doesn't try to use them. In the HDIF_ms_area_address_range structure, HDAT spec version 10.5, the mirror attribute at offset 0x14 is renamed to memory attribute. The memory attribute now defines byte 3 as secure memory whereas previously it was reserved. The rest of the attribute is unchanged: 1st byte -> Range is Mirrorable 0x00 = false 0x01 = true 2nd byte -> Hardware Mirroring Algorithm 0x0A – Memory Mirroring algorithm for P9 systems 0xFF – Memory Mirroring Not Supported 3rd byte -> SMF Memory 0x00 = false 0x01 = true 4th byte -> Reserved Signed-off-by: Ryan Grimm --- hdata/memory.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hdata/memory.c b/hdata/memory.c index bd47fee4..9443f297 100755 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -32,7 +32,7 @@ struct HDIF_ms_area_address_range { __be64 start; __be64 end; __be32 chip; - __be32 mirror_attr; + __be32 memory_attr; __be64 mirror_start; __be32 controller_id; __be32 phys_attr; @@ -66,6 +66,9 @@ struct HDIF_ms_area_address_range { #define MS_CONTROLLER_MCC_ID(id) GETFIELD(PPC_BITMASK32(8, 15), id) #define MS_CONTROLLER_OMI_ID(id) GETFIELD(PPC_BITMASK32(16, 31), id) +#define MS_ATTR_PEF PPC_BIT32(23) +#define UV_SECURE_MEM_BIT PPC_BIT(15) + struct HDIF_ms_area_id { __be16 id; #define MS_PTYPE_RISER_CARD 0x8000 @@ -150,10 +153,10 @@ static bool add_address_range(struct dt_node *root, chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip)); prlog(PR_DEBUG, " Range: 0x%016llx..0x%016llx " - "on Chip 0x%x mattr: 0x%x pattr: 0x%x status:0x%x\n", + "on Chip 0x%x memattr: 0x%08x pattr: 0x%x status:0x%x\n", (long long)be64_to_cpu(arange->start), (long long)be64_to_cpu(arange->end), - chip_id, be32_to_cpu(arange->mirror_attr), + chip_id, be32_to_cpu(arange->memory_attr), mem_type, mem_status); /* reg contains start and length */ @@ -182,6 +185,13 @@ static bool add_address_range(struct dt_node *root, return false; } + if (be32_to_cpu(arange->memory_attr) & MS_ATTR_PEF) { + prlog(PR_DEBUG, "HDAT: Found secure memory\n"); + name = "secure-memory"; + dev_type = "secure-memory"; + compat = "ibm,secure-memory"; + } + if (be16_to_cpu(id->flags) & MS_AREA_SHARED) { mem = dt_find_by_name_addr(dt_root, name, reg[0]); if (mem) { From patchwork Wed Aug 26 18:37:47 2020 Content-Type: text/plain; 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Wed, 26 Aug 2020 18:38:41 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 07QIce9X48759110 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 26 Aug 2020 18:38:40 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9445CAC060 for ; Wed, 26 Aug 2020 18:38:40 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 63746AC05B for ; Wed, 26 Aug 2020 18:38:40 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:40 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:47 -0400 Message-Id: <20200826183749.143980-10-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=985 phishscore=0 impostorscore=0 adultscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 clxscore=1015 suspectscore=1 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260137 Subject: [Skiboot] [PATCH v8 09/11] Create ibm, ultravisor node after uv image loaded X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" See doc/opal-uv-abi.rst for details. Signed-off-by: Ryan Grimm --- hw/ultravisor.c | 28 ++++++++++++++++++++++++++++ include/ultravisor.h | 2 ++ 2 files changed, 30 insertions(+) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 34c16404..9b408e40 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -75,6 +75,32 @@ int start_ultravisor(void *fdt) return OPAL_SUCCESS; } +static void add_uv(void) +{ + struct dt_node *uv_node, *secure_mem_node, *uv_fw_node; + uint64_t uv_fw_start; + char fw_name[64]; + + secure_mem_node = dt_find_compatible_node_on_chip(dt_root, NULL, + "ibm,secure-memory", 0); + if (!secure_mem_node) { + prlog(PR_DEBUG, "HDAT: No ibm,secure-memory found\n"); + return; + } + + uv_node = dt_new_check(dt_root, "ibm,ultravisor"); + dt_add_property_string(uv_node, "compatible", "ibm,ultravisor"); + dt_add_property_cells(uv_node, "#address-cells", 2); + dt_add_property_cells(uv_node, "#size-cells", 2); + + uv_fw_start = dt_get_address(secure_mem_node, 0, NULL); + + snprintf(fw_name, 64, "firmware@%llx", (unsigned long long)uv_fw_start); + uv_fw_node = dt_new_check(uv_node, fw_name); + dt_add_property_string(uv_fw_node, "compatible", "ibm,uv-firmware"); + dt_add_property_u64s(uv_fw_node, "reg", uv_fw_start, UV_LOAD_MAX_SIZE); +} + static int uv_decompress_image(void) { struct xz_decompress uv_xz; @@ -105,6 +131,8 @@ static int uv_decompress_image(void) return OPAL_INTERNAL_ERROR; } + add_uv(); + return OPAL_SUCCESS; } diff --git a/include/ultravisor.h b/include/ultravisor.h index 8048cb76..a2ae1ac5 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -67,4 +67,6 @@ static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) #define MAX_COMPRESSED_UV_IMAGE_SIZE 0x40000 /* 256 Kilobytes */ void uv_preload_image(void); +#define UV_LOAD_MAX_SIZE 0x200000 + #endif /* __ULTRAVISOR_H */ From patchwork Wed Aug 26 18:37:48 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352089 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF8D63dSz9sRK for ; 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Wed, 26 Aug 2020 18:38:46 +0000 (GMT) Received: from alain.ibm.com (unknown [9.160.10.71]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP for ; Wed, 26 Aug 2020 18:38:46 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:48 -0400 Message-Id: <20200826183749.143980-11-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 phishscore=0 bulkscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 suspectscore=13 impostorscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 10/11] skiboot/imc: Disable IMC node when UV enabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan Don't create the IMC nodes when the ultravisor is enabled. Hypervisor IMC initialization requires access to HOMER and IMC scoms which are protected and only accessable via ultra calls. So, don't create them until the kernel supports the ultra calls. Signed-off-by: Madhavan Srinivasan [ grimm: move S bit check to beginning of function ] [ grimm: comments and commit message ] Signed-off-by: Ryan Grimm --- hw/imc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/imc.c b/hw/imc.c index 927fba0b..f6351225 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -527,6 +527,16 @@ void imc_init(void) struct dt_node *dev; int err_flag = -1; + /* + * If MSR(S) bit is set, HOMER and IMC scoms are only accessible via + * ultra call. The kernels lacks support, so don't create them. + * + * At this point uv_present can't be used since uv_init() + * is called much later, so check the MSR bit. + */ + if (is_msr_bit_set(MSR_S)) + return; + if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { dev = dt_find_compatible_node(dt_root, NULL, "ibm,opal-in-memory-counters"); From patchwork Wed Aug 26 18:37:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1352090 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BcF8f3JXXz9sRK for ; Thu, 27 Aug 2020 04:42:26 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; 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Wed, 26 Aug 2020 18:38:52 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Wed, 26 Aug 2020 14:37:49 -0400 Message-Id: <20200826183749.143980-12-grimm@linux.ibm.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20200826183749.143980-1-grimm@linux.ibm.com> References: <20200826183749.143980-1-grimm@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-26_10:2020-08-26, 2020-08-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 mlxscore=0 malwarescore=0 suspectscore=3 adultscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008260134 Subject: [Skiboot] [PATCH v8 11/11] Add obsolete secure-memory-ranges property X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Upstream kernel code looks for this so keep compatibility till it's safe to remove. Signed-off-by: Ryan Grimm --- hw/ultravisor.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 9b408e40..ebea350d 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -75,6 +75,35 @@ int start_ultravisor(void *fdt) return OPAL_SUCCESS; } +static void add_obsolete_uv_prop(struct dt_node *uv_node) +{ + uint64_t secure_start, secure_size; + struct dt_node *np; + int num_ranges = 0; + uint64_t *ranges; + int i = 0; + + dt_for_each_compatible(dt_root, np, "ibm,secure-memory") + num_ranges++; + + ranges = malloc(num_ranges * sizeof(ranges) * 2); + if (!ranges) { + prerror("UV: Malloc failed"); + return; + } + + dt_for_each_compatible(dt_root, np, "ibm,secure-memory") { + secure_start = dt_get_address(np, 0, &secure_size); + ranges[i] = secure_start; + ranges[i++] = secure_size; + } + + dt_add_property(uv_node, "secure-memory-ranges", + ranges, sizeof(ranges)); + free(ranges); +} + + static void add_uv(void) { struct dt_node *uv_node, *secure_mem_node, *uv_fw_node; @@ -99,6 +128,8 @@ static void add_uv(void) uv_fw_node = dt_new_check(uv_node, fw_name); dt_add_property_string(uv_fw_node, "compatible", "ibm,uv-firmware"); dt_add_property_u64s(uv_fw_node, "reg", uv_fw_start, UV_LOAD_MAX_SIZE); + + add_obsolete_uv_prop(uv_node); } static int uv_decompress_image(void)