From patchwork Thu Aug 13 09:26:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1344174 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256 header.s=ti-com-17Q1 header.b=HHEVXsl6; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BS1Rj2YYVz9sTH for ; Thu, 13 Aug 2020 19:26:57 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 02592821E0; Thu, 13 Aug 2020 11:26:41 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="HHEVXsl6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0534D81C33; Thu, 13 Aug 2020 11:26:39 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 2357C812FE for ; Thu, 13 Aug 2020 11:26:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vigneshr@ti.com Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 07D9QYbI055991 for ; Thu, 13 Aug 2020 04:26:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1597310794; bh=YDB+Ub2qtxF0oGRs9xYmrmR9iLgUpCcRFg2vjj8IoFk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=HHEVXsl6hzSxkjP5Axb41R2cLSz75VqPYLkcTDmgaEgUz5NnO8uxhbnpRVl6bGoXL RfI9hNCHfebrCgVMtfH6gvYJzJu89mAmLgKcfIsixqrTcnQhFVZR313dj8L+OVo1AK HdgNVEvf66iZlGOkcVqsgsSMYDR6gwf4JU9CncWk= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 07D9QYFP101837 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Thu, 13 Aug 2020 04:26:34 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Thu, 13 Aug 2020 04:26:34 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 13 Aug 2020 04:26:34 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07D9QUrm076777; Thu, 13 Aug 2020 04:26:32 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: Vignesh Raghavendra , Subject: [PATCH 1/5] arm: mach-k3: Add HyperFlash boot mode support Date: Thu, 13 Aug 2020 14:56:15 +0530 Message-ID: <20200813092619.21027-2-vigneshr@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200813092619.21027-1-vigneshr@ti.com> References: <20200813092619.21027-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode to NOR boot to enable SPL to load next stage using NOR boot flow. Signed-off-by: Vignesh Raghavendra --- arch/arm/mach-k3/include/mach/j721e_spl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h index 3fa85ca3b6..e8947917a6 100644 --- a/arch/arm/mach-k3/include/mach/j721e_spl.h +++ b/arch/arm/mach-k3/include/mach/j721e_spl.h @@ -15,6 +15,7 @@ #define BOOT_DEVICE_ETHERNET 0x04 #define BOOT_DEVICE_I2C 0x06 #define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH /* With BootMode B = 1 */ #define BOOT_DEVICE_MMC2 0x10 From patchwork Thu Aug 13 09:26:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1344175 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Thu, 13 Aug 2020 04:26:36 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07D9QUrn076777; Thu, 13 Aug 2020 04:26:34 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: Vignesh Raghavendra , Subject: [PATCH 2/5] board: ti: j721e: Add support for HyperFlash detection Date: Thu, 13 Aug 2020 14:56:16 +0530 Message-ID: <20200813092619.21027-3-vigneshr@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200813092619.21027-1-vigneshr@ti.com> References: <20200813092619.21027-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of them can be used at any time. J7200 EVM has both HyperFlash and OSPI flash on board. There is a user switch (SW3.1) that can be toggled to select OSPI flash vs HyperFlash. Read the state of this switch via wkup_gpio0_6 line and fixup the DT nodes to select OSPI vs HyperFlash Signed-off-by: Vignesh Raghavendra --- board/ti/j721e/evm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index ebaa6faa93..7925b76ab7 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -117,6 +117,13 @@ static void __maybe_unused detect_enable_hyperflash(void *blob) } #endif +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TARGET_J7200_A72_EVM) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + detect_enable_hyperflash(spl_image->fdt_addr); +} +#endif + #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { From patchwork Thu Aug 13 09:26:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1344176 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 13 Aug 2020 04:26:38 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07D9QUro076777; Thu, 13 Aug 2020 04:26:37 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: Vignesh Raghavendra , Subject: [PATCH 3/5] ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash Date: Thu, 13 Aug 2020 14:56:17 +0530 Message-ID: <20200813092619.21027-4-vigneshr@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200813092619.21027-1-vigneshr@ti.com> References: <20200813092619.21027-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Enable HyperBus and HyperFlash to support HyperFlash boot. Signed-off-by: Vignesh Raghavendra --- .../k3-j7200-common-proc-board-u-boot.dtsi | 28 +++++++++++++ .../arm/dts/k3-j7200-r5-common-proc-board.dts | 40 +++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 4972a7559f..0a5faa2134 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -131,3 +131,31 @@ dr_mode = "peripheral"; u-boot,dm-spl; }; + +&wkup_gpio_pins_default { + u-boot,dm-spl; +}; + +&wkup_gpio0 { + u-boot,dm-spl; +}; + +&mcu_fss0_hpb0_pins_default { + u-boot,dm-spl; +}; + +&fss { + u-boot,dm-spl; +}; + +&hbmc { + u-boot,dm-spl; + + flash@0,0 { + u-boot,dm-spl; + }; +}; + +&hbmc_mux { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f5e4166926..bd30284755 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -107,6 +107,31 @@ J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; }; + + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; }; &main_pmx0 { @@ -214,4 +239,19 @@ maximum-speed = "high-speed"; }; +&hbmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; + ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + }; +}; + #include "k3-j7200-common-proc-board-u-boot.dtsi" From patchwork Thu Aug 13 09:26:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1344177 X-Patchwork-Delegate: lokeshvutla@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Thu, 13 Aug 2020 04:26:41 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 13 Aug 2020 04:26:40 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07D9QUrp076777; Thu, 13 Aug 2020 04:26:39 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: Vignesh Raghavendra , Subject: [PATCH 4/5] configs: j7200_evm_*_defconfig: Enable HyperFlash boot related configs Date: Thu, 13 Aug 2020 14:56:18 +0530 Message-ID: <20200813092619.21027-5-vigneshr@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200813092619.21027-1-vigneshr@ti.com> References: <20200813092619.21027-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Enable configs required to support HyperFlash boot and detection of onboard mux switch for HyperFlash selection Signed-off-by: Vignesh Raghavendra --- configs/j7200_evm_a72_defconfig | 3 +++ configs/j7200_evm_r5_defconfig | 13 +++++++++++++ 2 files changed, 16 insertions(+) diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 6e854648eb..a0046c32e1 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -41,7 +41,9 @@ CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y @@ -87,6 +89,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 2908bc30c4..bd1268e9cf 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x70000 @@ -37,7 +38,9 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y @@ -67,6 +70,8 @@ CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_SPL_OF_TRANSLATE=y CONFIG_CLK=y CONFIG_SPL_CLK=y @@ -87,6 +92,14 @@ CONFIG_MMC_SDHCI=y CONFIG_SPL_MMC_SDHCI_ADMA=y CONFIG_MMC_SDHCI_AM654=y CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_HBMC_AM654=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_STMICRO=y From patchwork Thu Aug 13 09:26:19 2020 Content-Type: text/plain; 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Thu, 13 Aug 2020 04:26:42 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Thu, 13 Aug 2020 04:26:42 -0500 Received: from ula0132425.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 07D9QUrq076777; Thu, 13 Aug 2020 04:26:41 -0500 From: Vignesh Raghavendra To: Lokesh Vutla CC: Vignesh Raghavendra , Subject: [PATCH 5/5] configs: j721e_evm.h: Add U-Boot image address for HyperFlash boot Date: Thu, 13 Aug 2020 14:56:19 +0530 Message-ID: <20200813092619.21027-6-vigneshr@ti.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200813092619.21027-1-vigneshr@ti.com> References: <20200813092619.21027-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean Add memory mapped address location of U-Boot images in HyperFlash boot mode. Signed-off-by: Vignesh Raghavendra --- include/configs/j721e_evm.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index c8a76037ff..a570893378 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -23,8 +23,10 @@ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else +#define CONFIG_SYS_UBOOT_BASE 0x50080000 /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as * possible (to allow the build to go through), as this directly affects