From patchwork Mon Aug 3 21:00:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340506 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Kc4sKYz9sTR for ; Tue, 4 Aug 2020 07:01:24 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729032AbgHCVBY (ORCPT ); Mon, 3 Aug 2020 17:01:24 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:34288 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbgHCVBX (ORCPT ); Mon, 3 Aug 2020 17:01:23 -0400 Received: by mail-io1-f65.google.com with SMTP id q75so31848823iod.1; Mon, 03 Aug 2020 14:01:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bKskqR1BQLcQkRJa4jVCjBb26v/8ydnan9t1CfXlQP0=; b=F3I5h+1s3UcJuJQIeVbdou8/lAyhnUMlEhtMa1/w69LqALXHoY4ZNvEqEZ8I7v1E4b 2jNorcDEgjjTASJg9DPX9XhGvMvRZK44Y7EHm00YQCDJ99YYZ3nYiKIKRMnhrRfj1cAR uZv7WY5kUeNPzuJOy3HgdGN261vglpbF6hCEd8f/R0gPmI6/7Cv7ueRiqOEgllHS75Ks J8u6RYTVWDsKnl6L6ECuQiOvJzm0qpFSZC0/IIjTrNZMPJO0uuZ3oP8hyfoFxL16n8xS 7pqLANaQt55//SdPd5NxH9pt31J4i7B6G+0hxwTZnbCNQ7qyWWtbGKMNK/oB7cPOJD1c veuQ== X-Gm-Message-State: AOAM533y/m1MgN+Lfli8vdjoQidgdVwd3BzWF9Zq0d/6fMSOkfvVC/RZ 6yAZDex/edq+AqGKKbyugQ== X-Google-Smtp-Source: ABdhPJy4qG4p8bfrwbYSt3lvEPjhQpXlxLgUy+tuEvf+7Lf39Luq/OZA9TVNwuc57X3DpMVIygnSPw== X-Received: by 2002:a05:6638:2601:: with SMTP id m1mr1810484jat.141.1596488481653; Mon, 03 Aug 2020 14:01:21 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:21 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 01/27] PCI: Allow root and child buses to have different pci_ops Date: Mon, 3 Aug 2020 15:00:50 -0600 Message-Id: <20200803210116.3132633-2-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PCI host bridges often have different ways to access the root and child bus config spaces. The host bridge drivers have invented their own abstractions to handle this. Let's support having different root and child bus pci_ops so these per driver abstractions can be removed. Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/probe.c | 8 +++++++- include/linux/pci.h | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 2f66988cea25..8712e595174d 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1030,6 +1030,7 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) { struct pci_bus *child; + struct pci_host_bridge *host; int i; int ret; @@ -1039,11 +1040,16 @@ static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, return NULL; child->parent = parent; - child->ops = parent->ops; child->msi = parent->msi; child->sysdata = parent->sysdata; child->bus_flags = parent->bus_flags; + host = pci_find_host_bridge(parent); + if (host->child_ops) + child->ops = host->child_ops; + else + child->ops = parent->ops; + /* * Initialize some portions of the bus device, but don't register * it now as the parent is not properly set up yet. diff --git a/include/linux/pci.h b/include/linux/pci.h index c79d83304e52..cec789a0437e 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -516,6 +516,7 @@ struct pci_host_bridge { struct device dev; struct pci_bus *bus; /* Root bus */ struct pci_ops *ops; + struct pci_ops *child_ops; void *sysdata; int busnr; struct list_head windows; /* resource_entry */ From patchwork Mon Aug 3 21:00:51 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340509 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Kk2yzDz9sTK for ; Tue, 4 Aug 2020 07:01:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729338AbgHCVB0 (ORCPT ); Mon, 3 Aug 2020 17:01:26 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:32825 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbgHCVBZ (ORCPT ); Mon, 3 Aug 2020 17:01:25 -0400 Received: by mail-il1-f194.google.com with SMTP id p16so21555130ile.0; Mon, 03 Aug 2020 14:01:24 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bKkfbqtFs4Kbwg3DVrwD4EpvIH0b0CJsDrYNB8t8wYc=; b=K4K81kwhURZLjBoN5skJTJbRLhzsDfzeasnLbCI5VohAbnP5ZH+/SfT0Vm9Bu+p09N muOOqweLvp0EjYPJPsDSMi4w/sQIDQW11EMhUQXaXw1ZXRT66qCMDsitu9isybSc2uW6 Q/dgho82FhzK4tgYVxcy+q4Eq2yFci6fWIHFEvMcDUU8CIIarmSOK5kTffI5Knwt/hzs nlJ4TnjplXj9KsSV3MWjyTtUylkh3zr375+zzcxKuDvFl1mlTF0numuNjFDaBwOfM4jX GO2gCYSakP5dmo9iFEPd/sa1s3TtwjanXGL98hA4jqsAY3QXnUEJ55YaRxPZaWTqvzp5 gvTg== X-Gm-Message-State: AOAM532hLjx2c/TyIX1/luReVd8P2M8XEiF4ODujkPWBaIMuIMWkTpXK vB81LwUKgQBFIgIprq1YSg== X-Google-Smtp-Source: ABdhPJw4WMAKi84yjvuB4NlTKVq4hN/CQshetql5tZed0XuQCt7CLqL/x/eQ7de+2ioPLWoU6nJ9fg== X-Received: by 2002:a92:a112:: with SMTP id v18mr1292705ili.124.1596488484082; Mon, 03 Aug 2020 14:01:24 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:23 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 02/27] PCI: dwc: Use DBI accessors instead of own config accessors Date: Mon, 3 Aug 2020 15:00:51 -0600 Message-Id: <20200803210116.3132633-3-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Designware DBI space contains the root bus bridge config space. Platforms needing custom {rd,wr}_own_conf functions are also the ones needing custom {read,write}_dbi ops functions and the access sequences are the same. Replace all dw_pcie_{rd,wr}_own_conf() calls with the DBI variants in preparation to remove dw_pcie_{rd,wr}_own_conf(). Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 55 +++++++------------ 1 file changed, 19 insertions(+), 36 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0a4a5aa6fe46..6232aefbbdb4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -82,13 +82,13 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) unsigned long val; u32 status, num_ctrls; irqreturn_t ret = IRQ_NONE; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; for (i = 0; i < num_ctrls; i++) { - dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + - (i * MSI_REG_CTRL_BLOCK_SIZE), - 4, &status); + status = dw_pcie_readl_dbi(pci, PCIE_MSI_INTR0_STATUS + + (i * MSI_REG_CTRL_BLOCK_SIZE)); if (!status) continue; @@ -148,6 +148,7 @@ static int dw_pci_msi_set_affinity(struct irq_data *d, static void dw_pci_bottom_mask(struct irq_data *d) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; unsigned long flags; @@ -158,8 +159,7 @@ static void dw_pci_bottom_mask(struct irq_data *d) bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; pp->irq_mask[ctrl] |= BIT(bit); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -167,6 +167,7 @@ static void dw_pci_bottom_mask(struct irq_data *d) static void dw_pci_bottom_unmask(struct irq_data *d) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; unsigned long flags; @@ -177,8 +178,7 @@ static void dw_pci_bottom_unmask(struct irq_data *d) bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; pp->irq_mask[ctrl] &= ~BIT(bit); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -186,13 +186,14 @@ static void dw_pci_bottom_unmask(struct irq_data *d) static void dw_pci_bottom_ack(struct irq_data *d) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); unsigned int res, bit, ctrl; ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL; res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, BIT(bit)); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit)); } static struct irq_chip dw_pci_msi_bottom_irq_chip = { @@ -310,10 +311,8 @@ void dw_pcie_msi_init(struct pcie_port *pp) msi_target = (u64)pp->msi_data; /* Program the msi_data */ - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, - lower_32_bits(msi_target)); - dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, - upper_32_bits(msi_target)); + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); + dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); } EXPORT_SYMBOL_GPL(dw_pcie_msi_init); @@ -327,7 +326,6 @@ int dw_pcie_host_init(struct pcie_port *pp) struct pci_bus *child; struct pci_host_bridge *bridge; struct resource *cfg_res; - u32 hdr_type; int ret; raw_spin_lock_init(&pci->pp.lock); @@ -458,21 +456,6 @@ int dw_pcie_host_init(struct pcie_port *pp) goto err_free_msi; } - ret = dw_pcie_rd_own_conf(pp, PCI_HEADER_TYPE, 1, &hdr_type); - if (ret != PCIBIOS_SUCCESSFUL) { - dev_err(pci->dev, "Failed reading PCI_HEADER_TYPE cfg space reg (ret: 0x%x)\n", - ret); - ret = pcibios_err_to_errno(ret); - goto err_free_msi; - } - if (hdr_type != PCI_HEADER_TYPE_BRIDGE) { - dev_err(pci->dev, - "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n", - hdr_type); - ret = -EIO; - goto err_free_msi; - } - pp->root_bus_nr = pp->busn->start; bridge->dev.parent = dev; @@ -651,12 +634,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp) /* Initialize IRQ Status array */ for (ctrl = 0; ctrl < num_ctrls; ctrl++) { pp->irq_mask[ctrl] = ~0; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, pp->irq_mask[ctrl]); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + pp->irq_mask[ctrl]); + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); + ~0); } } @@ -698,14 +681,14 @@ void dw_pcie_setup_rc(struct pcie_port *pp) pp->io_bus_addr, pp->io_size); } - dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); /* Program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + dw_pcie_writew_dbi(pci, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); val |= PORT_LOGIC_SPEED_CHANGE; - dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); dw_pcie_dbi_ro_wr_dis(pci); } From patchwork Mon Aug 3 21:00:52 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340510 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Kl1gNCz9sTR for ; Tue, 4 Aug 2020 07:01:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729346AbgHCVB3 (ORCPT ); Mon, 3 Aug 2020 17:01:29 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:38423 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729344AbgHCVB1 (ORCPT ); Mon, 3 Aug 2020 17:01:27 -0400 Received: by mail-io1-f66.google.com with SMTP id l1so39991437ioh.5; Mon, 03 Aug 2020 14:01:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ijQ8ATU40Ukxf+vdFPpN/cTBNWQIy8LHFEwNkXuS7vE=; b=TtA3D50HOWjGSOYcI0fLq7MAUnDBSi++nGASm4Aoh/xGbxG+Nth6WBRpCcWzR9SZpJ zXFkOFhdk5CglhnIbRVhmHVnrTacwOWTsbwSRutc8x0VmJKmquUL+Gsix5cdpmcsFwQz k0+kaJQSrIPorGnuaRYv9orYBj9W0AYPkcJe7trNLYw/agEG2PAuWh4BjPBgOjPjVSg8 Pwsc5AphA4aWpxRoxYG36XEP47a81vesf02tunJ5SNy+qKfpGxOeW++4gDyBA4TwHmyB Eq121ULzAvJ6cWj5psaqF7VRaLKEH/0fSCEaHlmY4VaVJYSKZO/gmO4qxftZGmUIOTff TY3w== X-Gm-Message-State: AOAM532GpYjM3KbWCmeSb05lEiLzZCNVZwWkvEuYlBu6FitDnYc5T/Gp YmOiADsJm8DwexS5xjTDBQ== X-Google-Smtp-Source: ABdhPJwDDB+OwHWjJuTy7sDEknkVzY4VCrs5f0YZ1QmljRmggfDq+USGhZLjxDletIoYITtztOCGKA== X-Received: by 2002:a05:6638:2482:: with SMTP id x2mr1801792jat.55.1596488486266; Mon, 03 Aug 2020 14:01:26 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:25 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 03/27] PCI: dwc: Allow overriding bridge pci_ops Date: Mon, 3 Aug 2020 15:00:52 -0600 Message-Id: <20200803210116.3132633-4-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org In preparation to allow drivers to set their own root and child pci_ops instead of using the DWC specific config space ops, we need to make the pci_host_bridge pointer available and move setting the bridge->ops and bridge->child_ops pointer to before the .host_init() hook. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 15 ++++++++++----- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6232aefbbdb4..7cd8c9528d4c 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -344,6 +344,8 @@ int dw_pcie_host_init(struct pcie_port *pp) if (!bridge) return -ENOMEM; + pp->bridge = bridge; + ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows, &bridge->dma_ranges, NULL); if (ret) @@ -450,6 +452,10 @@ int dw_pcie_host_init(struct pcie_port *pp) } } + /* Set default bus ops */ + bridge->ops = &dw_pcie_ops; + bridge->child_ops = &dw_pcie_ops; + if (pp->ops->host_init) { ret = pp->ops->host_init(pp); if (ret) @@ -461,7 +467,6 @@ int dw_pcie_host_init(struct pcie_port *pp) bridge->dev.parent = dev; bridge->sysdata = pp; bridge->busnr = pp->root_bus_nr; - bridge->ops = &dw_pcie_ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; @@ -667,11 +672,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_COMMAND, val); /* - * If the platform provides ->rd_other_conf, it means the platform - * uses its own address translation component rather than ATU, so - * we should not program the ATU here. + * If the platform provides its own child bus config accesses, it means + * the platform uses its own address translation component rather than + * ATU, so we should not program the ATU here. */ - if (!pp->ops->rd_other_conf) { + if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) { dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 656e00f8fbeb..bad3cddab28e 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -201,6 +201,7 @@ struct pcie_port { u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; struct pci_bus *root_bus; + struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); }; From patchwork Mon Aug 3 21:00:53 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340513 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Kn67kxz9sTX for ; Tue, 4 Aug 2020 07:01:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729356AbgHCVBa (ORCPT ); Mon, 3 Aug 2020 17:01:30 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:43651 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729040AbgHCVB3 (ORCPT ); Mon, 3 Aug 2020 17:01:29 -0400 Received: by mail-io1-f68.google.com with SMTP id k23so39948190iom.10; Mon, 03 Aug 2020 14:01:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iogw0PHdW281Zilh8Ybv/eHK0mtpVLAHgw0xblz2JaM=; b=Y+G2v9urpYl/zFtdG3UZYy7xrppuQDw4XuVOJnC+YA1KSSOiIgf3tQh6V2qHshLntD xXG3yq5Kw/+74OYr3fWMaSjmr6qZFiU+kEjL8liXnId16rLCSTW4wHsYmF6zW1eR2sNp nZBVHw0nzVPcc/lofqPmwnywFw/aYDPhIlx13HVrEQUKkbHnIHG17t4YdBXLRHLfsNT/ Ns/x3yGacAY9h22ajXgWiKkjU+nnrZ3vrbMOs+LxSkvmrT0JGz8oAwKC8cyAAXfVlWan Y168V6JPNJkR8QePx3brLcY+IdQrrm4DusWfiznfyWgaYpNDYGyUInL2eqP5gktOYj4n MEbA== X-Gm-Message-State: AOAM530Zt6IRkNcoPaDkDcVX4RCQKZPXY85uO8wvzbj3pHI6/1w17vS/ Hd/7blXodU0WArYVg8czgA== X-Google-Smtp-Source: ABdhPJzvA+ZR7sxoZ88i2XSskORxkOa+8bB7U69jJSZRKahou6ztK7tanUL8FCvVfOXfz7EcTwHx3A== X-Received: by 2002:a6b:c504:: with SMTP id v4mr1848864iof.20.1596488488493; Mon, 03 Aug 2020 14:01:28 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:27 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 04/27] PCI: dwc: Add a default pci_ops.map_bus for root port Date: Mon, 3 Aug 2020 15:00:53 -0600 Message-Id: <20200803210116.3132633-5-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Designware root port config space is memory mapped accesses via the DBI space by default. Add a common implementation dw_pcie_own_conf_map_bus() for platforms to use. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 11 +++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 7cd8c9528d4c..e9d31c341881 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -615,6 +615,17 @@ static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); } +void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) +{ + struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + + if (PCI_SLOT(devfn) > 0) + return NULL; + + return pci->dbi_base + where; +} + static struct pci_ops dw_pcie_ops = { .read = dw_pcie_rd_conf, .write = dw_pcie_wr_conf, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index bad3cddab28e..dbe53e464e11 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -378,6 +378,8 @@ void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp); void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); +void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, + int where); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { From patchwork Mon Aug 3 21:00:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Ks0fmbz9sTK for ; Tue, 4 Aug 2020 07:01:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729357AbgHCVBe (ORCPT ); Mon, 3 Aug 2020 17:01:34 -0400 Received: from mail-il1-f196.google.com ([209.85.166.196]:44506 "EHLO mail-il1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728889AbgHCVBc (ORCPT ); Mon, 3 Aug 2020 17:01:32 -0400 Received: by mail-il1-f196.google.com with SMTP id j9so28944215ilc.11; Mon, 03 Aug 2020 14:01:31 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EQL3A7dHzz+gC5njEctrBiMEIqtA+XjXrb2o208g3Ks=; b=F7YBgQRbZju55J1lslO3ZYYUq/hG4N8wTHAwZU2uIZn8/wbItJEPFW7cgXc/wG+XfX h0WHNqI1RTLpyW656CwcisHE7Q+Q4x8mW2n84ZwgibfSrfEBeh6zm2gmmWlakCDUtgEx avkG/p9QCgev92l5nTcWtt14O1h+Elp5VWTer/gNDWmJQlxbloZGCMUvdStxhzeqXlpS LSjbamKWn3SX7BPFb8J11Gzdtulr3dRD/Qp0FqS50o17Sqf7h5MtlxvR1BWPEFbhy8cp PyoI8WMbk9WKubwvcXdA1h7tHii6zExHwmSoD9wS9iFe7js/PGcKdtTMbtf+5I5DxpEU 1XCg== X-Gm-Message-State: AOAM533sflnPRlLher4tSnqpk1k4OBCcobnTMHudfrIOl+9Q6YddgPbV fiUxMbrLl0V74dU6/sv1wQ== X-Google-Smtp-Source: ABdhPJzftW92R17dfbV7F93wEn6AsKYKgSXK+D8yX+DoZOz9nVGWzXcp3oJtQO05/bk7IoPLrTUNQg== X-Received: by 2002:a92:d7cb:: with SMTP id g11mr1303449ilq.89.1596488491153; Mon, 03 Aug 2020 14:01:31 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:30 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 05/27] PCI: dwc: al: Use pci_ops for child config space accessors Date: Mon, 3 Aug 2020 15:00:54 -0600 Message-Id: <20200803210116.3132633-6-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Amazon driver to use the standard pci_ops for child bus config accesses. Cc: Jonathan Chocron Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-al.c | 63 ++++++---------------------- 1 file changed, 13 insertions(+), 50 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c index 270868f3859a..5c5763f14485 100644 --- a/drivers/pci/controller/dwc/pcie-al.c +++ b/drivers/pci/controller/dwc/pcie-al.c @@ -222,14 +222,15 @@ static inline void al_pcie_target_bus_set(struct al_pcie *pcie, reg); } -static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie, - unsigned int busnr, - unsigned int devfn) +static void __iomem *al_pcie_conf_addr_map_bus(struct pci_bus *bus, + unsigned int devfn, int where) { + struct pcie_port *pp = bus->sysdata; + struct al_pcie *pcie = to_al_pcie(to_dw_pcie_from_pp(pp)); + unsigned int busnr = bus->number; struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg; unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask; unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask; - struct pcie_port *pp = &pcie->pci->pp; void __iomem *pci_base_addr; pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base + @@ -245,52 +246,14 @@ static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie, target_bus_cfg->reg_mask); } - return pci_base_addr; -} - -static int al_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 *val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct al_pcie *pcie = to_al_pcie(pci); - unsigned int busnr = bus->number; - void __iomem *pci_addr; - int rc; - - pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn); - - rc = dw_pcie_read(pci_addr + where, size, val); - - dev_dbg(pci->dev, "%d-byte config read from %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n", - size, pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), where, - (pci_addr + where), *val); - - return rc; + return pci_base_addr + where; } -static int al_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct al_pcie *pcie = to_al_pcie(pci); - unsigned int busnr = bus->number; - void __iomem *pci_addr; - int rc; - - pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn); - - rc = dw_pcie_write(pci_addr + where, size, val); - - dev_dbg(pci->dev, "%d-byte config write to %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n", - size, pci_domain_nr(bus), bus->number, - PCI_SLOT(devfn), PCI_FUNC(devfn), where, - (pci_addr + where), val); - - return rc; -} +static struct pci_ops al_child_pci_ops = { + .map_bus = al_pcie_conf_addr_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; static void al_pcie_config_prepare(struct al_pcie *pcie) { @@ -344,6 +307,8 @@ static int al_pcie_host_init(struct pcie_port *pp) struct al_pcie *pcie = to_al_pcie(pci); int rc; + pp->bridge->child_ops = &al_child_pci_ops; + rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id); if (rc) return rc; @@ -358,8 +323,6 @@ static int al_pcie_host_init(struct pcie_port *pp) } static const struct dw_pcie_host_ops al_pcie_host_ops = { - .rd_other_conf = al_pcie_rd_other_conf, - .wr_other_conf = al_pcie_wr_other_conf, .host_init = al_pcie_host_init, }; From patchwork Mon Aug 3 21:00:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Kt0JzQz9sTX for ; Tue, 4 Aug 2020 07:01:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729358AbgHCVBg (ORCPT ); Mon, 3 Aug 2020 17:01:36 -0400 Received: from mail-il1-f195.google.com ([209.85.166.195]:40929 "EHLO mail-il1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729344AbgHCVBe (ORCPT ); Mon, 3 Aug 2020 17:01:34 -0400 Received: by mail-il1-f195.google.com with SMTP id x1so12026155ilp.7; Mon, 03 Aug 2020 14:01:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=enkj1hpfF2DRae6tMsmNr00vC0nnMrJ8ecK1LKopnys=; b=rQn1t+BOENmRWvmbHYrQf3zlPXqpa/lIcaiBI45L63nvwN1Hk5EFBK1wnEIhVnzJLs GtegczRiLxzQ+MWNgA9d7fmKcCg/p2cz4tD+ez+O1QUo9zCAxOB9aaPt+YblWm+TtWX0 1hUA7my7iKW8cyTw3Kki5X0wwPbQ+RJTV2+lArmdqOflhcuGZ8PUhsRWtuV5WkFsHF9/ AC8mP2sVTmP7eBT+lLTZ6HKU0oCBiUUkrbNoxMEefk0ak/tUGF6ccWg12A4a30k/9HFa lkfiP8ggjOeeSpg32rHIr5q1QeCX5NMH/b3ujQfcqUK3JsYdSUwnoJy3relZ040Yzqw1 HRjA== X-Gm-Message-State: AOAM533rOodk6idYvR7l4IbEwNCCo2GO10BSeYOD6a/r70TmD1LVle3Q iN49JDpO7PG5sG8gr/7QJw== X-Google-Smtp-Source: ABdhPJzWPzbp0GjA/fWrdCLZshRyk6S65JBCKe+YdG5gw5OjbQ3+gG0tLzeJjdOPlVejehxqb5N9Qg== X-Received: by 2002:a92:d2c8:: with SMTP id w8mr1409855ilg.38.1596488493349; Mon, 03 Aug 2020 14:01:33 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:32 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 06/27] PCI: dwc: keystone: Use pci_ops for config space accessors Date: Mon, 3 Aug 2020 15:00:55 -0600 Message-Id: <20200803210116.3132633-7-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the TI Keystone driver to use the standard pci_ops for config accesses. Cc: Murali Karicheri Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 40 ++++++++++------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 790679fdfa48..df1194d186bc 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -430,10 +430,10 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) ks_pcie_app_writel(ks_pcie, CMD_STATUS, val); } -static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 *val) +static void __iomem *ks_pcie_other_map_bus(struct pci_bus *bus, + unsigned int devfn, int where) { + struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); u32 reg; @@ -444,25 +444,14 @@ static int ks_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, reg |= CFG_TYPE1; ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); - return dw_pcie_read(pp->va_cfg0_base + where, size, val); + return pp->va_cfg0_base + where; } -static int ks_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, - u32 val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - u32 reg; - - reg = CFG_BUS(bus->number) | CFG_DEVICE(PCI_SLOT(devfn)) | - CFG_FUNC(PCI_FUNC(devfn)); - if (bus->parent->number != pp->root_bus_nr) - reg |= CFG_TYPE1; - ks_pcie_app_writel(ks_pcie, CFG_SETUP, reg); - - return dw_pcie_write(pp->va_cfg0_base + where, size, val); -} +static struct pci_ops ks_child_pcie_ops = { + .map_bus = ks_pcie_other_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; /** * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization @@ -490,6 +479,12 @@ static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); } +static struct pci_ops ks_pcie_ops = { + .map_bus = dw_pcie_own_conf_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + /** * ks_pcie_link_up() - Check if link up */ @@ -807,6 +802,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); int ret; + pp->bridge->ops = &ks_pcie_ops; + pp->bridge->child_ops = &ks_child_pcie_ops; + ret = ks_pcie_config_legacy_irq(ks_pcie); if (ret) return ret; @@ -842,8 +840,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) } static const struct dw_pcie_host_ops ks_pcie_host_ops = { - .rd_other_conf = ks_pcie_rd_other_conf, - .wr_other_conf = ks_pcie_wr_other_conf, .host_init = ks_pcie_host_init, .msi_host_init = ks_pcie_msi_host_init, .scan_bus = ks_pcie_v3_65_scan_bus, From patchwork Mon Aug 3 21:00:56 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340518 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Kw4rkxz9sSt for ; Tue, 4 Aug 2020 07:01:40 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729369AbgHCVBh (ORCPT ); Mon, 3 Aug 2020 17:01:37 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:43661 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729365AbgHCVBg (ORCPT ); Mon, 3 Aug 2020 17:01:36 -0400 Received: by mail-io1-f66.google.com with SMTP id k23so39948561iom.10; Mon, 03 Aug 2020 14:01:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DhVIHy/Rw3yhAfrDggAhIwfl4PW3KaTrEVn3uFz3dc8=; b=mGfvjJ46N/FQjo19ot0o+xbJClOAX2J9x0YQjYvXVvPwJV8D5RmMUofnnr7uHaStkh kDQ7urSLtBiGS1DH3Ofr3wOegJqXTuppubHEkHMJyY/LQFiNYU0ay8kkB9yrvKNvvU6I xPpatg7EMzvGs/sJTPt58eQP1gyF0ltwdPkFfE9e8ARF7KD1ApyVahq9BfNFxVg3ln2b oavXhc37HD4G9Br2ORYxiQdz22laYVX2iQk/UX6Oc1uyeQXj4qstsE2/VIa26Ba09/pN 5DFxBKcscwnYNdPHzVGhPNF2WCwLQZLy1vSamdRwvkVmf57G7kBHcMGezvq8YhPtYx+l XHQA== X-Gm-Message-State: AOAM5311jcXP1s+/hOiG7CXGwpyPb5ci/TY/t4D9FuGXB2xAjPfqTwZG mlefQCtiQJd3MCWK0kxbZg== X-Google-Smtp-Source: ABdhPJyjX1+wO5hyGV3g2v/BQHcjESE2gsWA9W9Ke9+7b6wyQJsyc0STPcQ+YQyGpmdVfbKRm8sSqg== X-Received: by 2002:a5e:d519:: with SMTP id e25mr1841622iom.36.1596488495414; Mon, 03 Aug 2020 14:01:35 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:34 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 07/27] PCI: dwc: tegra: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:00:56 -0600 Message-Id: <20200803210116.3132633-8-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Tegra driver to use the standard pci_ops for root bus config accesses. Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-tegra194.c | 30 ++++++++++++---------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 92b77f7d8354..52bb145c42d1 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -568,42 +568,44 @@ static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) return IRQ_HANDLED; } -static int tegra_pcie_dw_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) +static int tegra_pcie_dw_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - /* * This is an endpoint mode specific register happen to appear even * when controller is operating in root port mode and system hangs * when it is accessed with link being in ASPM-L1 state. * So skip accessing it altogether */ - if (where == PORT_LOGIC_MSIX_DOORBELL) { + if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) { *val = 0x00000000; return PCIBIOS_SUCCESSFUL; } - return dw_pcie_read(pci->dbi_base + where, size, val); + return pci_generic_config_read(bus, devfn, where, size, val); } -static int tegra_pcie_dw_wr_own_conf(struct pcie_port *pp, int where, int size, - u32 val) +static int tegra_pcie_dw_wr_own_conf(struct pci_bus *bus, u32 devfn, int where, + int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - /* * This is an endpoint mode specific register happen to appear even * when controller is operating in root port mode and system hangs * when it is accessed with link being in ASPM-L1 state. * So skip accessing it altogether */ - if (where == PORT_LOGIC_MSIX_DOORBELL) + if (!PCI_SLOT(devfn) && where == PORT_LOGIC_MSIX_DOORBELL) return PCIBIOS_SUCCESSFUL; - return dw_pcie_write(pci->dbi_base + where, size, val); + return pci_generic_config_write(bus, devfn, where, size, val); } +static struct pci_ops tegra_pci_ops = { + .map_bus = dw_pcie_own_conf_map_bus, + .read = tegra_pcie_dw_rd_own_conf, + .write = tegra_pcie_dw_wr_own_conf, +}; + #if defined(CONFIG_PCIEASPM) static void disable_aspm_l11(struct tegra_pcie_dw *pcie) { @@ -970,6 +972,8 @@ static int tegra_pcie_dw_host_init(struct pcie_port *pp) struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); u32 val, tmp, offset, speed; + pp->bridge->ops = &tegra_pci_ops; + tegra_pcie_prepare_host(pp); if (dw_pcie_wait_for_link(pci)) { @@ -1057,8 +1061,6 @@ static const struct dw_pcie_ops tegra_dw_pcie_ops = { }; static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = { - .rd_own_conf = tegra_pcie_dw_rd_own_conf, - .wr_own_conf = tegra_pcie_dw_wr_own_conf, .host_init = tegra_pcie_dw_host_init, .set_num_vectors = tegra_pcie_set_msi_vec_num, }; From patchwork Mon Aug 3 21:00:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340521 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Ky2Km1z9sSt for ; Tue, 4 Aug 2020 07:01:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729061AbgHCVBj (ORCPT ); Mon, 3 Aug 2020 17:01:39 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:45700 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729370AbgHCVBi (ORCPT ); Mon, 3 Aug 2020 17:01:38 -0400 Received: by mail-io1-f65.google.com with SMTP id u126so2717262iod.12; Mon, 03 Aug 2020 14:01:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qfEvf5H5JZ3RCT8OcWDqKEAE854FjnIcjQahQFy60ZU=; b=ERSly5GkwWXYFvfxneAsDkwNhQgKm/cv6Qa9KURKeQacv7ptH1yGplFUYjHsTfLjl+ 4EIBd34LkyV8Y2IcPZhsQYo+WRs7oNhY9u72xMhDrr8WNotB0XDDZXOODB7P1nMnMqhR Zdf1kqqp9UjcCtKDAQo37AacHl64/w/m7F+MPREjFXBMZwdzYsCB3JV+De3o/UTj+bIi +IQTgPzoEcbSlUdXCEJ/+R2Fqe5rf/OHNmNx66SGkPmomaHFWThW2Fi7o0SaConG/cai PuRJl2roJRdNK7abqq+P6f3l05JsLhfnym9vVigyEeftkvr38MQOfivvdZMmrwcK260W bNcA== X-Gm-Message-State: AOAM5313zTPMxSYsr3hEAKJH5QEzzY0U8NvzEj717IpxM4dOH9/8UmKn zvA9jNS1CLl4L13sq+HWjA== X-Google-Smtp-Source: ABdhPJxVu37JrAtNyU3mWLs6CsBaCHUNz0/4V4wrWC42BJDmf56FSirpVGwbFUOMHezq7H+x89bQUQ== X-Received: by 2002:a6b:9008:: with SMTP id s8mr1803377iod.132.1596488497604; Mon, 03 Aug 2020 14:01:37 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:37 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 08/27] PCI: dwc: meson: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:00:57 -0600 Message-Id: <20200803210116.3132633-9-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Amlogic meson driver to use the standard pci_ops for root bus config accesses. FIXME: child bus accessors Cc: Yue Wang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Kevin Hilman Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-meson.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index ca59ba9e0ecd..54ce3369d963 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -383,13 +383,12 @@ static void meson_pcie_enable_interrupts(struct meson_pcie *mp) dw_pcie_msi_init(&mp->pci.pp); } -static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) +static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, + int where, int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); int ret; - ret = dw_pcie_read(pci->dbi_base + where, size, val); + ret = pci_generic_config_read(bus, devfn, where, size, val); if (ret != PCIBIOS_SUCCESSFUL) return ret; @@ -410,13 +409,11 @@ static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, return PCIBIOS_SUCCESSFUL; } -static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where, - int size, u32 val) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - - return dw_pcie_write(pci->dbi_base + where, size, val); -} +static struct pci_ops meson_pci_ops = { + .map_bus = dw_pcie_own_conf_map_bus, + .read = meson_pcie_rd_own_conf, + .write = pci_generic_config_write, +}; static int meson_pcie_link_up(struct dw_pcie *pci) { @@ -463,6 +460,8 @@ static int meson_pcie_host_init(struct pcie_port *pp) struct meson_pcie *mp = to_meson_pcie(pci); int ret; + pp->bridge->ops = &meson_pci_ops; + ret = meson_pcie_establish_link(mp); if (ret) return ret; @@ -473,8 +472,6 @@ static int meson_pcie_host_init(struct pcie_port *pp) } static const struct dw_pcie_host_ops meson_pcie_host_ops = { - .rd_own_conf = meson_pcie_rd_own_conf, - .wr_own_conf = meson_pcie_wr_own_conf, .host_init = meson_pcie_host_init, }; From patchwork Mon Aug 3 21:00:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Kz0QYyz9sTK for ; Tue, 4 Aug 2020 07:01:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729375AbgHCVBl (ORCPT ); Mon, 3 Aug 2020 17:01:41 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:38453 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729372AbgHCVBk (ORCPT ); Mon, 3 Aug 2020 17:01:40 -0400 Received: by mail-io1-f65.google.com with SMTP id l1so39992207ioh.5; Mon, 03 Aug 2020 14:01:40 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uqMmmSdRu2mAJmxJVyfdC1UZDoCNddnAHqJmdw3g1qc=; b=kbh/gROR243Odr5WjQNkYijTi8E5dG08IEnI96YhEKNcfAGLtuYLyJD1JIRTiIuD0C CfFzzGHJYBQxl7NtxACRGHxHO0sOfZwFL167qVqyRcbBrSFw9zEOWgHb7TxkkWSyWk5G b8K7uRWRjjoyk2uZpkzEJUtnNr3MX7nuIplrbGhqz6mUJLZYc7DQ7XtZM68w9SrFezSr hbP5INOFlox0Rl4cvwNaBQZY0vZs177aSvGv0RKb4rHjYNNvz7CS1LZEFL1kafsRIJYK SmUUfCjyDTmSG6752X7d0p2IJnkLPj3LjBXD4mud6wmTi5yj+x/77dbQ/mTXnk8qGTc5 O9sg== X-Gm-Message-State: AOAM531wschz0usaKytMHCOCSv7M8xmzDRoMrxgVay8bT4/i59DHRriV u4TH1w3/rP2v4lnXeqcu1g== X-Google-Smtp-Source: ABdhPJw7+kSjYhGRYEIhQk6tNLudHqZmYvJC/9LNtA8wCqiPqZlbDpGdf2cy3RCei6R9SOjDM6lY5w== X-Received: by 2002:a5e:930b:: with SMTP id k11mr1852419iom.30.1596488499811; Mon, 03 Aug 2020 14:01:39 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:39 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 09/27] PCI: dwc: kirin: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:00:58 -0600 Message-Id: <20200803210116.3132633-10-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the HiSilicon Kirin driver to use the standard pci_ops for root bus config accesses. Cc: Xiaowei Song Cc: Binghui Wang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-kirin.c | 39 +++++++++++++------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index c19617a912bd..1680dc72b416 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -335,34 +335,37 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR); } -static int kirin_pcie_rd_own_conf(struct pcie_port *pp, +static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - kirin_pcie_sideband_dbi_r_mode(kirin_pcie, true); - ret = dw_pcie_read(pci->dbi_base + where, size, val); - kirin_pcie_sideband_dbi_r_mode(kirin_pcie, false); + if (PCI_SLOT(devfn)) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } - return ret; + *val = dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; } -static int kirin_pcie_wr_own_conf(struct pcie_port *pp, +static int kirin_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - kirin_pcie_sideband_dbi_w_mode(kirin_pcie, true); - ret = dw_pcie_write(pci->dbi_base + where, size, val); - kirin_pcie_sideband_dbi_w_mode(kirin_pcie, false); + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; - return ret; + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; } +static struct pci_ops kirin_pci_ops = { + .read = kirin_pcie_rd_own_conf, + .write = kirin_pcie_wr_own_conf, +}; + static u32 kirin_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size) { @@ -428,6 +431,8 @@ static int kirin_pcie_establish_link(struct pcie_port *pp) static int kirin_pcie_host_init(struct pcie_port *pp) { + pp->bridge->ops = &kirin_pci_ops; + kirin_pcie_establish_link(pp); if (IS_ENABLED(CONFIG_PCI_MSI)) @@ -443,8 +448,6 @@ static const struct dw_pcie_ops kirin_dw_pcie_ops = { }; static const struct dw_pcie_host_ops kirin_pcie_host_ops = { - .rd_own_conf = kirin_pcie_rd_own_conf, - .wr_own_conf = kirin_pcie_wr_own_conf, .host_init = kirin_pcie_host_init, }; From patchwork Mon Aug 3 21:00:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340525 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9L34S6yz9sTK for ; Tue, 4 Aug 2020 07:01:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729385AbgHCVBn (ORCPT ); Mon, 3 Aug 2020 17:01:43 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:38507 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729372AbgHCVBn (ORCPT ); Mon, 3 Aug 2020 17:01:43 -0400 Received: by mail-il1-f194.google.com with SMTP id 77so3879440ilc.5; Mon, 03 Aug 2020 14:01:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w74e1Ztc1qAn6gEbliDEy8D1xkphK6dVWVgtaNcLV4w=; b=q1kAxFAcUcChwZzscN/BtqszSs41IJB+QrwM+exX6dedGv3CStCdg/RVz2KB+JVNTd 4IzBPkm0KWUVoQ4ol9qkscOv5vrBQudfo1+NfI9m0Ie9QPrCbL1FWFvWGIoHbsrrhZ7o Ag1BMDk25H9rYpGDvjxrHwK5Q1JAiPIeymUp/zuRaZisSurn+DxHc1OdJVwfvyMS5LTj emC/ivP3X7FimUFw7DQL9RBvzs7V66EsWDpqY/6jAfE+5Gr+AjZr8iDaNI/egBBWDGJh ZpJSCfRz4Q8V8LarXXLf8Q3BIMjaaxvwFWHCAOIN0zRX4W3u+nA95bg1XdzlcJ8PsIFF FWvw== X-Gm-Message-State: AOAM531GjW4M+HLPRoK3DZq9YUI5T4TS4b27JHPhELLBJo/mJY7g9u+i nC2l1dGg0OPiwySPF6Ii8A== X-Google-Smtp-Source: ABdhPJxfAjXpg9S6OMpw6Nsv1iLQNUvPbf7BO8gLdDkl8+aUBf9YmuX7VSlCNgb+o/i5Ag3SVp1l9g== X-Received: by 2002:a92:1b42:: with SMTP id b63mr1415959ilb.76.1596488501865; Mon, 03 Aug 2020 14:01:41 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:41 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 10/27] PCI: dwc: exynos: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:00:59 -0600 Message-Id: <20200803210116.3132633-11-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Samsung Exynos driver to use the standard pci_ops for root bus config accesses. Cc: Jingoo Han Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-exynos.c | 45 ++++++++++++++----------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-exynos.c b/drivers/pci/controller/dwc/pci-exynos.c index c5043d951e80..d5d37cffa441 100644 --- a/drivers/pci/controller/dwc/pci-exynos.c +++ b/drivers/pci/controller/dwc/pci-exynos.c @@ -338,32 +338,37 @@ static void exynos_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, exynos_pcie_sideband_dbi_w_mode(ep, false); } -static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) +static int exynos_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct exynos_pcie *ep = to_exynos_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - exynos_pcie_sideband_dbi_r_mode(ep, true); - ret = dw_pcie_read(pci->dbi_base + where, size, val); - exynos_pcie_sideband_dbi_r_mode(ep, false); - return ret; + if (PCI_SLOT(devfn)) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + *val = dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; } -static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, - u32 val) +static int exynos_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct exynos_pcie *ep = to_exynos_pcie(pci); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - exynos_pcie_sideband_dbi_w_mode(ep, true); - ret = dw_pcie_write(pci->dbi_base + where, size, val); - exynos_pcie_sideband_dbi_w_mode(ep, false); - return ret; + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; + + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; } +static struct pci_ops exynos_pci_ops = { + .read = exynos_pcie_rd_own_conf, + .write = exynos_pcie_wr_own_conf, +}; + static int exynos_pcie_link_up(struct dw_pcie *pci) { struct exynos_pcie *ep = to_exynos_pcie(pci); @@ -381,6 +386,8 @@ static int exynos_pcie_host_init(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct exynos_pcie *ep = to_exynos_pcie(pci); + pp->bridge->ops = &exynos_pci_ops; + exynos_pcie_establish_link(ep); exynos_pcie_enable_interrupts(ep); @@ -388,8 +395,6 @@ static int exynos_pcie_host_init(struct pcie_port *pp) } static const struct dw_pcie_host_ops exynos_pcie_host_ops = { - .rd_own_conf = exynos_pcie_rd_own_conf, - .wr_own_conf = exynos_pcie_wr_own_conf, .host_init = exynos_pcie_host_init, }; From patchwork Mon Aug 3 21:01:00 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9L471bMz9sTS for ; Tue, 4 Aug 2020 07:01:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729388AbgHCVBp (ORCPT ); Mon, 3 Aug 2020 17:01:45 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:45714 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729372AbgHCVBp (ORCPT ); Mon, 3 Aug 2020 17:01:45 -0400 Received: by mail-io1-f65.google.com with SMTP id u126so2717602iod.12; Mon, 03 Aug 2020 14:01:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cgcVbPqzxoZQ8BD2LBqh5z0DmxU5aGMCc3S38te1hMk=; b=T1xN1SiG8Sv7G3fzMq84RCcYSYLkz39xYzkCcIZKo0JnYQk+HIjOoWES7b00a9wCuf Ok9Iu37SKtGYVe7OJcry4VkBKLmxY9f0zy/J10yIOPuiBTBlOtC2ndJQR/igPGIhahPl XvBVCekC2wlrYOSf5WZQMuuZSFV69IlEx5kuveC8NMMpT/GiAuC1KQkaHBVOEleasb5T GB7oxJmLdFMzI/E9vnfqTdJOT80m0f/riQiwtEIN7bWf07H4xkz+CmGEpynoKcve+Vo5 z4q7/G5lNpX8ANjlsAUSJmdjC+4qNu4mSU6mZyoqtcaye4bfNWha3v4zREYM7nWa/CYx a1Dg== X-Gm-Message-State: AOAM530/YJ5pKJ8/nchtXz0NI00U+/cKYPew8evKPfLZl3OfOymBQEHB K1rMVCVvnuCyk1wqM1iiDw== X-Google-Smtp-Source: ABdhPJwZ2v3QRbVXEHElHg+0cQOqL+nUwqS+NoWUw+dR20bJGFNYxn6FK+LKQ0Ij90nYJuTJGr2nyQ== X-Received: by 2002:a05:6638:1690:: with SMTP id f16mr1822826jat.91.1596488504104; Mon, 03 Aug 2020 14:01:44 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:43 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Shawn Guo Subject: [RFC 11/27] PCI: dwc: histb: Use pci_ops for root config space accessors Date: Mon, 3 Aug 2020 15:01:00 -0600 Message-Id: <20200803210116.3132633-12-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the HiSilicon histb driver to use the standard pci_ops for root bus config accesses. Cc: Shawn Guo Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-histb.c | 41 ++++++++++++++----------- 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c index 811b5c6d62ea..0d93088deea3 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -122,32 +122,37 @@ static void histb_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, histb_pcie_dbi_w_mode(&pci->pp, false); } -static int histb_pcie_rd_own_conf(struct pcie_port *pp, int where, - int size, u32 *val) +static int histb_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - histb_pcie_dbi_r_mode(pp, true); - ret = dw_pcie_read(pci->dbi_base + where, size, val); - histb_pcie_dbi_r_mode(pp, false); + if (PCI_SLOT(devfn)) { + *val = ~0; + return PCIBIOS_DEVICE_NOT_FOUND; + } - return ret; + *val = dw_pcie_read_dbi(pci, where, size); + return PCIBIOS_SUCCESSFUL; } -static int histb_pcie_wr_own_conf(struct pcie_port *pp, int where, - int size, u32 val) +static int histb_pcie_wr_own_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - int ret; + struct dw_pcie *pci = to_dw_pcie_from_pp(bus->sysdata); - histb_pcie_dbi_w_mode(pp, true); - ret = dw_pcie_write(pci->dbi_base + where, size, val); - histb_pcie_dbi_w_mode(pp, false); + if (PCI_SLOT(devfn)) + return PCIBIOS_DEVICE_NOT_FOUND; - return ret; + dw_pcie_write_dbi(pci, where, size, val); + return PCIBIOS_SUCCESSFUL; } +static struct pci_ops histb_pci_ops = { + .read = histb_pcie_rd_own_conf, + .write = histb_pcie_wr_own_conf, +}; + static int histb_pcie_link_up(struct dw_pcie *pci) { struct histb_pcie *hipcie = to_histb_pcie(pci); @@ -194,6 +199,8 @@ static int histb_pcie_establish_link(struct pcie_port *pp) static int histb_pcie_host_init(struct pcie_port *pp) { + pp->bridge->ops = &histb_pci_ops; + histb_pcie_establish_link(pp); if (IS_ENABLED(CONFIG_PCI_MSI)) @@ -203,8 +210,6 @@ static int histb_pcie_host_init(struct pcie_port *pp) } static const struct dw_pcie_host_ops histb_pcie_host_ops = { - .rd_own_conf = histb_pcie_rd_own_conf, - .wr_own_conf = histb_pcie_wr_own_conf, .host_init = histb_pcie_host_init, }; From patchwork Mon Aug 3 21:01:01 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340528 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9L60vT9z9sTK for ; Tue, 4 Aug 2020 07:01:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729397AbgHCVBt (ORCPT ); Mon, 3 Aug 2020 17:01:49 -0400 Received: from mail-il1-f193.google.com ([209.85.166.193]:40944 "EHLO mail-il1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729392AbgHCVBs (ORCPT ); Mon, 3 Aug 2020 17:01:48 -0400 Received: by mail-il1-f193.google.com with SMTP id x1so12026731ilp.7; Mon, 03 Aug 2020 14:01:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u/8WdlxIj2tgo5PZc1xxYI0moFux1woMX4shol7l+Cw=; b=e4jKaWMVUf/KIicAv42vpcJM1nODKB586c0ynZ8f0T5kQ/Jh6/mYFIo7nTNVKmyDEn phy46cmnEQxp5DqiT/ADNg6zpWscur9xHrp8jDxhEDfHvoQ9KuwQvlA/liMDf8CLmoFx jXXSkXAyuzqgtT6PPN3uyu8RzD5+TIxx/10gkREKqPm9TbrnEzkGtgZE1AZx+dd8SdGp T8pHVaKZLDN7gVJWolgIgLRdfMbh/bcxz6UqsefEjgZwBcoSJbcv2YcRMDDPyaq6yjtb ufUSrAdA8mMz+r6+uG88uwrIO6dBzSn3rfSYXV5SAXFzDAdSQztbU39HYVoYJEq1HJ48 fUAw== X-Gm-Message-State: AOAM531+j/pfLTtrAh550Il+mewhjaxAeIW5szJzW+hMCpvSt7zamcXh ui4SBEsPbnG417krILAUAg== X-Google-Smtp-Source: ABdhPJzrmbAcmNdnEbm0tgBp/5AY07aPIAywXllP5h77tMmzndDaOvLh9Qs6NLwuucPoLn76/UlYDA== X-Received: by 2002:a05:6e02:ee9:: with SMTP id j9mr1332603ilk.163.1596488507637; Mon, 03 Aug 2020 14:01:47 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:47 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 12/27] PCI: dwc: Remove dwc specific config accessor ops Date: Mon, 3 Aug 2020 15:01:01 -0600 Message-Id: <20200803210116.3132633-13-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that all the drivers needing custom config accessors have been converted to define their own pci_ops, we can remove the DWC specific function callbacks {rd,wr}_{own,other}_conf. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 14 -------------- drivers/pci/controller/dwc/pcie-designware.h | 6 ------ 2 files changed, 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index e9d31c341881..6e9f106e8e05 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -26,9 +26,6 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, { struct dw_pcie *pci; - if (pp->ops->rd_own_conf) - return pp->ops->rd_own_conf(pp, where, size, val); - pci = to_dw_pcie_from_pp(pp); return dw_pcie_read(pci->dbi_base + where, size, val); } @@ -38,9 +35,6 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, { struct dw_pcie *pci; - if (pp->ops->wr_own_conf) - return pp->ops->wr_own_conf(pp, where, size, val); - pci = to_dw_pcie_from_pp(pp); return dw_pcie_write(pci->dbi_base + where, size, val); } @@ -548,10 +542,6 @@ static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { - if (pp->ops->rd_other_conf) - return pp->ops->rd_other_conf(pp, bus, devfn, where, - size, val); - return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val, false); } @@ -559,10 +549,6 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) { - if (pp->ops->wr_other_conf) - return pp->ops->wr_other_conf(pp, bus, devfn, where, - size, val); - return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val, true); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index dbe53e464e11..28e7ad3eb89f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -160,12 +160,6 @@ enum dw_pcie_device_mode { }; struct dw_pcie_host_ops { - int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); - int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); - int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, u32 *val); - int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, - unsigned int devfn, int where, int size, u32 val); int (*host_init)(struct pcie_port *pp); void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); From patchwork Mon Aug 3 21:01:02 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LC4ZHCz9sTK for ; Tue, 4 Aug 2020 07:01:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729394AbgHCVBx (ORCPT ); Mon, 3 Aug 2020 17:01:53 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:32872 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVBx (ORCPT ); Mon, 3 Aug 2020 17:01:53 -0400 Received: by mail-il1-f194.google.com with SMTP id p16so21556272ile.0; Mon, 03 Aug 2020 14:01:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=saXc7GUoDkesF20I7UFsdi9hPtbZ6gcBdE2OHbCMpCA=; b=AeuRLWSgFcKQKmcANc4PQpwnG/FfjVS5DBAAZmtpNLJ2Lz2mTjil0TYg78nbYTcf1c PBCRbI4wkh8CDQuvRQm5vwU8KNy0g6Uvw4ajb9GgJoRdiRN/z3d9q/wyw81CxC2PJAXe 6SKg4I2awpPeU669tvQW6/jZLaqzDfO+zI4A93vQ+K9p6ZEYrIqL+A8U94ixzGxfzlo4 /qeF5z0Ql/truWgtft41t+ZIBYK5nplUtDy7vp2LIvMU5nuS15h/RlyNkkldqP9JeYzz RpMSJe2VRJXZZ12AH9RaJHGxuU19CQpdnJpD73M707LV5fh56ep5wqVnAFT1PGCipylL 6k9A== X-Gm-Message-State: AOAM530kyD9aBgA8kgPBFWtk/Ymwuoeg79HyUu+VzQWFbDeM8HCSGCYv h1+P37VmaH7SCDdNkxDlRA== X-Google-Smtp-Source: ABdhPJyvv0uRK79mfofQnWPAX/lrUkNhl98uSGAQALtBwC5yCmLzPHG/gk1AEvK1d658EgveC+qAIg== X-Received: by 2002:a92:d1ce:: with SMTP id u14mr1318029ilg.270.1596488511699; Mon, 03 Aug 2020 14:01:51 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:51 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 13/27] PCI: dwc: Use generic config accessors Date: Mon, 3 Aug 2020 15:01:02 -0600 Message-Id: <20200803210116.3132633-14-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that all the platforms with custom config access handling define their own pci_ops, let's split the default config accessors to use different pci_ops for root and child buses. With this, we can use the generic config accessors. The child bus accesses mainly require a .map_bus() hook to reconfigure the iATU on each config space access. BTW, if there are only 2 viewports which means config space and I/O accesses are mutually exclusive because the iATU window is shared, how are accesses serialized? That seems broken... Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 120 ++++++------------ 1 file changed, 42 insertions(+), 78 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 6e9f106e8e05..e9778f8ee955 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -20,24 +20,7 @@ #include "pcie-designware.h" static struct pci_ops dw_pcie_ops; - -static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, - u32 *val) -{ - struct dw_pcie *pci; - - pci = to_dw_pcie_from_pp(pp); - return dw_pcie_read(pci->dbi_base + where, size, val); -} - -static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, - u32 val) -{ - struct dw_pcie *pci; - - pci = to_dw_pcie_from_pp(pp); - return dw_pcie_write(pci->dbi_base + where, size, val); -} +static struct pci_ops dw_child_pcie_ops; static void dw_msi_ack_irq(struct irq_data *d) { @@ -448,7 +431,7 @@ int dw_pcie_host_init(struct pcie_port *pp) /* Set default bus ops */ bridge->ops = &dw_pcie_ops; - bridge->child_ops = &dw_pcie_ops; + bridge->child_ops = &dw_child_pcie_ops; if (pp->ops->host_init) { ret = pp->ops->host_init(pp); @@ -498,14 +481,14 @@ void dw_pcie_host_deinit(struct pcie_port *pp) } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); -static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val, - bool write) +static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, + unsigned int devfn, int where) { - int ret, type; + int type; u32 busdev, cfg_size; u64 cpu_addr; void __iomem *va_cfg_base; + struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | @@ -526,79 +509,59 @@ static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus, dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, type, cpu_addr, busdev, cfg_size); - if (write) - ret = dw_pcie_write(va_cfg_base + where, size, *val); - else - ret = dw_pcie_read(va_cfg_base + where, size, val); - if (pci->num_viewport <= 2) - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, - PCIE_ATU_TYPE_IO, pp->io_base, - pp->io_bus_addr, pp->io_size); - - return ret; -} - -static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 *val) -{ - return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val, - false); + return va_cfg_base + where; } -static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, - u32 devfn, int where, int size, u32 val) -{ - return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val, - true); -} - -static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus, - int dev) +static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) { + int ret; + struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - /* If there is no link, then there is no device */ - if (bus->number != pp->root_bus_nr) { - if (!dw_pcie_link_up(pci)) - return 0; - } + ret = pci_generic_config_read(bus, devfn, where, size, val); - /* Access only one slot on each root port */ - if (bus->number == pp->root_bus_nr && dev > 0) - return 0; + if (!ret && pci->num_viewport <= 2) + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, pp->io_base, + pp->io_bus_addr, pp->io_size); - return 1; + return ret; } -static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, - int size, u32 *val) +static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) { + int ret; struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) { - *val = 0xffffffff; - return PCIBIOS_DEVICE_NOT_FOUND; - } + ret = pci_generic_config_write(bus, devfn, where, size, val); - if (bus->number == pp->root_bus_nr) - return dw_pcie_rd_own_conf(pp, where, size, val); + if (!ret && pci->num_viewport <= 2) + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_IO, pp->io_base, + pp->io_bus_addr, pp->io_size); - return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); + return ret; } -static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, - int where, int size, u32 val) +static struct pci_ops dw_child_pcie_ops = { + .map_bus = dw_pcie_other_conf_map_bus, + .read = dw_pcie_rd_other_conf, + .write = dw_pcie_wr_other_conf, +}; + +void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { struct pcie_port *pp = bus->sysdata; + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - if (!dw_pcie_valid_device(pp, bus, PCI_SLOT(devfn))) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (bus->number == pp->root_bus_nr) - return dw_pcie_wr_own_conf(pp, where, size, val); + if (PCI_SLOT(devfn) > 0) + return NULL; - return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); + return pci->dbi_base + where; } void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) @@ -613,8 +576,9 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, } static struct pci_ops dw_pcie_ops = { - .read = dw_pcie_rd_conf, - .write = dw_pcie_wr_conf, + .map_bus = dw_pcie_own_conf_map_bus, + .read = pci_generic_config_read, + .write = pci_generic_config_write, }; void dw_pcie_setup_rc(struct pcie_port *pp) @@ -673,7 +637,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * the platform uses its own address translation component rather than * ATU, so we should not program the ATU here. */ - if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) { + if (pp->bridge->child_ops == &dw_child_pcie_ops) { dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); From patchwork Mon Aug 3 21:01:03 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LH4sWgz9sTS for ; Tue, 4 Aug 2020 07:01:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729257AbgHCVB5 (ORCPT ); Mon, 3 Aug 2020 17:01:57 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:46757 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVB4 (ORCPT ); Mon, 3 Aug 2020 17:01:56 -0400 Received: by mail-io1-f68.google.com with SMTP id a5so24746443ioa.13; Mon, 03 Aug 2020 14:01:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aFafu+8WFYxvnK2ZfkQMV1ef4S4ilss7PqKLS2/JE9Q=; b=ipXeKRH+xqu0EHK9jtgf5Niv5ypGpvAs060+j9cftbVi4H/bRDhG4/dVGwvVx5JEuZ DI8dw9dThv7cLhacTBNq92rxLY3Qqzoh7rfMF94qLt0ZxFvI+9CllvwmSmmOfiyxrbey XSR3bKBJrznxUu0TYsNwB3gPWLoYuOjwEfokUuErIleQ5er6evK2ZczBC0MhtDIcydGY 0tpmW9/iqdtVlm5bhCpV4bTutf2+AyvM9vtv87nTcn9fLvkBTIoQNCSmY9hDepk/ZxV+ rm/7YMm/SApcwCfSmiEbTa5V91g1z66Tlxjjaxc0/D9V1WAEmj8TKwUtzTmMogD6gSMs ZS0w== X-Gm-Message-State: AOAM531oYEUOpJwzwHi58YBqEG0jGT3S7IVM90Y0Px592R0fgDjnsWv6 3rF5j1EwrwocnDZnjOd3cA== X-Google-Smtp-Source: ABdhPJwJ3HnlJnV2ngZJFyUd41+SK9bAY0gYR06YRKYq8NPItVwUmrMdWUTQ4AtFe1sC/npigxntYA== X-Received: by 2002:a5d:87c9:: with SMTP id q9mr1812686ios.113.1596488515619; Mon, 03 Aug 2020 14:01:55 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:55 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 14/27] PCI: Also call .add_bus() callback for root bus Date: Mon, 3 Aug 2020 15:01:03 -0600 Message-Id: <20200803210116.3132633-15-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Similar to pcibios_add_bus(), call pci_ops.add_bus() when the root bus is added. This allows host bridge drivers to do any setup requiring a bus pointer. There are currently no .add_bus() callbacks, so this is safe to do. Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- drivers/pci/probe.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 8712e595174d..337a3b7766ca 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -935,6 +935,12 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge) pcibios_add_bus(bus); + if (bus->ops->add_bus) { + err = bus->ops->add_bus(bus); + if (WARN_ON(err < 0)) + dev_err(&bus->dev, "failed to add bus: %d\n", err); + } + /* Create legacy_io and legacy_mem files for this bus */ pci_create_legacy_files(bus); From patchwork Mon Aug 3 21:01:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340536 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LL281Pz9sTR for ; Tue, 4 Aug 2020 07:02:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729405AbgHCVCA (ORCPT ); Mon, 3 Aug 2020 17:02:00 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:45747 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVCA (ORCPT ); Mon, 3 Aug 2020 17:02:00 -0400 Received: by mail-io1-f66.google.com with SMTP id u126so2718395iod.12; Mon, 03 Aug 2020 14:01:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+G09sVWmLiEk+qlmhnIPsi/B/n4JiVilLbMwDzTJ8Fc=; b=PaoWVWjJPXhqL4kgjd3GLb0n3DyC2PeyL+cfvdOJEGt8nunuxRHj2H5NQ9PSdaxTnM oHEeOiK1lAtlgw6N+pXTQhsFucGqIo5dC1ab+c7oyD+IIuyk96GMq4ohyLSI+YE+E5+N EyjUO165ow6j8kEUf+ZAaGTwwzkNmIOTdmzyX9cjlibmB6iSMj1ezTVwQd5lMYN1xxA9 i57z+MDAtmdkmOyFt2MYO5+A1+AokobryHc89++mOOFuajqBZIMU7jPgoj+NEZ6sg/Ql 5b03x00Gk8/Q5MhR83hg5b/IzROudK5Y0fNuIEcdJXpmlpu0s3SA51cCp8tUyE0wWJTV q6kQ== X-Gm-Message-State: AOAM530l8j86JMGgWWVQ1mB5HyjTi6Dwzga5Z8VGxyLlZdGkB8FHfvaW 82hSUIwIq+E0JBITbt6P4g== X-Google-Smtp-Source: ABdhPJwMMkdyajQxcuVfgyMatvkAGgozf6l/jhIrQdnBe0B3HLM8TfQxbxa+NUmVrm7WcBb9dbLq7Q== X-Received: by 2002:a5e:c311:: with SMTP id a17mr1821353iok.12.1596488518872; Mon, 03 Aug 2020 14:01:58 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:01:58 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 15/27] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Date: Mon, 3 Aug 2020 15:01:04 -0600 Message-Id: <20200803210116.3132633-16-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org TI keystone is the only Designware driver using .scan_bus(). This function pointer is the only thing preventing the Designware driver from using pci_host_probe(). Let's use the pci_ops.add_bus hook instead. Cc: Murali Karicheri Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index df1194d186bc..17271b21fb7d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -454,15 +454,19 @@ static struct pci_ops ks_child_pcie_ops = { }; /** - * ks_pcie_v3_65_scan_bus() - keystone scan_bus post initialization + * ks_pcie_v3_65_add_bus() - keystone add_bus post initialization * * This sets BAR0 to enable inbound access for MSI_IRQ register */ -static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) +static int ks_pcie_v3_65_add_bus(struct pci_bus *bus) { + struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + if (!pci_is_root_bus(bus)) + return 0; + /* Configure and set up BAR0 */ ks_pcie_set_dbi_mode(ks_pcie); @@ -477,12 +481,15 @@ static void ks_pcie_v3_65_scan_bus(struct pcie_port *pp) * be sufficient. Use physical address to avoid any conflicts. */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); + + return 0; } static struct pci_ops ks_pcie_ops = { .map_bus = dw_pcie_own_conf_map_bus, .read = pci_generic_config_read, .write = pci_generic_config_write, + .add_bus = ks_pcie_v3_65_add_bus, }; /** @@ -842,7 +849,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) static const struct dw_pcie_host_ops ks_pcie_host_ops = { .host_init = ks_pcie_host_init, .msi_host_init = ks_pcie_msi_host_init, - .scan_bus = ks_pcie_v3_65_scan_bus, }; static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { From patchwork Mon Aug 3 21:01:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LN3zqzz9sTK for ; Tue, 4 Aug 2020 07:02:04 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729407AbgHCVCC (ORCPT ); Mon, 3 Aug 2020 17:02:02 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:45964 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVCC (ORCPT ); Mon, 3 Aug 2020 17:02:02 -0400 Received: by mail-il1-f194.google.com with SMTP id f68so10457680ilh.12; Mon, 03 Aug 2020 14:02:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+aVzUrW/b+OR7PsyqkF7d3uV9W2kuObPvJUPmZOvAKM=; b=L5i6A4KQ9QUbLbttgLwwy/EyNetA5PHd8XPe6orXHFuIEjmU0DyNWHMrrTTZLyuc/3 HAESAL6lnpFVYomVOkkynlTU0yjh22VHQNSMPgzGySzeP+1UNyqp8hQkRUpfSHcs5SQm cg/kAeNL3EETnfYQdZrOqPE5DuKaYY+Ax+bfFd1unVrE67fqiBP7pf3pE5bH1ehtSvfl /yrODqXKyDzkFRRMsKsdq8vqGAXjTfYWXUVlSbFYMIB6Joxkar+aF+cQOzNIEgl6qAif vUPSxeoGWkuh7QiPRHBMJceSiR8QSUNeYVu+aQFnHwmorIku+4fioOLeVGtAlY05eci2 vGTQ== X-Gm-Message-State: AOAM532OQTuwBdZDCOc4x8WYphrzUUHl6avW+/rWmzj/80Z2Pm65V6kX XNELdnCiAN65Z3cl21X7vw== X-Google-Smtp-Source: ABdhPJzvMiwNh6mYspCSiLag2A19Z5Dkvf/eGkppl3qfixJbFF7IVuurRzwNE2IrpB0eB0YCgBL/0A== X-Received: by 2002:a92:c883:: with SMTP id w3mr1144796ilo.2.1596488521305; Mon, 03 Aug 2020 14:02:01 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:00 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 16/27] PCI: dwc: Convert to use pci_host_probe() Date: Mon, 3 Aug 2020 15:01:05 -0600 Message-Id: <20200803210116.3132633-17-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that there are no more .scan_bus() callbacks, we can remove it and just use pci_host_probe(). Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Signed-off-by: Rob Herring --- .../pci/controller/dwc/pcie-designware-host.c | 21 +++---------------- drivers/pci/controller/dwc/pcie-designware.h | 1 - 2 files changed, 3 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index e9778f8ee955..dc336163104a 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -300,7 +300,6 @@ int dw_pcie_host_init(struct pcie_port *pp) struct device_node *np = dev->of_node; struct platform_device *pdev = to_platform_device(dev); struct resource_entry *win; - struct pci_bus *child; struct pci_host_bridge *bridge; struct resource *cfg_res; int ret; @@ -447,23 +446,9 @@ int dw_pcie_host_init(struct pcie_port *pp) bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; - ret = pci_scan_root_bus_bridge(bridge); - if (ret) - goto err_free_msi; - - pp->root_bus = bridge->bus; - - if (pp->ops->scan_bus) - pp->ops->scan_bus(pp); - - pci_bus_size_bridges(pp->root_bus); - pci_bus_assign_resources(pp->root_bus); - - list_for_each_entry(child, &pp->root_bus->children, node) - pcie_bus_configure_settings(child); - - pci_bus_add_devices(pp->root_bus); - return 0; + ret = pci_host_probe(bridge); + if (!ret) + return 0; err_free_msi: if (pci_msi_enabled() && !pp->ops->msi_host_init) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 28e7ad3eb89f..10d22269254a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -161,7 +161,6 @@ enum dw_pcie_device_mode { struct dw_pcie_host_ops { int (*host_init)(struct pcie_port *pp); - void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); }; From patchwork Mon Aug 3 21:01:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LR2nPHz9sSt for ; Tue, 4 Aug 2020 07:02:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729414AbgHCVCF (ORCPT ); Mon, 3 Aug 2020 17:02:05 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:34380 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVCE (ORCPT ); Mon, 3 Aug 2020 17:02:04 -0400 Received: by mail-io1-f68.google.com with SMTP id q75so31850951iod.1; Mon, 03 Aug 2020 14:02:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KBszrZoR6KfV8PIUJ9TAD0pOH/WhVXS7vLHSzuibxQI=; b=ffSv2U+0W36NH6O2luIDvOWR8rQ5f6KQdv6yLauVEdpvgY9XDZhwMtgtSk9Qr6oui1 1Bibbh+6z+H2lu5/iPlIvTbwmYFWGJVMjaLaIDtpx3L/FO3F/+mF2bH5nQTBjmF5+s/K x5OK63at196Y6YSe5F6D/m/+gr9R9vDEHBvq+XU6kf4Fai7CCrBD5443gdy/cIPNbJEK fur2ALfcEFlhml8TR5JcWWTGftorAJPr185dHYAboKts7WHUNh2i93H+3dWCGrTkO6g9 avkQMcv7x7T/BRIgHFKfYpkaxXrFbQZoHEb9tTL34POm1+PInluifixn0xTDhl28nSwO cCzg== X-Gm-Message-State: AOAM5333mMj0LTHl4gN2XVM98/xarue34ziXkGv/LQwjIgiDho8ywhYV +JTrlIFgLBl0IFUjJ7eW9Q== X-Google-Smtp-Source: ABdhPJwRuSSPOninoBNPo5aHkonSJpYI9fAmTlwclA+BVNVifs96k/azUtlQrFpO1XKMGj3SdjN9iw== X-Received: by 2002:a02:c735:: with SMTP id h21mr1877476jao.90.1596488523308; Mon, 03 Aug 2020 14:02:03 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:02 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 17/27] PCI: dwc: Remove root_bus pointer Date: Mon, 3 Aug 2020 15:01:06 -0600 Message-Id: <20200803210116.3132633-18-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The pci_host_bridge struct already has a pointer to its pci_bus, so let's convert the one user to use the bridge struct and remove the private 'root_bus' pointer. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.h | 1 - drivers/pci/controller/dwc/pcie-tegra194.c | 4 ++-- 3 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index dc336163104a..9528c8b1c9ab 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -459,8 +459,8 @@ EXPORT_SYMBOL_GPL(dw_pcie_host_init); void dw_pcie_host_deinit(struct pcie_port *pp) { - pci_stop_root_bus(pp->root_bus); - pci_remove_root_bus(pp->root_bus); + pci_stop_root_bus(pp->bridge->bus); + pci_remove_root_bus(pp->bridge->bus); if (pci_msi_enabled() && !pp->ops->msi_host_init) dw_pcie_free_msi(pp); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 10d22269254a..67aac6fdca24 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -193,7 +193,6 @@ struct pcie_port { struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_mask[MAX_MSI_CTRLS]; - struct pci_bus *root_bus; struct pci_host_bridge *bridge; raw_spinlock_t lock; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 52bb145c42d1..c567c9c09ff6 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1264,9 +1264,9 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie) * 5.2 Link State Power Management (Page #428). */ - list_for_each_entry(child, &pp->root_bus->children, node) { + list_for_each_entry(child, &pp->bridge->bus->children, node) { /* Bring downstream devices to D0 if they are not already in */ - if (child->parent == pp->root_bus) { + if (child->parent == pp->bridge->bus) { root_bus = child; break; } From patchwork Mon Aug 3 21:01:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340542 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LT3hFsz9sTK for ; Tue, 4 Aug 2020 07:02:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729419AbgHCVCI (ORCPT ); Mon, 3 Aug 2020 17:02:08 -0400 Received: from mail-il1-f194.google.com ([209.85.166.194]:38541 "EHLO mail-il1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729064AbgHCVCH (ORCPT ); Mon, 3 Aug 2020 17:02:07 -0400 Received: by mail-il1-f194.google.com with SMTP id 77so3880456ilc.5; Mon, 03 Aug 2020 14:02:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xUz+R+tsBr+VP4t6lLVIS/60DtpOg9mXVRA50yAPEow=; b=LP4EQuwh8Xj3f4ySgVjcu4Y6D6rZtxq/xrustadAh7YEWME8WMtPQzLNwjK/MMpu0g n4TGcoFi08806zPBAbb9TlpJ6dtoVRjA5WPM7sVyGe9Jv4EJqHIMBkcZ1k1kOgXlDLwF T5WeaeWy0WcJAqTYVI8ERYBzJBZeRvy3ASxc90toFCcznXRMJWQFD0YGy53DC+O6/iMy huNHIbztY2WQK5hxxQKr0NYQ3Ud7ki9KVVREjJvanW2bfpBnXDKY3wBvIIIWVcoJNLVv 1mYmWFjB4ixG/snRzQHlOBImvo1sntKZJ2Z7xq+Kl3UIcc0zp/sMU/V6foJg4flviUG6 KsbA== X-Gm-Message-State: AOAM531bA2Kkivz5C6JtsAYTAQhJybW8a/ya4As1vyxNmY9Oz4DxYuvZ WEWcJ4KBUUq2v77UDK/Huw== X-Google-Smtp-Source: ABdhPJxQRC2hDazWRnHx6HVUyG/OxIUURk6yYbgjpKPr1lZXzY4+auLTp11NjAtvPj4c/6iBYyYg8Q== X-Received: by 2002:a05:6e02:14cf:: with SMTP id o15mr1329621ilk.239.1596488525559; Mon, 03 Aug 2020 14:02:05 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:04 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 18/27] PCI: dwc: Remove storing of PCI resources Date: Mon, 3 Aug 2020 15:01:07 -0600 Message-Id: <20200803210116.3132633-19-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The PCI bridge resources are stored in pci_host_bridge.windows, so there's no need to store them in a DWC specific struct. There's also no need to parse the resources and store them a 2nd time as they are mainly used for one time setup of iATU windows. Cc: Murali Karicheri Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Jonathan Chocron Cc: Jingoo Han Cc: Gustavo Pimentel Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 8 +++-- drivers/pci/controller/dwc/pcie-al.c | 7 +++-- .../pci/controller/dwc/pcie-designware-host.c | 29 ++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 6 ---- 4 files changed, 19 insertions(+), 31 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 17271b21fb7d..bdf4fe1fc822 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -400,10 +400,14 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) u32 num_viewport = ks_pcie->num_viewport; struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; - u64 start = pp->mem->start; - u64 end = pp->mem->end; + u64 start, end; + struct resource *mem; int i; + mem = resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM)->res; + start = mem->start; + end = mem->end; + /* Disable BARs for inbound access */ ks_pcie_set_dbi_mode(ks_pcie); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c index 5c5763f14485..72bf1777f264 100644 --- a/drivers/pci/controller/dwc/pcie-al.c +++ b/drivers/pci/controller/dwc/pcie-al.c @@ -265,6 +265,7 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) u8 secondary_bus; u32 cfg_control; u32 reg; + struct resource *bus = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS)->res; target_bus_cfg = &pcie->target_bus_cfg; @@ -278,13 +279,13 @@ static void al_pcie_config_prepare(struct al_pcie *pcie) target_bus_cfg->ecam_mask = ecam_bus_mask; /* This portion is taken from the cfg_target_bus reg */ target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask; - target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask; + target_bus_cfg->reg_val = bus->start & target_bus_cfg->reg_mask; al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val, target_bus_cfg->reg_mask); - secondary_bus = pp->busn->start + 1; - subordinate_bus = pp->busn->end; + secondary_bus = bus->start + 1; + subordinate_bus = bus->end; /* Set the valid values of secondary and subordinate buses */ cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9528c8b1c9ab..a981e9de81d7 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -331,17 +331,9 @@ int dw_pcie_host_init(struct pcie_port *pp) resource_list_for_each_entry(win, &bridge->windows) { switch (resource_type(win->res)) { case IORESOURCE_IO: - pp->io = win->res; - pp->io->name = "I/O"; - pp->io_size = resource_size(pp->io); - pp->io_bus_addr = pp->io->start - win->offset; - pp->io_base = pci_pio_to_address(pp->io->start); - break; - case IORESOURCE_MEM: - pp->mem = win->res; - pp->mem->name = "MEM"; - pp->mem_size = resource_size(pp->mem); - pp->mem_bus_addr = pp->mem->start - win->offset; + pp->io_size = resource_size(win->res); + pp->io_bus_addr = win->res->start - win->offset; + pp->io_base = pci_pio_to_address(win->res->start); break; case 0: pp->cfg = win->res; @@ -350,9 +342,6 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = pp->cfg->start; pp->cfg1_base = pp->cfg->start + pp->cfg0_size; break; - case IORESOURCE_BUS: - pp->busn = win->res; - break; } } @@ -366,8 +355,6 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - pp->mem_base = pp->mem->start; - if (!pp->va_cfg0_base) { pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, pp->cfg0_base, pp->cfg0_size); @@ -438,8 +425,6 @@ int dw_pcie_host_init(struct pcie_port *pp) goto err_free_msi; } - pp->root_bus_nr = pp->busn->start; - bridge->dev.parent = dev; bridge->sysdata = pp; bridge->busnr = pp->root_bus_nr; @@ -623,9 +608,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * ATU, so we should not program the ATU here. */ if (pp->bridge->child_ops == &dw_child_pcie_ops) { + struct resource_entry *entry = + resource_list_first_type(&pp->bridge->windows, IORESOURCE_MEM); + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, - PCIE_ATU_TYPE_MEM, pp->mem_base, - pp->mem_bus_addr, pp->mem_size); + PCIE_ATU_TYPE_MEM, entry->res->start, + entry->res->start - entry->offset, + resource_size(entry->res)); if (pci->num_viewport > 2) dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX2, PCIE_ATU_TYPE_IO, pp->io_base, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 67aac6fdca24..3d552ec8a850 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -176,13 +176,7 @@ struct pcie_port { resource_size_t io_base; phys_addr_t io_bus_addr; u32 io_size; - u64 mem_base; - phys_addr_t mem_bus_addr; - u32 mem_size; struct resource *cfg; - struct resource *io; - struct resource *mem; - struct resource *busn; int irq; const struct dw_pcie_host_ops *ops; int msi_irq; From patchwork Mon Aug 3 21:01:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340543 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LV3Yjdz9sTR for ; Tue, 4 Aug 2020 07:02:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729422AbgHCVCJ (ORCPT ); Mon, 3 Aug 2020 17:02:09 -0400 Received: from mail-il1-f196.google.com ([209.85.166.196]:44555 "EHLO mail-il1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729421AbgHCVCJ (ORCPT ); Mon, 3 Aug 2020 17:02:09 -0400 Received: by mail-il1-f196.google.com with SMTP id j9so28945699ilc.11; Mon, 03 Aug 2020 14:02:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A5ZRdGbgMokbNA9oTRazmcvFgPKDBEIf6TFNg0ak5Ts=; b=qZxKoT1foi+uSuk53LfhPqd0EzhI03llostbNQYWNZwVJzHEURc8eEWEgCcWk3vpVs QAB72IsVN5kD/TPQtpIMR4NAW9t2o6lhNHvcyDHGiDloKEKVWeG7tZOp9RNGeM6g5Ner z/SpCSBseHzx4xYYzpU4zqR5/sKfp6E4TaS/atCq2Mh0qtlixJbRyU5QrNKp3g7AP+LI WsvyMq1/I7BCgoZzrurHU9xpk8daet8XBnOJYOCVGYSyT8W5CCj1PhJmVT/Ht7whpOiF TEbsGGwkgdW/WpCm/f+/qrKT4X2jqj75Fbs0wwL/TKfdux0xsRcJYRXKMBzPCmSJZGaB zEuA== X-Gm-Message-State: AOAM533dwSYEPHD03rg1fm1YygA9gpfb7vEJdiYY6qXTEnXypa86Jq0I kFMacaCy9AQlDlEXTdoQ2g== X-Google-Smtp-Source: ABdhPJw9hQJvyqAcDIO3UaEmiIOveBESyqnRHcwOtmBQyXK9HRW5j6bU0VVQqY+1zy8sjr3lVihj5w== X-Received: by 2002:a92:660e:: with SMTP id a14mr1369453ilc.290.1596488527825; Mon, 03 Aug 2020 14:02:07 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:07 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 19/27] PCI: dwc: Simplify config space handling Date: Mon, 3 Aug 2020 15:01:08 -0600 Message-Id: <20200803210116.3132633-20-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The config space is divided in half for type 0 and type 1 accesses, but this is pointless as there's only one iATU window which is reconfigured on each access. The only platform doing something custom is TI Keystone (surprise!). It does its own mapping of the config space to avoid spliting the config space and never actually uses va_cfg1_base as it has its own config space accessors. With the splitting removed, Keystone can use the default mapping of config space. Cc: Murali Karicheri Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Jingoo Han Cc: Gustavo Pimentel Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 8 --- .../pci/controller/dwc/pcie-designware-host.c | 63 ++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 4 -- 3 files changed, 20 insertions(+), 55 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index bdf4fe1fc822..e9028c98d6c0 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -873,16 +873,8 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; - struct resource *res; int ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); - pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); - - pp->va_cfg1_base = pp->va_cfg0_base; - ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index a981e9de81d7..1ff4702595b6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -308,10 +308,8 @@ int dw_pcie_host_init(struct pcie_port *pp) cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (cfg_res) { - pp->cfg0_size = resource_size(cfg_res) >> 1; - pp->cfg1_size = resource_size(cfg_res) >> 1; + pp->cfg0_size = resource_size(cfg_res); pp->cfg0_base = cfg_res->start; - pp->cfg1_base = cfg_res->start + pp->cfg0_size; } else if (!pp->va_cfg0_base) { dev_err(dev, "Missing *config* reg space\n"); } @@ -336,25 +334,22 @@ int dw_pcie_host_init(struct pcie_port *pp) pp->io_base = pci_pio_to_address(win->res->start); break; case 0: - pp->cfg = win->res; - pp->cfg0_size = resource_size(pp->cfg) >> 1; - pp->cfg1_size = resource_size(pp->cfg) >> 1; - pp->cfg0_base = pp->cfg->start; - pp->cfg1_base = pp->cfg->start + pp->cfg0_size; + dev_err(dev, "Missing *config* reg space\n"); + pp->cfg0_size = resource_size(win->res); + pp->cfg0_base = win->res->start; + if (!pci->dbi_base) { + pci->dbi_base = devm_pci_remap_cfgspace(dev, + pp->cfg0_base, + pp->cfg0_size); + if (!pci->dbi_base) { + dev_err(dev, "Error with ioremap\n"); + return -ENOMEM; + } + } break; } } - if (!pci->dbi_base) { - pci->dbi_base = devm_pci_remap_cfgspace(dev, - pp->cfg->start, - resource_size(pp->cfg)); - if (!pci->dbi_base) { - dev_err(dev, "Error with ioremap\n"); - return -ENOMEM; - } - } - if (!pp->va_cfg0_base) { pp->va_cfg0_base = devm_pci_remap_cfgspace(dev, pp->cfg0_base, pp->cfg0_size); @@ -364,16 +359,6 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - if (!pp->va_cfg1_base) { - pp->va_cfg1_base = devm_pci_remap_cfgspace(dev, - pp->cfg1_base, - pp->cfg1_size); - if (!pp->va_cfg1_base) { - dev_err(dev, "Error with ioremap\n"); - return -ENOMEM; - } - } - ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport); if (ret) pci->num_viewport = 2; @@ -455,32 +440,24 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) { int type; - u32 busdev, cfg_size; - u64 cpu_addr; - void __iomem *va_cfg_base; + u32 busdev; struct pcie_port *pp = bus->sysdata; struct dw_pcie *pci = to_dw_pcie_from_pp(pp); busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | PCIE_ATU_FUNC(PCI_FUNC(devfn)); - if (bus->parent->number == pp->root_bus_nr) { + if (bus->parent->number == pp->root_bus_nr) type = PCIE_ATU_TYPE_CFG0; - cpu_addr = pp->cfg0_base; - cfg_size = pp->cfg0_size; - va_cfg_base = pp->va_cfg0_base; - } else { + else type = PCIE_ATU_TYPE_CFG1; - cpu_addr = pp->cfg1_base; - cfg_size = pp->cfg1_size; - va_cfg_base = pp->va_cfg1_base; - } + dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1, - type, cpu_addr, - busdev, cfg_size); + type, pp->cfg0_size, + busdev, pp->cfg0_size); - return va_cfg_base + where; + return pp->va_cfg0_base + where; } static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 3d552ec8a850..2db6f52dfe81 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -170,13 +170,9 @@ struct pcie_port { u64 cfg0_base; void __iomem *va_cfg0_base; u32 cfg0_size; - u64 cfg1_base; - void __iomem *va_cfg1_base; - u32 cfg1_size; resource_size_t io_base; phys_addr_t io_bus_addr; u32 io_size; - struct resource *cfg; int irq; const struct dw_pcie_host_ops *ops; int msi_irq; From patchwork Mon Aug 3 21:01:09 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340546 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9LY6rN5z9sTX for ; Tue, 4 Aug 2020 07:02:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729429AbgHCVCM (ORCPT ); Mon, 3 Aug 2020 17:02:12 -0400 Received: from mail-io1-f66.google.com ([209.85.166.66]:46785 "EHLO mail-io1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729421AbgHCVCL (ORCPT ); Mon, 3 Aug 2020 17:02:11 -0400 Received: by mail-io1-f66.google.com with SMTP id a5so24747179ioa.13; Mon, 03 Aug 2020 14:02:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TMmKGLqxoIiv5nH6EL2xp/hSv/Gz0ReZ5qtRf7b9+lE=; b=OGoWRMwxyC0QG6kO81r6XWFPwqO1jIZDeKowVnEEw+v/njlDA32MwI2PfpR5UM7NUz mIlg7i/KzpeWjKgwQdvjfqFFsbzh+fdGnEPE1B3NfHnXM1AKSgiJ+WWXAiT/4s0kA2/E nFwL5+hzjmv2hZS0CQTVDvv2yRSfQPj0WerLc5iATxdWRjxuuB9cGr7ROtiJS8CJXXo0 LpVgtKSGpOI57NCP67CeTANtvGUmYThU+rn4UW9uhG4DwRk7fB2oVRVYv6s0N3IjUfP8 ymc/Ytpwu6aaKvJZ7y6T0vTROzBBx8XKaWbNNpZxVYNKgnTH1CXpaj5NtVvj4cq2/KBO anNg== X-Gm-Message-State: AOAM532axCo+eTiu4iI1DhEnysoz/ZfUK+IuVm33WqnQMZOxBfRS9DhF WlCEoFplw5Ng7PGC2g9+yQ== X-Google-Smtp-Source: ABdhPJxeiUiiXL4Rua4Fu69Vg+K0w1bnYWMxWGlLFPHzRqQHvNY5emITrazErXZ1fYfEY9jR9WKX5A== X-Received: by 2002:a05:6638:1005:: with SMTP id r5mr1866400jab.116.1596488530148; Mon, 03 Aug 2020 14:02:10 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:09 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 20/27] PCI: dwc/keystone: Drop duplicated 'num-viewport' Date: Mon, 3 Aug 2020 15:01:09 -0600 Message-Id: <20200803210116.3132633-21-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The DWC core driver already parses and stores the 'num-viewport' DT property, so there is no need for the Keystone driver to store it. Cc: Murali Karicheri Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-keystone.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e9028c98d6c0..205754a6bc3c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -123,7 +123,6 @@ struct keystone_pcie { int msi_host_irq; int num_lanes; - u32 num_viewport; struct phy **phy; struct device_link **link; struct device_node *msi_intc_np; @@ -397,9 +396,9 @@ static void ks_pcie_clear_dbi_mode(struct keystone_pcie *ks_pcie) static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { u32 val; - u32 num_viewport = ks_pcie->num_viewport; struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; + u32 num_viewport = pci->num_viewport; u64 start, end; struct resource *mem; int i; @@ -1199,7 +1198,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct resource *res; unsigned int version; void __iomem *base; - u32 num_viewport; struct phy **phy; int link_speed; u32 num_lanes; @@ -1352,12 +1350,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - ret = of_property_read_u32(np, "num-viewport", &num_viewport); - if (ret < 0) { - dev_err(dev, "unable to read *num-viewport* property\n"); - goto err_get_sync; - } - /* * "Power Sequencing and Reset Signal Timings" table in * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 @@ -1371,7 +1363,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) gpiod_set_value_cansleep(gpiod, 1); } - ks_pcie->num_viewport = num_viewport; pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) From patchwork Mon Aug 3 21:01:10 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Lg4ddJz9sTK for ; Tue, 4 Aug 2020 07:02:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729453AbgHCVCS (ORCPT ); Mon, 3 Aug 2020 17:02:18 -0400 Received: from mail-il1-f196.google.com ([209.85.166.196]:41451 "EHLO mail-il1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729421AbgHCVCP (ORCPT ); Mon, 3 Aug 2020 17:02:15 -0400 Received: by mail-il1-f196.google.com with SMTP id c16so20531153ils.8; Mon, 03 Aug 2020 14:02:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4tVnhS6O+K590csRd4/lSa2PYfRPYOAvm58gPgPLsFY=; b=evvNIFAW0o50ANfN2d5JvFz8cvW8j7I4oaXsj232Lq6ZKZDOzFZ8Awm0TNXJTTfnRO igJ3457wNYfzZ/XtvBNOaxfnEmQD1o2FInR+bLQ/3BPPZkhtF3V/aFQS9Ywauw3yUw8g HFlObAFW7I6WPYYYVZSjujqwTaxDLdLawy91pkezIQMk70YFd7nUVui3fcYTdhpmyx5B ekPvWv5pG57ytZFmag3lkyhkCY/ikgmV89Gu/si0zcv7RJJ7aj8bf3lYYMDpgf1QX8bI iGqvLYS8Fi9z/tONIAww5y+xO8xxOKI/Szo/fCV4yDjlKdoUGnorehibbYMxESCGhNjX HjGw== X-Gm-Message-State: AOAM5330oh/pWYnxZrOfwxKs7Lxmmb4xEeEr8dpnn+VzM50GR6kdtagP wmm2p/NXpUA7QPU1tr4KZA== X-Google-Smtp-Source: ABdhPJxrPD8UFPm240Z1CyA8Fd4/vL+RyL0sOj2CDP3xiqnUbs/cuHBijh90alAfV3wjw6im7IrWBQ== X-Received: by 2002:a92:999a:: with SMTP id t26mr1365750ilk.145.1596488533931; Mon, 03 Aug 2020 14:02:13 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:13 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Andy Gross Subject: [RFC 21/27] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Date: Mon, 3 Aug 2020 15:01:10 -0600 Message-Id: <20200803210116.3132633-22-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Move the IS_ENABLED(CONFIG_PCI_MSI) check into dw_pcie_msi_init() instead of duplicating it in all the drivers. Cc: Richard Zhu Cc: Lucas Stach Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Yue Wang Cc: Kevin Hilman Cc: Jesper Nilsson Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Xiaowei Song Cc: Binghui Wang Cc: Stanimir Varbanov Cc: Andy Gross Cc: Bjorn Andersson Cc: Kunihiko Hayashi Cc: Masahiro Yamada Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@axis.com Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-imx6.c | 4 +--- drivers/pci/controller/dwc/pci-meson.c | 8 +------- drivers/pci/controller/dwc/pcie-artpec6.c | 11 +---------- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware-plat.c | 4 +--- drivers/pci/controller/dwc/pcie-histb.c | 4 +--- drivers/pci/controller/dwc/pcie-kirin.c | 4 +--- drivers/pci/controller/dwc/pcie-qcom.c | 4 +--- drivers/pci/controller/dwc/pcie-uniphier.c | 3 +-- 9 files changed, 11 insertions(+), 34 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 8f08ae53f53e..7b526f4f85ce 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -847,9 +847,7 @@ static int imx6_pcie_host_init(struct pcie_port *pp) imx6_setup_phy_mpll(imx6_pcie); dw_pcie_setup_rc(pp); imx6_pcie_establish_link(imx6_pcie); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index 54ce3369d963..cbde683d107f 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -377,12 +377,6 @@ static int meson_pcie_establish_link(struct meson_pcie *mp) return dw_pcie_wait_for_link(pci); } -static void meson_pcie_enable_interrupts(struct meson_pcie *mp) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(&mp->pci.pp); -} - static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) { @@ -466,7 +460,7 @@ static int meson_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - meson_pcie_enable_interrupts(mp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index 28d5a1095200..969f217c5675 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -346,15 +346,6 @@ static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie) usleep_range(100, 200); } -static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie) -{ - struct dw_pcie *pci = artpec6_pcie->pci; - struct pcie_port *pp = &pci->pp; - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); -} - static int artpec6_pcie_host_init(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -368,7 +359,7 @@ static int artpec6_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); artpec6_pcie_establish_link(pci); dw_pcie_wait_for_link(pci); - artpec6_pcie_enable_interrupts(artpec6_pcie); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 1ff4702595b6..0e62bed7f6cb 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -276,6 +276,9 @@ void dw_pcie_msi_init(struct pcie_port *pp) struct device *dev = pci->dev; u64 msi_target; + if (!IS_ENABLED(CONFIG_PCI_MSI)) + return; + pp->msi_page = alloc_page(GFP_KERNEL); pp->msi_data = dma_map_page(dev, pp->msi_page, 0, PAGE_SIZE, DMA_FROM_DEVICE); diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 73646b677aff..4990cd010983 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -39,9 +39,7 @@ static int dw_plat_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); dw_pcie_wait_for_link(pci); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c index 0d93088deea3..c97c37c6314e 100644 --- a/drivers/pci/controller/dwc/pcie-histb.c +++ b/drivers/pci/controller/dwc/pcie-histb.c @@ -202,9 +202,7 @@ static int histb_pcie_host_init(struct pcie_port *pp) pp->bridge->ops = &histb_pci_ops; histb_pcie_establish_link(pp); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c index 1680dc72b416..0be17db42f56 100644 --- a/drivers/pci/controller/dwc/pcie-kirin.c +++ b/drivers/pci/controller/dwc/pcie-kirin.c @@ -434,9 +434,7 @@ static int kirin_pcie_host_init(struct pcie_port *pp) pp->bridge->ops = &kirin_pci_ops; kirin_pcie_establish_link(pp); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 138e1a2d21cc..9f1d3ba686fa 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1237,9 +1237,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp) } dw_pcie_setup_rc(pp); - - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); qcom_ep_reset_deassert(pcie); diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c index a5401a0b1e58..07ba2d833941 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier.c +++ b/drivers/pci/controller/dwc/pcie-uniphier.c @@ -322,8 +322,7 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) if (ret) return ret; - if (IS_ENABLED(CONFIG_PCI_MSI)) - dw_pcie_msi_init(pp); + dw_pcie_msi_init(pp); return 0; } From patchwork Mon Aug 3 21:01:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Lh3SnFz9sTR for ; Tue, 4 Aug 2020 07:02:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729102AbgHCVCT (ORCPT ); Mon, 3 Aug 2020 17:02:19 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:45789 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVCS (ORCPT ); Mon, 3 Aug 2020 17:02:18 -0400 Received: by mail-io1-f65.google.com with SMTP id u126so2719389iod.12; Mon, 03 Aug 2020 14:02:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yeVh4LY4Ol0sFEbqSsJcffa7f//z27paKHgfSp0xtxI=; b=PRxnPLGjDqHtLZhyyfH0d3hVBWgx6ENJDH2v8rbBdzDz8WvI2bv3DxRsayKghBvaLr et58lDEMVgpvs9peb7FXlDYGNJpHfz6VTdjV5cf3Ktqy5XhITlEQ15Cdwg/vfhg6bBWC KKN/aeiPF54OSzB9/qiQLjGrONIKjt5BupoGzFkujXOo7y4Q318vSuxKWVVaFyeRP8Ce c3rnc6e2fYknq2FcW75uu9Txm8LZ8fslt2H4nAJhP30/gVRjrAelNGdRCfJ7+AUq7vOK 3Mx5px8snzwGRqyw6/PRk+hDSC9kZ6K4N+Dj/EerPkIm5RJTx18LN40CMy+VVlIjZzLm 0SkA== X-Gm-Message-State: AOAM532dXE+PdD82jUDZ0HDBO2ET4azXc2YfWsOQAEHh8lgklpbDm26H ptF4uHxeQEbkNywjVr7ybA== X-Google-Smtp-Source: ABdhPJxHdYdH6fpt0x+gUcwdUAm9TdIxKmfEPs100vcr5aCcB5zinD7L8bd5gBFg5DUxhkQoFWaU1g== X-Received: by 2002:a5e:c30f:: with SMTP id a15mr1845040iok.184.1596488537676; Mon, 03 Aug 2020 14:02:17 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:17 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 22/27] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Date: Mon, 3 Aug 2020 15:01:11 -0600 Message-Id: <20200803210116.3132633-23-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org PCIE_LINK_WIDTH_SPEED_CONTROL is already defined in pcie-designware.h, so remove it from the i.MX6 driver. Cc: Richard Zhu Cc: Lucas Stach Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-imx6.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 7b526f4f85ce..64e694f04dce 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -116,8 +116,6 @@ struct imx6_pcie { #define PCIE_PHY_STAT (PL_OFFSET + 0x110) #define PCIE_PHY_STAT_ACK BIT(16) -#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C - /* PHY registers (not memory-mapped) */ #define PCIE_PHY_ATEOVRD 0x10 #define PCIE_PHY_ATEOVRD_EN BIT(2) From patchwork Mon Aug 3 21:01:12 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340551 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Ln0qJvz9sTK for ; Tue, 4 Aug 2020 07:02:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729463AbgHCVCY (ORCPT ); Mon, 3 Aug 2020 17:02:24 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:33153 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729103AbgHCVCW (ORCPT ); Mon, 3 Aug 2020 17:02:22 -0400 Received: by mail-io1-f65.google.com with SMTP id g14so2509436iom.0; Mon, 03 Aug 2020 14:02:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bEN9vVsE3mU2Nyqo3uVsRwOE6mBebuJzlr8xG6a6d4M=; b=gvlZ85rNLI4mgSE7YxG4Q0KiemuST2J48lyVHCiY+PD/HkVNhJJeVF9iNU9j+8IQmA m7RZlm8jqvU/xvqtd9qXD3jCxIEGFPXJ215cUFJZfmk7q85O+SWGeLcYhRozUKOQB20E 3lypsIO/PIMIq6wFTTqsMH8smaBVIeAccdeOcp1p34QjkYuYMDjxMW/QhzyQ/aFpV+zs BcIdQWmrsFL08Tj8HKJ5T9IntAeb0VAgtM72j92rAc0ek4lZBlfUIR4zVOJT0xudrgrI ggu+PN1ng44B7cXiAICRF/sdUdyK8LwW5IllpxmaZ/yMl3XwfymoyW80U2tB3qWjQViJ 6Fow== X-Gm-Message-State: AOAM532rDbMpmjaGbpD+D13MkBENq9zkSYqmBgywDILaw+rD5kp1SKuA HVVY1x77VoWi1WEwiT7ong== X-Google-Smtp-Source: ABdhPJzc5blExyVY0xBSjialU7rbyHIo6WdVKug3iv8C/bQYaB+qRckTphLyP0HPoPp/7SDACilwzg== X-Received: by 2002:a02:a584:: with SMTP id b4mr1758886jam.68.1596488541762; Mon, 03 Aug 2020 14:02:21 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:21 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 23/27] PCI: dwc/meson: Drop unnecessary RC config space initialization Date: Mon, 3 Aug 2020 15:01:12 -0600 Message-Id: <20200803210116.3132633-24-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The common Designware init already initializes the RC PCI_COMMAND, BAR0 and BAR1 registers. The only difference here is the common code sets SERR. If clearing SERR is what's desired, then the Meson driver should do that instead. Cc: Yue Wang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Kevin Hilman Cc: linux-pci@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-meson.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index cbde683d107f..d1cfc65f0a69 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -34,15 +34,6 @@ #define NUM_OF_LANES_X1 BIT(8) #define DIRECT_SPEED_CHANGE BIT(17) -#define TYPE1_HDR_OFFSET 0x0 -#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04) -#define PCI_IO_EN BIT(0) -#define PCI_MEM_SPACE_EN BIT(1) -#define PCI_BUS_MASTER_EN BIT(2) - -#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10) -#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14) - #define PCIE_CAP_OFFSET 0x70 #define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) #define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) @@ -303,9 +294,6 @@ static void meson_pcie_init_dw(struct meson_pcie *mp) val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE; meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); - - meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0); - meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1); } static int meson_size_to_payload(struct meson_pcie *mp, int size) @@ -353,13 +341,6 @@ static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); } -static inline void meson_enable_memory_space(struct meson_pcie *mp) -{ - /* Set the RC Bus Master, Memory Space and I/O Space enables */ - meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN, - PCIE_STATUS_COMMAND); -} - static int meson_pcie_establish_link(struct meson_pcie *mp) { struct dw_pcie *pci = &mp->pci; @@ -370,7 +351,6 @@ static int meson_pcie_establish_link(struct meson_pcie *mp) meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE); dw_pcie_setup_rc(pp); - meson_enable_memory_space(mp); meson_pcie_assert_reset(mp); From patchwork Mon Aug 3 21:01:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340554 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Lt4WPvz9sTK for ; Tue, 4 Aug 2020 07:02:30 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729468AbgHCVC3 (ORCPT ); Mon, 3 Aug 2020 17:02:29 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:35000 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVC1 (ORCPT ); Mon, 3 Aug 2020 17:02:27 -0400 Received: by mail-io1-f68.google.com with SMTP id s189so32774718iod.2; Mon, 03 Aug 2020 14:02:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PM8zrR6BXOfDRWMk7IOmZATjTEqDEPOnq1HMPd0fm+I=; b=Pth5GiV2sgoMtDvU2E4+9rNu7QJOQZUekMh3rDsA8pW6bM0JolDGZZr+g799xUvu9/ /2LM0bbqqfFODyPdR+6eZBVjWP/gk4FW37w6MUFrupXG2wmrRrg4k+XQcADoGdLmHHUN GsOEIO1z1xBwq4FXVFC0uRRO8K/qiy+OKD3q7+X+9iTIv6LTTWLIlTs8RbxMFyJ30bKX RyaDp8hpQDuI/UoquvTYtzf3fzUMOY2naCc9kmSvcsjtou6S+ULgC/KXD/IP5gLdtfWK NiLkVhFAYqL9vvL/gFLo4CC0BhMU1hgVj80G4F1tmWudYO4idbyyCiE0GKCez7aZ62eR 80pw== X-Gm-Message-State: AOAM530UjJ5dl0/7cC2WG4lNn33pQ+3feEVsh3guR39+6ikoiepvAwD9 RmmfX8zVWX8FxUdp86kwVQ== X-Google-Smtp-Source: ABdhPJw96k8lyNK11/NlxPpmp4xlor/b3WWjFcRtY1Ld3dnCdpoOVounuLgtCLR+q/EA7hpBdE6Lnw== X-Received: by 2002:a05:6638:1690:: with SMTP id f16mr1826708jat.91.1596488544963; Mon, 03 Aug 2020 14:02:24 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:24 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 24/27] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Date: Mon, 3 Aug 2020 15:01:13 -0600 Message-Id: <20200803210116.3132633-25-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The meson 'elbi' registers are just the Designware 'dbi' space and all the registers accessed are either standard PCI config space or DWC port logic registers. Convert the accesses to use the common defines and register accessors. Cc: Yue Wang Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Kevin Hilman Cc: Jingoo Han Cc: Gustavo Pimentel Cc: linux-pci@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-meson.c | 113 +++++++------------ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 39 insertions(+), 75 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-meson.c b/drivers/pci/controller/dwc/pci-meson.c index d1cfc65f0a69..734aace62173 100644 --- a/drivers/pci/controller/dwc/pci-meson.c +++ b/drivers/pci/controller/dwc/pci-meson.c @@ -22,23 +22,7 @@ #define to_meson_pcie(x) dev_get_drvdata((x)->dev) -/* External local bus interface registers */ -#define PLR_OFFSET 0x700 -#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10) -#define FAST_LINK_MODE BIT(7) -#define LINK_CAPABLE_MASK GENMASK(21, 16) -#define LINK_CAPABLE_X1 BIT(16) - -#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c) -#define NUM_OF_LANES_MASK GENMASK(12, 8) -#define NUM_OF_LANES_X1 BIT(8) -#define DIRECT_SPEED_CHANGE BIT(17) - -#define PCIE_CAP_OFFSET 0x70 -#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08) -#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5) #define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5) -#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12) #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12) /* PCIe specific config registers */ @@ -68,11 +52,6 @@ enum pcie_data_rate { PCIE_GEN4 }; -struct meson_pcie_mem_res { - void __iomem *elbi_base; - void __iomem *cfg_base; -}; - struct meson_pcie_clk_res { struct clk *clk; struct clk *port_clk; @@ -86,7 +65,7 @@ struct meson_pcie_rc_reset { struct meson_pcie { struct dw_pcie pci; - struct meson_pcie_mem_res mem_res; + void __iomem *cfg_base; struct meson_pcie_clk_res clk_res; struct meson_pcie_rc_reset mrst; struct gpio_desc *reset_gpio; @@ -125,28 +104,18 @@ static int meson_pcie_get_resets(struct meson_pcie *mp) return 0; } -static void __iomem *meson_pcie_get_mem(struct platform_device *pdev, - struct meson_pcie *mp, - const char *id) -{ - struct device *dev = mp->pci.dev; - struct resource *res; - - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id); - - return devm_ioremap_resource(dev, res); -} - static int meson_pcie_get_mems(struct platform_device *pdev, struct meson_pcie *mp) { - mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi"); - if (IS_ERR(mp->mem_res.elbi_base)) - return PTR_ERR(mp->mem_res.elbi_base); + struct dw_pcie *pci = &mp->pci; - mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg"); - if (IS_ERR(mp->mem_res.cfg_base)) - return PTR_ERR(mp->mem_res.cfg_base); + pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi"); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); + if (IS_ERR(mp->cfg_base)) + return PTR_ERR(mp->cfg_base); return 0; } @@ -244,24 +213,14 @@ static int meson_pcie_probe_clocks(struct meson_pcie *mp) return 0; } -static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg) -{ - writel(val, mp->mem_res.elbi_base + reg); -} - -static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg) -{ - return readl(mp->mem_res.elbi_base + reg); -} - static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg) { - return readl(mp->mem_res.cfg_base + reg); + return readl(mp->cfg_base + reg); } static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg) { - writel(val, mp->mem_res.cfg_base + reg); + writel(val, mp->cfg_base + reg); } static void meson_pcie_assert_reset(struct meson_pcie *mp) @@ -273,27 +232,28 @@ static void meson_pcie_assert_reset(struct meson_pcie *mp) static void meson_pcie_init_dw(struct meson_pcie *mp) { + struct dw_pcie *pci = &mp->pci; u32 val; val = meson_cfg_readl(mp, PCIE_CFG0); val |= APP_LTSSM_ENABLE; meson_cfg_writel(mp, val, PCIE_CFG0); - val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF); - val &= ~(LINK_CAPABLE_MASK | FAST_LINK_MODE); - meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val &= ~(PORT_LINK_MODE_MASK | PORT_LINK_FAST_LINK_MODE); + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF); - val |= LINK_CAPABLE_X1; - meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL); + val |= PORT_LINK_MODE_1_LANES; + dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); - val &= ~NUM_OF_LANES_MASK; - meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_LINK_WIDTH_MASK; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); - val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF); - val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE; - meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val |= PORT_LOGIC_LINK_WIDTH_1_LANES | PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); } static int meson_size_to_payload(struct meson_pcie *mp, int size) @@ -315,30 +275,34 @@ static int meson_size_to_payload(struct meson_pcie *mp, int size) static void meson_set_max_payload(struct meson_pcie *mp, int size) { + struct dw_pcie *pci = &mp->pci; u32 val; + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int max_payload_size = meson_size_to_payload(mp, size); - val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); - val &= ~PCIE_CAP_MAX_PAYLOAD_MASK; - meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); + val &= ~PCI_EXP_DEVCTL_PAYLOAD; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); - val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size); - meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); + dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); } static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size) { + struct dw_pcie *pci = &mp->pci; u32 val; + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int max_rd_req_size = meson_size_to_payload(mp, size); - val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); - val &= ~PCIE_CAP_MAX_READ_REQ_MASK; - meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); + val &= ~PCI_EXP_DEVCTL_READRQ; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); - val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL); val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size); - meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS); + dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val); } static int meson_pcie_establish_link(struct meson_pcie *mp) @@ -466,7 +430,6 @@ static int meson_add_pcie_port(struct meson_pcie *mp, } pp->ops = &meson_pcie_host_ops; - pci->dbi_base = mp->mem_res.elbi_base; ret = dw_pcie_host_init(pp); if (ret) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 2db6f52dfe81..b18a9a5f48d2 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -36,6 +36,7 @@ #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_DLL_LINK_EN BIT(5) +#define PORT_LINK_FAST_LINK_MODE BIT(7) #define PORT_LINK_MODE_MASK GENMASK(21, 16) #define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n) #define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1) From patchwork Mon Aug 3 21:01:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340555 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9Lw3FZRz9sSt for ; Tue, 4 Aug 2020 07:02:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729085AbgHCVCb (ORCPT ); Mon, 3 Aug 2020 17:02:31 -0400 Received: from mail-io1-f68.google.com ([209.85.166.68]:40326 "EHLO mail-io1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVCa (ORCPT ); Mon, 3 Aug 2020 17:02:30 -0400 Received: by mail-io1-f68.google.com with SMTP id l17so40001373iok.7; Mon, 03 Aug 2020 14:02:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VwFTr4t0lrmNy8f4Fgv3/l49uahHgczW7Wdy7hSwZ1w=; b=LORzLGQCc25xfattQ/r/eucxR1jhevA1boxWsnpFezxp4FAJH8zXFAS55YebAQxt49 h7OtBc4Rk3Es3JBBHnKpfKL+HGl0MiW0fDRZpCCLs1kEM/T4tdr3CviNX8FNvuWwplVw 0syBl5MkVIX8PJVjRD4ejJo7rxJ87n2tlAj8De73inJKZZvIgOFpabtSSa/btmXiVOwW 5cfjhryp9Sa5+CUY6Mee1jqIK5Ip5g8WdUvaf+UcHMhBXSvFHaoVklyZfwFpN6DfeF05 tK452SW3+4DSxiIqaGUViYGYCv0m8+KMtJcLbNJiFLOZvNX/X2f4tZyAAwxG7w8V2TUI 4x0A== X-Gm-Message-State: AOAM530dT9iH43Gsh1KoPGuU1LF4DdqnW7pOPVXRL5Iw+uEISKFI9hbG 4lWsoCqdtNi1jAa2AUaeeQ== X-Google-Smtp-Source: ABdhPJzMEhzv37+IQcarhuMxavAyD+FE8gqZIx02+KuoDY977KQ4tDj1eOPm1iwpPoPc4bKstznlOA== X-Received: by 2002:a5d:9b96:: with SMTP id r22mr1878334iom.66.1596488549634; Mon, 03 Aug 2020 14:02:29 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:29 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang , Andy Gross Subject: [RFC 25/27] PCI: dwc/qcom: Use common PCI register definitions Date: Mon, 3 Aug 2020 15:01:14 -0600 Message-Id: <20200803210116.3132633-26-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The QCom driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Cc: Stanimir Varbanov Cc: Andy Gross Cc: Bjorn Andersson Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++---------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9f1d3ba686fa..dba5f7d7f727 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -39,11 +39,6 @@ #define L23_CLK_RMV_DIS BIT(2) #define L1_CLK_RMV_DIS BIT(1) -#define PCIE20_COMMAND_STATUS 0x04 -#define CMD_BME_VAL 0x4 -#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98 -#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 - #define PCIE20_PARF_PHY_CTRL 0x40 #define PCIE20_PARF_PHY_REFCLK 0x4C #define PCIE20_PARF_DBI_BASE_ADDR 0x168 @@ -65,10 +60,6 @@ #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c #define CFG_BRIDGE_SB_INIT BIT(0) -#define PCIE20_CAP 0x70 -#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC) -#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11)) -#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14) #define PCIE_CAP_LINK1_VAL 0x2FD7F #define PCIE20_PARF_Q2A_FLUSH 0x1AC @@ -974,6 +965,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); int i, ret; u32 val; @@ -1047,16 +1039,16 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) pcie->parf + PCIE20_PARF_SYS_CTRL); writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); - writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS); + writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG); - writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1); + writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); - val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); - val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT; - writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES); + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_ASPMS; + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); - writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base + - PCIE20_DEVICE_CONTROL2_STATUS2); + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + + PCI_EXP_DEVCTL2); return 0; @@ -1209,7 +1201,8 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) static int qcom_pcie_link_up(struct dw_pcie *pci) { - u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA); + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); return !!(val & PCI_EXP_LNKSTA_DLLLA); } From patchwork Mon Aug 3 21:01:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340558 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9M04Chmz9sTK for ; Tue, 4 Aug 2020 07:02:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729103AbgHCVCe (ORCPT ); Mon, 3 Aug 2020 17:02:34 -0400 Received: from mail-il1-f195.google.com ([209.85.166.195]:42462 "EHLO mail-il1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVCe (ORCPT ); Mon, 3 Aug 2020 17:02:34 -0400 Received: by mail-il1-f195.google.com with SMTP id i138so26418165ild.9; Mon, 03 Aug 2020 14:02:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L06mAH8VA/IGeAefhzubwBSDxwj6YYC6qe74xf8W5J0=; b=uFuql2o52z3hJdVklnXHk/cwlxvZEfKGarlcVuO8vom/H5UTx8+JwICK+MHz26rnhy nAiEp7cZkZ8Bbfwob/MWu41yPuCygaSEXJ390hspWsW3rKiDFECBXfNwCIg6VBJDP2FB 1ROYjlRCrZpd9fW0O4ZFTN5cmC3BmU79isUMPKQpQ1Df5wJwxsAmjfFMlkMmM7w3yKhM +2M8wmpqfDXkS5CIqY4Q2IJ69XWtbXMnU7WffBKZS2qADMEhRnGTGb+7X+TFzwFFDyk5 2P7xVrpHjXGim2VkXkFK45z+PbxQ2se0OFI8JOj4m7rmydsETPpCp7X0669oUb50iiY9 UVsQ== X-Gm-Message-State: AOAM533mjdRWNecBwgPI7fYrEluQ2kb83Z0Dsfp0WLdWYgBMVw9aI88w Z6L34MjuPtt8MG4QL/onqg== X-Google-Smtp-Source: ABdhPJyaj3PFM+CFdCy6mV1i58kFekEGMqO1UowSfypEY5AIM4vaGx5gSsEY/QdqAhmg5ntfqWZ6EQ== X-Received: by 2002:a05:6e02:ea2:: with SMTP id u2mr1371612ilj.140.1596488552257; Mon, 03 Aug 2020 14:02:32 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:31 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 26/27] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Date: Mon, 3 Aug 2020 15:01:15 -0600 Message-Id: <20200803210116.3132633-27-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org While the Designware controller appears to hard code the PCI_CAP_ID_EXP capability register at 0x70, there's no need to hard code this in the driver as it is discoverable. Cc: Kishon Vijay Abraham I Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Murali Karicheri Cc: Pratyush Anand Cc: linux-omap@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pci-dra7xx.c | 4 +--- drivers/pci/controller/dwc/pci-keystone.c | 11 +++++------ drivers/pci/controller/dwc/pcie-spear13xx.c | 4 +--- 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index 6184ebc9392d..b4508c3ffe96 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -73,8 +73,6 @@ #define LINK_UP BIT(16) #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF -#define EXP_CAP_ID_OFFSET 0x70 - #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128 @@ -142,7 +140,7 @@ static int dra7xx_pcie_establish_link(struct dw_pcie *pci) struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci); struct device *dev = pci->dev; u32 reg; - u32 exp_cap_off = EXP_CAP_ID_OFFSET; + u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); if (dw_pcie_link_up(pci)) { dev_err(dev, "link is already up\n"); diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 205754a6bc3c..d2eca3afebdb 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -96,8 +96,6 @@ #define LEG_EP 0x1 #define RC 0x2 -#define EXP_CAP_ID_OFFSET 0x70 - #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 @@ -1125,22 +1123,23 @@ static int ks_pcie_am654_set_mode(struct device *dev, static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed) { u32 val; + u32 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); dw_pcie_dbi_ro_wr_en(pci); - val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= link_speed; - dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP, + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); } - val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2); + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { val &= ~((u32)PCI_EXP_LNKCAP_SLS); val |= link_speed; - dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2, + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, val); } diff --git a/drivers/pci/controller/dwc/pcie-spear13xx.c b/drivers/pci/controller/dwc/pcie-spear13xx.c index 7d0cdfd8138b..a4303148e8b1 100644 --- a/drivers/pci/controller/dwc/pcie-spear13xx.c +++ b/drivers/pci/controller/dwc/pcie-spear13xx.c @@ -65,8 +65,6 @@ struct pcie_app_reg { /* CR6 */ #define MSI_CTRL_INT (1 << 26) -#define EXP_CAP_ID_OFFSET 0x70 - #define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev) static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) @@ -75,7 +73,7 @@ static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie) struct pcie_port *pp = &pci->pp; struct pcie_app_reg *app_reg = spear13xx_pcie->app_base; u32 val; - u32 exp_cap_off = EXP_CAP_ID_OFFSET; + u32 exp_cap_off = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); if (dw_pcie_link_up(pci)) { dev_err(pci->dev, "link already up\n"); From patchwork Mon Aug 3 21:01:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Rob Herring (Arm)" X-Patchwork-Id: 1340559 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=kernel.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BL9M22NNVz9sSt for ; Tue, 4 Aug 2020 07:02:38 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729126AbgHCVCh (ORCPT ); Mon, 3 Aug 2020 17:02:37 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:43788 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728570AbgHCVCg (ORCPT ); Mon, 3 Aug 2020 17:02:36 -0400 Received: by mail-io1-f65.google.com with SMTP id k23so39951531iom.10; Mon, 03 Aug 2020 14:02:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5V63dl5D15U/c4aTTJinxu1IGbYXot5HyJAyQBAcQN8=; b=lf+K0Ql0HCqhJcyF4kai/etIqiUZ5bNVUJd1+XspolRaUPLVLF6HBHldF/eAGa4TuT pxPeu7ETiPIkjyXkvnU3ZWVZdmXznDyHHSy93nOnTCrIYV2cy9EMWm8FCWdKvKRFDDSj bj95yG17VJ9ktftMRMUw+bhcIOpKW/KbyJqppiMFA8wpr8TkW8D7ozmuY1evdMp484Jq kVog3G7VEvBV+dIiF+cuEHt5FunipPMYC9l+3Pxo4oDYhz+7klGu1zcZ0tydwv08girF uOf7Z2qnsEIfEYSqg6hT/M9BaaVd62Lkk2tTBr6so+m8bb3+CqlPIlE3dQM1Fo1ZD7y+ pxAQ== X-Gm-Message-State: AOAM533M199Z9L1ErQJW2xeBpdskJyMIwQUIg32k+YS0Kxx2VA2t/H6O 86r7O0LE3m2qQzGF9QN+6A== X-Google-Smtp-Source: ABdhPJye2Mo2SgL9U7MmsN235jpxm7lOgHdwxN7y4uIMz2vtYYQ/vzsM/p/WbFYNk1hakIOySw24tA== X-Received: by 2002:a6b:c504:: with SMTP id v4mr1853953iof.20.1596488554927; Mon, 03 Aug 2020 14:02:34 -0700 (PDT) Received: from xps15.herring.priv ([64.188.179.252]) by smtp.googlemail.com with ESMTPSA id r6sm9292280iod.7.2020.08.03.14.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 14:02:34 -0700 (PDT) From: Rob Herring To: Bjorn Helgaas , Gustavo Pimentel , Jingoo Han , Lorenzo Pieralisi Cc: Binghui Wang , Bjorn Andersson , Fabio Estevam , Jesper Nilsson , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , Kishon Vijay Abraham I , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org, linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-tegra@vger.kernel.org, Lucas Stach , Masahiro Yamada , Murali Karicheri , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Stanimir Varbanov , Thierry Reding , Xiaowei Song , Yue Wang Subject: [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic register definitions Date: Mon, 3 Aug 2020 15:01:16 -0600 Message-Id: <20200803210116.3132633-28-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200803210116.3132633-1-robh@kernel.org> References: <20200803210116.3132633-1-robh@kernel.org> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra driver has its own defines for common Designware Port Logic registers. Convert it to use the standard register definitions. Cc: Jingoo Han Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-pci@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Rob Herring --- drivers/pci/controller/dwc/pcie-designware.h | 6 +++ drivers/pci/controller/dwc/pcie-tegra194.c | 56 ++++++++------------ 2 files changed, 28 insertions(+), 34 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index b18a9a5f48d2..3bd322db69a6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -32,7 +32,13 @@ /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_AFR 0x70C #define PORT_AFR_N_FTS_MASK GENMASK(15, 8) +#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n) #define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16) +#define PORT_AFR_ENTER_ASPM BIT(30) +#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 24 +#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) +#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 27 +#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27) #define PCIE_PORT_LINK_CONTROL 0x710 #define PORT_LINK_DLL_LINK_EN BIT(5) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index c567c9c09ff6..ad295c854853 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -183,19 +183,7 @@ #define EVENT_COUNTER_GROUP_SEL_SHIFT 24 #define EVENT_COUNTER_GROUP_5 0x5 -#define PORT_LOGIC_ACK_F_ASPM_CTRL 0x70C -#define ENTER_ASPM BIT(30) -#define L0S_ENTRANCE_LAT_SHIFT 24 -#define L0S_ENTRANCE_LAT_MASK GENMASK(26, 24) -#define L1_ENTRANCE_LAT_SHIFT 27 -#define L1_ENTRANCE_LAT_MASK GENMASK(29, 27) -#define N_FTS_SHIFT 8 -#define N_FTS_MASK GENMASK(7, 0) #define N_FTS_VAL 52 - -#define PORT_LOGIC_GEN2_CTRL 0x80C -#define PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE BIT(17) -#define FTS_MASK GENMASK(7, 0) #define FTS_VAL 52 #define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828 @@ -401,9 +389,9 @@ static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N; appl_writel(pcie, val, APPL_CAR_RESET_OVRD); - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); - val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE; - dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val |= PORT_LOGIC_SPEED_CHANGE; + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); } } @@ -694,11 +682,11 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); /* Program L0s and L1 entrance latencies */ - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); - val &= ~L0S_ENTRANCE_LAT_MASK; - val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT); - val |= ENTER_ASPM; - dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); + val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; + val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); + val |= PORT_AFR_ENTER_ASPM; + dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); } static int init_debugfs(struct tegra_pcie_dw *pcie) @@ -895,15 +883,15 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); /* Configure FTS */ - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); - val &= ~(N_FTS_MASK << N_FTS_SHIFT); - val |= N_FTS_VAL << N_FTS_SHIFT; - dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); + val &= ~PORT_AFR_N_FTS_MASK; + val |= PORT_AFR_N_FTS(N_FTS_VAL); + dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); - val &= ~FTS_MASK; + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_N_FTS_MASK; val |= FTS_VAL; - dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); /* Enable as 0xFFFF0001 response for CRS */ val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT); @@ -1820,15 +1808,15 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); /* Configure N_FTS & FTS */ - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL); - val &= ~(N_FTS_MASK << N_FTS_SHIFT); - val |= N_FTS_VAL << N_FTS_SHIFT; - dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val); + val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); + val &= ~PORT_AFR_N_FTS_MASK; + val |= PORT_AFR_N_FTS(FTS_VAL); + dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); - val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL); - val &= ~FTS_MASK; + val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_N_FTS_MASK; val |= FTS_VAL; - dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val); + dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val); /* Configure Max Speed from DT */ if (pcie->max_speed && pcie->max_speed != -EINVAL) {