From patchwork Thu Jul 23 23:21:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 1335194 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.a=rsa-sha256 header.s=mail181024 header.b=xcEWeqzC; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BCSyP2Gplz9sR4 for ; Fri, 24 Jul 2020 09:21:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728177AbgGWXVa (ORCPT ); Thu, 23 Jul 2020 19:21:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47202 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727775AbgGWXV2 (ORCPT ); Thu, 23 Jul 2020 19:21:28 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [IPv6:2001:df5:b000:5::4]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C414FC0619D3 for ; Thu, 23 Jul 2020 16:21:27 -0700 (PDT) Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 37C97891B2; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1595546484; bh=gMxO8i9clW2OX4l94MGgERIuhi2kgyZuM5WdocG61W8=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=xcEWeqzCPiZuZY6t1JYpYgT6lHKDkwVJXRE7idSVm0XXwjwWMm/TGOZmmyDA6hNVd cb6NkNYn1rcdmFbkN1eP7A7B5TEDV47Qea2I0uiYZ6/naJ5fhQ+jm/KHgvmVgIgbtJ S8U6IIwO5lE/TICz0l3Dc2iRYZA4d2HMHa+bYjAoqDEUj6IlKZfXh+AnfVeq7lbEEe fT6l0OX+7aQzZpqfZeXomKGrHroVrNKdOwdOZh3nIGJ/q5zaRA7BLnKvvqtHnIME4h KyL0AeUOWXVQL8S7KXITV6vndrBgPt9wytNI820/ItrmsmhwQSKO1A+2IX8vwu7Ejw G0Odv4J6uWAkw== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Fri, 24 Jul 2020 11:21:22 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.20]) by smtp (Postfix) with ESMTP id E782B13EEB7; Fri, 24 Jul 2020 11:21:23 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 1D87A280079; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) From: Chris Packham To: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2 1/3] net: dsa: mv88e6xxx: MV88E6097 does not support jumbo configuration Date: Fri, 24 Jul 2020 11:21:20 +1200 Message-Id: <20200723232122.5384-2-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200723232122.5384-1-chris.packham@alliedtelesis.co.nz> References: <20200723232122.5384-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 x-atlnz-ls: pat Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The MV88E6097 chip does not support configuring jumbo frames. Prior to commit 5f4366660d65 only the 6352, 6351, 6165 and 6320 chips configured jumbo mode. The refactor accidentally added the function for the 6097. Remove the erroneous function pointer assignment. Fixes: 5f4366660d65 ("net: dsa: mv88e6xxx: Refactor setting of jumbo frames") Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- Changes in v2: - Add review from Andrew drivers/net/dsa/mv88e6xxx/chip.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 6f019955ae42..4ddb6f3035c9 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3494,7 +3494,6 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { .port_set_frame_mode = mv88e6351_port_set_frame_mode, .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, - .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, From patchwork Thu Jul 23 23:21:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 1335192 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.a=rsa-sha256 header.s=mail181024 header.b=ypg0SOMI; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BCSyJ08tCz9sR4 for ; Fri, 24 Jul 2020 09:21:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727908AbgGWXV0 (ORCPT ); Thu, 23 Jul 2020 19:21:26 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:46218 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727115AbgGWXV0 (ORCPT ); Thu, 23 Jul 2020 19:21:26 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 6EF21891B3; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1595546484; bh=27Rf7c0sMrO2x585TIZH/W6JNKUcsP81RWV+FdFnYfU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=ypg0SOMInXz2fhDt+KpaU2J+qPLJr+1X0En90HZuPqdIHY03GqpSmkc0U2mWSZVFk RQhh+F4ozVfNceU7o/Jh9D+a3g/tcKTW+jTPqAMY+scTKSj2XVfyj0I4L6hlGzUkyr Snh4zTYUdEdEEDtGifPYYy86UV4cqUWJP6EyJ5leS/5X8WI+fvUC1gWG9fzAdgat6n 1tbDBm08I9UeyeckMeBt9BjkboXMyjJGucWikNZWnibPZVlFDrnGefDC3omIhkAhv9 i7lC3RhU9T1s52fozkK0VLhBdVLDfZjv3PtS9S8dVFDTLPKeR7H8ZVs8ZtkPbecBsT rJsYsCu8aPJyg== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Fri, 24 Jul 2020 11:21:22 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.20]) by smtp (Postfix) with ESMTP id 14D3813EEB7; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 3EE89280079; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) From: Chris Packham To: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2 2/3] net: dsa: mv88e6xxx: Support jumbo configuration on 6190/6190X Date: Fri, 24 Jul 2020 11:21:21 +1200 Message-Id: <20200723232122.5384-3-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200723232122.5384-1-chris.packham@alliedtelesis.co.nz> References: <20200723232122.5384-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 x-atlnz-ls: pat Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org The MV88E6190 and MV88E6190X both support per port jumbo configuration just like the other GE switches. Install the appropriate ops. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- I'm including this change in my series for completeness. Looking at the datasheets I think this is an unintentional omission but I don't have actual hardware to test this change on so some testing from someone with access to the right chip would be appreciated. Changes in v2: - Add review from Andrew drivers/net/dsa/mv88e6xxx/chip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 4ddb6f3035c9..43a2ab8cf2c8 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3958,6 +3958,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = { .port_set_frame_mode = mv88e6351_port_set_frame_mode, .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, + .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_pause_limit = mv88e6390_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -4016,6 +4017,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = { .port_set_frame_mode = mv88e6351_port_set_frame_mode, .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, + .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_pause_limit = mv88e6390_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, From patchwork Thu Jul 23 23:21:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 1335193 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=alliedtelesis.co.nz Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=alliedtelesis.co.nz header.i=@alliedtelesis.co.nz header.a=rsa-sha256 header.s=mail181024 header.b=eoWGRD1d; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BCSyN3TD4z9sRK for ; Fri, 24 Jul 2020 09:21:32 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728019AbgGWXV1 (ORCPT ); Thu, 23 Jul 2020 19:21:27 -0400 Received: from gate2.alliedtelesis.co.nz ([202.36.163.20]:46223 "EHLO gate2.alliedtelesis.co.nz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727775AbgGWXV1 (ORCPT ); Thu, 23 Jul 2020 19:21:27 -0400 Received: from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 9B089891B4; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1595546484; bh=ygJw+StLaLgK+RAsbex5A3XEplXxMiWAgkqunNF1oLE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=eoWGRD1dVdycW3CfMFEfmrSyK6H21feyRCYMzb+z6Cf50Qx/i4lHzSlrvOFKioYh7 9XmMHIPVKLmYn+zig+mfjVAuqm5WaxX9x9LARDxsgAWWinT01EvQJqgcfRx7KrcGfU clBlAEbhWt7785fquflx7jMH1skQIq8tLoX8TCGx9QKKRA7aoh0FNYs3aOZVCR6RWy 0put+opCKgPdPu2OxYMBKhAtbojtQkNdYIAnu4Gx0B7QHy/h5NBkB7ebdtF6nKswP8 nVez5eAO0frm7YnVAGvpRlWFbMQJWwx3qZC3+k6Lr38haPY4LhWF6jFyaYzA6xyoVk b6g9ZWH2J5nlQ== Received: from smtp (Not Verified[10.32.16.33]) by mmarshal3.atlnz.lc with Trustwave SEG (v7,5,8,10121) id ; Fri, 24 Jul 2020 11:21:22 +1200 Received: from chrisp-dl.ws.atlnz.lc (chrisp-dl.ws.atlnz.lc [10.33.22.20]) by smtp (Postfix) with ESMTP id 5246413EEB7; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) Received: by chrisp-dl.ws.atlnz.lc (Postfix, from userid 1030) id 7C63D280079; Fri, 24 Jul 2020 11:21:24 +1200 (NZST) From: Chris Packham To: andrew@lunn.ch, vivien.didelot@gmail.com, f.fainelli@gmail.com, davem@davemloft.net, kuba@kernel.org Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham Subject: [PATCH v2 3/3] net: dsa: mv88e6xxx: Use chip-wide max frame size for MTU Date: Fri, 24 Jul 2020 11:21:22 +1200 Message-Id: <20200723232122.5384-4-chris.packham@alliedtelesis.co.nz> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200723232122.5384-1-chris.packham@alliedtelesis.co.nz> References: <20200723232122.5384-1-chris.packham@alliedtelesis.co.nz> MIME-Version: 1.0 x-atlnz-ls: pat Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Some of the chips in the mv88e6xxx family don't support jumbo configuration per port. But they do have a chip-wide max frame size that can be used. Use this to approximate the behaviour of configuring a port based MTU. Signed-off-by: Chris Packham Reviewed-by: Andrew Lunn --- The only hardware I have access to uses a 88E6097. I've included the 6085, 6123 and 6185 based on reading the datasheets. Changes in v2: - Rebase on top of net-next/master drivers/net/dsa/mv88e6xxx/chip.c | 9 +++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 3 +++ drivers/net/dsa/mv88e6xxx/global1.c | 17 +++++++++++++++++ drivers/net/dsa/mv88e6xxx/global1.h | 2 ++ 4 files changed, 31 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 43a2ab8cf2c8..b8a3e8c88c07 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2699,6 +2699,8 @@ static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) if (chip->info->ops->port_set_jumbo_size) return 10240; + else if (chip->info->ops->set_max_frame_size) + return 1632; return 1522; } @@ -2710,6 +2712,8 @@ static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) mv88e6xxx_reg_lock(chip); if (chip->info->ops->port_set_jumbo_size) ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); + else if (chip->info->ops->set_max_frame_size) + ret = chip->info->ops->set_max_frame_size(chip, new_mtu); else if (new_mtu > 1522) ret = -EINVAL; @@ -3450,6 +3454,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = { .vtu_getnext = mv88e6352_g1_vtu_getnext, .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .phylink_validate = mv88e6185_phylink_validate, + .set_max_frame_size = mv88e6185_g1_set_max_frame_size, }; static const struct mv88e6xxx_ops mv88e6095_ops = { @@ -3478,6 +3483,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = { .vtu_getnext = mv88e6185_g1_vtu_getnext, .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, .phylink_validate = mv88e6185_phylink_validate, + .set_max_frame_size = mv88e6185_g1_set_max_frame_size, }; static const struct mv88e6xxx_ops mv88e6097_ops = { @@ -3515,6 +3521,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { .vtu_getnext = mv88e6352_g1_vtu_getnext, .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .phylink_validate = mv88e6185_phylink_validate, + .set_max_frame_size = mv88e6185_g1_set_max_frame_size, }; static const struct mv88e6xxx_ops mv88e6123_ops = { @@ -3549,6 +3556,7 @@ static const struct mv88e6xxx_ops mv88e6123_ops = { .vtu_getnext = mv88e6352_g1_vtu_getnext, .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .phylink_validate = mv88e6185_phylink_validate, + .set_max_frame_size = mv88e6185_g1_set_max_frame_size, }; static const struct mv88e6xxx_ops mv88e6131_ops = { @@ -3938,6 +3946,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = { .vtu_getnext = mv88e6185_g1_vtu_getnext, .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, .phylink_validate = mv88e6185_phylink_validate, + .set_max_frame_size = mv88e6185_g1_set_max_frame_size, }; static const struct mv88e6xxx_ops mv88e6190_ops = { diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 1c541b074256..2d70eac30e58 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -552,6 +552,9 @@ struct mv88e6xxx_ops { void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port, unsigned long *mask, struct phylink_link_state *state); + + /* Max Frame Size */ + int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu); }; struct mv88e6xxx_irq_ops { diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c index ca3a7a7a73c3..f62aa83ca08d 100644 --- a/drivers/net/dsa/mv88e6xxx/global1.c +++ b/drivers/net/dsa/mv88e6xxx/global1.c @@ -196,6 +196,23 @@ int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) return mv88e6185_g1_wait_ppu_disabled(chip); } +int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) +{ + u16 val; + int err; + + err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); + if (err) + return err; + + val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632; + + if (mtu > 1518) + val |= MV88E6185_G1_CTL1_MAX_FRAME_1632; + + return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); +} + /* Offset 0x10: IP-PRI Mapping Register 0 * Offset 0x11: IP-PRI Mapping Register 1 * Offset 0x12: IP-PRI Mapping Register 2 diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h index 5324c6f4ae90..1e3546f8b072 100644 --- a/drivers/net/dsa/mv88e6xxx/global1.h +++ b/drivers/net/dsa/mv88e6xxx/global1.h @@ -282,6 +282,8 @@ int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip); int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip); int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip); +int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu); + int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);