From patchwork Mon Jul 6 16:14:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rJT4Xrkz9sSn for ; Tue, 7 Jul 2020 02:15:21 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rJT2WCNzDqdl for ; Tue, 7 Jul 2020 02:15:21 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4B0rJ04hwyzDqc8 for ; Tue, 7 Jul 2020 02:14:55 +1000 (AEST) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 066GDfso092134 for ; Mon, 6 Jul 2020 12:14:53 -0400 Received: from ppma01dal.us.ibm.com (83.d6.3fa9.ip4.static.sl-reverse.com [169.63.214.131]) by mx0b-001b2d01.pphosted.com with ESMTP id 322nx1aewm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 12:14:52 -0400 Received: from pps.filterd (ppma01dal.us.ibm.com [127.0.0.1]) by ppma01dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 066Ftv90021207 for ; Mon, 6 Jul 2020 16:14:52 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma01dal.us.ibm.com with ESMTP id 322hd8mw7g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:14:52 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GEpos16581054 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:14:51 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F0BD6136053 for ; Mon, 6 Jul 2020 16:14:50 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A3E4613604F for ; Mon, 6 Jul 2020 16:14:50 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:14:50 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:28 -0400 Message-Id: <20200706161439.12635-2-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 01/12] doc/opal-uv-abi.rst X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Ryan Grimm --- doc/opal-uv-abi.rst | 420 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 420 insertions(+) create mode 100644 doc/opal-uv-abi.rst diff --git a/doc/opal-uv-abi.rst b/doc/opal-uv-abi.rst new file mode 100644 index 00000000..0d5af997 --- /dev/null +++ b/doc/opal-uv-abi.rst @@ -0,0 +1,420 @@ +.. SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later + +================= +OPAL UV ABI (RFC) +================= + +.. contents:: + :depth: 3 + +.. sectnum:: + :depth: 3 + +This document describes the function calling interface between OPAL +and the Ultravisor. + +Protected Execution Facility +############################ + +Protected Execution Facility (PEF) is an architectural change for +POWER 9 that enables Secure Virtual Machines (SVMs). When enabled, +PEF adds a new higher privileged mode, called Ultravisor mode, to +POWER architecture. Along with the new mode there is new firmware +called the Protected Execution Ultravisor (or Ultravisor for short). +Ultravisor mode is the highest privileged mode in POWER architecture. + ++------------------+ +| Privilege States | ++==================+ +| Problem | ++------------------+ +| Supervisor | ++------------------+ +| Hypervisor | ++------------------+ +| Ultravisor | ++------------------+ + +PEF protects SVMs from the hypervisor, privileged users, and other +VMs in the system. SVMs are protected while at rest and can only be +executed by an authorized machine. All virtual machines utilize +hypervisor services. The Ultravisor filters calls between the SVMs +and the hypervisor to assure that information does not accidentally +leak. All hypercalls except H_RANDOM are reflected to the hypervisor. +H_RANDOM is not reflected to prevent the hypervisor from influencing +random values in the SVM. + +To support this there is a refactoring of the ownership of resources +in the CPU. Some of the resources which were previously hypervisor +privileged are now ultravisor privileged. + +Hardware +======== + +The hardware changes include the following: + +* There is a new bit in the MSR that determines whether the current + process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process + is in secure mode, MSR(s)=0 process is in normal mode. + +* The MSR(S) bit can only be set by the Ultravisor. + +* HRFID cannot be used to set the MSR(S) bit. If the hypervisor needs + to return to a SVM it must use an ultracall. It can determine if + the VM it is returning to is secure. + +* There is a new Ultravisor privileged register, SMFCTRL, which has an + enable/disable bit SMFCTRL(E). + +* The privilege of a process is now determined by three MSR bits, + MSR(S, HV, PR). In each of the tables below the modes are listed + from least privilege to highest privilege. The higher privilege + modes can access all the resources of the lower privilege modes. + +**Secure Mode MSR Settings** + ++---+---+---+---------------+ +| S | HV| PR|Privilege | ++===+===+===+===============+ +| 1 | 0 | 1 | Problem | ++---+---+---+---------------+ +| 1 | 0 | 0 | Privileged(OS)| ++---+---+---+---------------+ +| 1 | 1 | 0 | Ultravisor | ++---+---+---+---------------+ +| 1 | 1 | 1 | Reserved | ++---+---+---+---------------+ + +**Normal Mode MSR Settings** + ++---+---+---+---------------+ +| S | HV| PR|Privilege | ++===+===+===+===============+ +| 0 | 0 | 1 | Problem | ++---+---+---+---------------+ +| 0 | 0 | 0 | Privileged(OS)| ++---+---+---+---------------+ +| 0 | 1 | 0 | Hypervisor | ++---+---+---+---------------+ +| 0 | 1 | 1 | Problem (HV) | ++---+---+---+---------------+ + +* Memory is partitioned into secure and normal memory. Only processes + that are running in secure mode can access secure memory. + +* The hardware does not allow anything that is not running secure to + access secure memory. This means that the Hypervisor cannot access + the memory of the SVM without using an ultracall (asking the + Ultravisor). The Ultravisor will only allow the hypervisor to see + the SVM memory encrypted. + +* I/O systems are not allowed to directly address secure memory. This + limits the SVMs to virtual I/O only. + +* The architecture allows the SVM to share pages of memory with the + hypervisor that are not protected with encryption. However, this + sharing must be initiated by the SVM. + +* When a process is running in secure mode all hypercalls + (syscall lev=1) are reflected to the Ultravisor. + +* When a process is in secure mode all interrupts go to the + Ultravisor. + +* The following resources have become Ultravisor privileged and + require an Ultravisor interface to manipulate: + + * Processor configurations registers (SCOMs). + + * Stop state information. + + * The debug registers CIABR, DAWR, and DAWRX become Ultravisor + resources when SMFCTRL(D) is set. If SMFCTRL(D) is not set they do + not work in secure mode. When set, reading and writing requires + an Ultravisor call, otherwise that will cause a Hypervisor Emulation + Assistance interrupt. + + * PTCR and partition table entries (partition table is in secure + memory). An attempt to write to PTCR will cause a Hypervisor + Emulation Assitance interrupt. + + * LDBAR (LD Base Address Register) and IMC (In-Memory Collection) + non-architected registers. An attempt to write to them will cause a + Hypervisor Emulation Assistance interrupt. + + * Paging for an SVM, sharing of memory with Hypervisor for an SVM. + (Including Virtual Processor Area (VPA) and virtual I/O). + +Software/Microcode +================== + +The software changes include: + +* When the UV_ESM ultracall is made the Ultravisor copies the VM into + secure memory, decrypts the verification information, and checks the + integrity of the SVM. If the integrity check passes the Ultravisor + passes control in secure mode. + +The Ultravisor offers new services to the hypervisor and SVMs. These +are accessed through ultracalls. + +Terminology +=========== + +* Hypercalls: special system calls used to request services from + Hypervisor. + +* Normal memory: Memory that is accessible to Hypervisor. + +* Normal page: Page backed by normal memory and available to + Hypervisor. + +* Secure memory: Memory that is accessible only to Ultravisor and + SVMs. + +* Secure page: Page backed by secure memory and only available to + Ultravisor and SVM. + +* SVM: Secure Virtual Machine. + +* Ultracalls: special system calls used to request services from + Ultravisor. + +Ultravisor Initialization +######################### + +Secure Memory +============= + +Skiboot parses secure memory from the HDAT tables and creates the secure-memory +and ibm,ultravisor device tree nodes. secure-memory is similar to a memory@ +node except the device_type is "secure_memory". For example: + +.. code-block:: dts + + secure-memory@100fe00000000 { + device_type = "secure_memory"; + compatible = "ibm,secure_memory"; + ibm,chip-id = <0>; + reg = < 0x100fe 0x0 0x2 0x0>; + } + +Regions of secure memory will be reserved by hostboot such as OCC, HOMER, and +SBE. Skiboot will use the existing reserve infrastructure to reserve them. +For example: + +.. code-block:: + + ibm,HCODE@100fffcaf0000 + ibm,OCC@100fffcdd0000 + ibm,RINGOVD@100fffcae0000 + ibm,WOFDATA@100fffcb90000 + ibm,arch-reg-data@100fffd700000 + ibm,hbrt-code-image@100fffcec0000 + ibm,hbrt-data@100fffd420000 + ibm,homer-image@100fffd800000 + ibm,homer-image@100fffdc00000 + ibm,occ-common-area@100ffff800000 + ibm,sbe-comm@100fffce90000 + ibm,sbe-comm@100fffceb0000 + ibm,sbe-ffdc@100fffce80000 + ibm,sbe-ffdc@100fffcea0000 + ibm,secure-crypt-algo-code@100fffce70000 + ibm,uvbwlist@100fffcad0000 + +For Mambo, ultra.tcl creates the secure-memory device tree node and the +ibm,ultravisor device tree node in external/mambo/skiboot.tcl. Secure memory +is currently defined as the bottom half of the total the size of memory. Mambo +has no protection on secure memory, so a watchpoint could be used to ensure +Skiboot does not touch secure memory. + +For BML, the BML script parses secure memory from the Cronus config file and +creates the secure-memory and ibm,ultravisor device tree nodes. + +In all cases, the console log should indicate secure memory has been found and +added to the device tree. For example: + +.. code-block:: + + [ 68.235326307,5] UV: Secure memory range added to DT [0x0001000e00000000..0x001001000000000] + +Loading The Ultravisor +====================== + +Skiboot uses secure and trusted boot to load and verify the compressed UV image +from the PNOR into regular memory. It unpacks the UV into regular memory in +the function ``init_uv``. + +``init_uv`` finds the UV node in the device tree via the "ibm,ultravisor" +compatible property. For example: + +.. code-block:: dts + + ibm,ultravisor { + compatible = "ibm,ultravisor"; + #address-cells = <0x02>; + #size-cells = <0x02>; + + firmware@200000000 { + compatible = "ibm,uv-firmware"; + reg = <0x02 0x00 0xf677f>; + memcons = <0x00 0x3022d030>; + sys-fdt = <0x00 0x30509068>; + uv-fdt = <0x02 0x200000>; + }; + }; + +Skiboot creates ibm,ultravisor and the reg property in hdata/spira.c. + +Mambo and BML use scripts to put the ultra image directly in regular memory and +a reserve is created named ibm,uv-firmware. + +Starting The Ultravisor +======================= + +Skiboot starts the UV in ``main_cpu_entry`` before the kernel is loaded and booted. +Skiboot creates a job on all threads and sends them to ``enter_uv`` in asm/head.S. +This function's prototype is: + +.. code-block:: c + + /* + * @brief Enter UV. + * + * @param Offset into ultravisor image for threads to jump to + * @param Flattened system device tree + * + * @return 0 on success, else a negative error code on failure. + */ + u64 enter_uv(uint64_t entry, void *fdt) + +The sys_fdt allows passing information to the UV, such as the location of the +memory console, and is easy to extend. + +In the future, a ``uv_fdt`` could be constructed in secure memory. For +example, a wrapping key could be passed to the ultravisor via a device tree +node in secure memory: + +.. code-block:: dts + + ibm,uv-fdt { + compatible = "ibm,uv-fdt"; + wrapping-key-password = "gUMShz6l2x4O9IeHrvBSuBR0FYANZTYK"; + }; + +The UV parses ``sys_fdt``, creates internal structures, and threads return in +hypervisor privilege moded. + +If successful, skiboot sets a variable named ``uv_present`` to true. Skiboot +uses this variable to dermine if the UV is initialized and ready to perform +ucalls. + +Ultravisor Failed Start Recovery +================================ + +If the ultravisor fails to start it will return a error code to init_uv. +init_uv will print error messages to the skiboot log and attempt to free +structures associated with the ultravisor. + +Skiboot will continue to be in ultravisor privilege mode, and will need to +perform a recovery action. + +[**TODO**: Need to describe the steps for Ultravisor load failure recovery action.] + +Ultracalls +########## + +Ultravisor calls ABI +==================== + +This section describes Ultravisor calls (ultracalls) needed by skiboot. The +ultracalls allow skiboot to request services from the Ultravisor such as +initializing a chip unit via XSCOM. + +Ultracalls are modeled after the hcall interface. The specific service needed +from an ultracall is specified in register R3. The status is returned in R3. +The call skiboot currently uses supports up to 6 arguments and 4 return +arguments. + +Each ultracall returns specific error codes, applicable in the context +of the ultracall. However, like with the PowerPC Architecture Platform +Reference (PAPR), if no specific error code is defined for a +particular situation, then the ultracall will fallback to an erroneous +parameter-position based code. i.e U_PARAMETER, U_P2, U_P3 etc +depending on the ultracall parameter that may have caused the error. + +For now this only covers ultracalls currently implemented and being used by +skiboot but others can be added here when it makes sense. + +The full specification for all ultracalls will eventually be made available in +the public/OpenPower version of the PAPR specification. + +Ultracalls used by Skiboot +========================== + +UV_READ_SCOM +------------ + +Perform an XSCOM read and put the value in a buffer. + +Syntax +~~~~~~ + +.. code-block:: c + + long ucall(unsigned long UV_READ_SCOM, + unsigned long *retbuf, + u64 partid, + u64 pcb_addr) + +Return values +~~~~~~~~~~~~~ + +* U_SUCCESS on success. +* U_PERMISSION if called from VM context. +* U_PARAMETER if invalid partiton or address. +* U_BUSY if unit is busy, need to retry. +* U_XSCOM_CHIPLET_OFF if cpu is asleep. +* U_XSCOM_PARTIAL_GOOD if partial good. +* U_XSCOM_ADDR_ERROR if address error. +* U_XSCOM_CLOCK_ERROR if clock error. +* U_XSCOM_PARITY_ERROR if parity error. +* U_XSCOM_TIMEOUT if timeout. +* U_XSCOM_CTR_OFFLINED if centaur offline. + +UV_WRITE_SCOM +------------- + +Perform an XSCOM write. + +Syntax +~~~~~~ + +.. code-block:: c + + long ucall(unsigned long UV_WRITE_SCOM, + u64 partid, + u64 pcb_addr, + u64 val) + +Return values +~~~~~~~~~~~~~ + +One of the following values: + +* U_SUCCESS on success. +* U_PERMISSION if called from VM context. +* U_PARAMETER if invalid partiton. +* U_BUSY if unit is busy, need to retry. +* U_XSCOM_CHIPLET_OFF if cpu is asleep. +* U_XSCOM_PARTIAL_GOOD if partial good. +* U_XSCOM_ADDR_ERROR if address error. +* U_XSCOM_CLOCK_ERROR if clock error. +* U_XSCOM_PARITY_ERROR if parity error. +* U_XSCOM_TIMEOUT if timeout. +* U_XSCOM_CTR_OFFLINED if centaur offline. + +References +########## + +.. [1] `Supporting Protected Computing on IBM Power Architecture `_ From patchwork Mon Jul 6 16:14:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323715 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rL32T6Lz9sRK for ; Tue, 7 Jul 2020 02:16:43 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rL31j0VzDqR0 for ; Tue, 7 Jul 2020 02:16:43 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4B0rJz68sPzDqcg for ; Tue, 7 Jul 2020 02:15:47 +1000 (AEST) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 066GE9ig087377 for ; Mon, 6 Jul 2020 12:15:42 -0400 Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0b-001b2d01.pphosted.com with ESMTP id 322kcxkn8f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 12:15:15 -0400 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 066Ft8GE026362 for ; Mon, 6 Jul 2020 16:15:03 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma02wdc.us.ibm.com with ESMTP id 322hd8gqpe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:15:02 +0000 Received: from b03ledav006.gho.boulder.ibm.com (b03ledav006.gho.boulder.ibm.com [9.17.130.237]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GExvj27066626 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:14:59 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 06819C605B for ; Mon, 6 Jul 2020 16:15:02 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A3714C606C for ; Mon, 6 Jul 2020 16:15:01 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:15:01 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:29 -0400 Message-Id: <20200706161439.12635-3-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=3 spamscore=0 cotscore=-2147483648 mlxlogscore=999 mlxscore=0 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 02/12] Add functions to initialize and start an ultravisor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Power 9 introduces a mode called ultravisor mode. init_uv looks for uv-src-address in the device tree and copies the image to the address specified in "reg". start_ultravisor is called in load_and_boot_kernel with the pointer to the system fdt. Every thread is sent to the ultravisor image and returns with UV mode off. A minimal ultravisor could disable UV and PEF, instructions in commit "skiboot.tcl: ultravisor support." [ maddy: Initial implementation] [Signed-off-by: Madhavan Srinivasan [ santosh: Initial implementation] Signed-off-by: Santosh Sivaraj Signed-off-by: Ryan Grimm --- asm/misc.S | 21 ++++++++++ core/init.c | 7 +++- hw/Makefile.inc | 2 +- hw/ultravisor.c | 93 ++++++++++++++++++++++++++++++++++++++++++++ include/processor.h | 7 ++++ include/ultravisor.h | 35 +++++++++++++++++ 6 files changed, 162 insertions(+), 3 deletions(-) create mode 100644 hw/ultravisor.c create mode 100644 include/ultravisor.h diff --git a/asm/misc.S b/asm/misc.S index 03344897..30f67872 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -306,3 +306,24 @@ exit_uv_mode: mtspr SPR_USRR0,%r4 PPC_INST_URFID +/* + * start_uv register usage: + * + * r3 : UV entry addr + * r4 : system fdt + */ +.global enter_uv +enter_uv: + mflr %r0 + std %r0,16(%r1) + sync + /* flush caches, etc */ + icbi 0,%r3 + sync + isync + mtctr %r3 + mr %r3,%r4 + bctrl /* branch to UV here */ + ld %r0,16(%r1) + mtlr %r0 + blr diff --git a/core/init.c b/core/init.c index 07e3092f..e0166098 100644 --- a/core/init.c +++ b/core/init.c @@ -47,6 +47,7 @@ #include #include #include +#include enum proc_gen proc_gen; unsigned int pcie_max_link_speed; @@ -603,6 +604,8 @@ void __noreturn load_and_boot_kernel(bool is_reboot) abort(); } + start_ultravisor(fdt); + op_display(OP_LOG, OP_MOD_INIT, 0x000C); mem_dump_free(); @@ -1369,8 +1372,8 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Add the list of interrupts going to OPAL */ add_opal_interrupts(); - /* Disable protected execution facility in BML */ - cpu_disable_pef(); + /* Initialize the ultravisor */ + init_uv(); /* Now release parts of memory nodes we haven't used ourselves... */ mem_region_release_unused(); diff --git a/hw/Makefile.inc b/hw/Makefile.inc index a7f450cf..f5408735 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -9,7 +9,7 @@ HW_OBJS += fake-nvram.o lpc-mbox.o npu2.o npu2-hw-procedures.o HW_OBJS += npu2-common.o npu2-opencapi.o phys-map.o sbe-p9.o capp.o HW_OBJS += occ-sensor.o vas.o sbe-p8.o dio-p9.o lpc-port80h.o cache-p9.o HW_OBJS += npu-opal.o npu3.o npu3-nvlink.o npu3-hw-procedures.o -HW_OBJS += ocmb.o +HW_OBJS += ocmb.o ultravisor.o HW=hw/built-in.a include $(SRC)/hw/fsp/Makefile.inc diff --git a/hw/ultravisor.c b/hw/ultravisor.c new file mode 100644 index 00000000..1be47ec5 --- /dev/null +++ b/hw/ultravisor.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2018-2019 IBM Corp. */ + +#include +#include +#include +#include +#include +#include +#include + +static struct dt_node *uv_fw_node; +static uint64_t uv_base_addr; +bool uv_present; + +static void cpu_start_ultravisor(void *fdt) +{ + uint64_t uv_entry = 0; + + if (dt_find_property(uv_fw_node, "uv-entry")) + uv_entry = dt_prop_get_u64(uv_fw_node, "uv-entry"); + + prlog(PR_DEBUG, "UV: Starting on CPU 0x%04x\n", this_cpu()->pir); + enter_uv(uv_base_addr + uv_entry, fdt); +} + +int start_ultravisor(void *fdt) +{ + struct cpu_thread *cpu; + struct cpu_job **jobs; + int i = 0; + + if (!uv_base_addr || !fdt) { + prlog(PR_DEBUG, "UV: uv_base_addr 0x%llx or fdt %p not set\n", + uv_base_addr, fdt); + return OPAL_INTERNAL_ERROR; + } + + jobs = zalloc(sizeof(struct cpu_job *) * cpu_max_pir); + + prlog(PR_DEBUG, "UV: Starting @0x%016llx fdt %p\n", + uv_base_addr, fdt); + + for_each_available_cpu(cpu) { + if (cpu == this_cpu()) + continue; + jobs[i++] = cpu_queue_job(cpu, "start_ultravisor", + cpu_start_ultravisor, fdt); + } + + cpu_start_ultravisor(fdt); + + uv_present = true; + + while (i > 0) + cpu_wait_job(jobs[--i], true); + + free(jobs); + + return OPAL_SUCCESS; +} + +void init_uv() +{ + uint64_t uv_dt_src, uv_fw_sz; + struct dt_node *reserved_mem; + + if (!is_msr_bit_set(MSR_S)) { + prlog(PR_DEBUG, "UV: S bit not set\n"); + return; + } + + uv_fw_node = dt_find_compatible_node(dt_root, NULL, "ibm,uv-firmware"); + if (!uv_fw_node) { + prlog(PR_DEBUG, "UV: No ibm,uv-firmware node found, disabling pef\n"); + cpu_disable_pef(); + return; + } + + reserved_mem = dt_find_by_path(dt_root, "/reserved-memory/ibm,uv-firmware"); + if (!reserved_mem) { + prerror("UV: No reserved memory for ibm,uv-firmware found\n"); + return; + } + + uv_dt_src = dt_get_address(reserved_mem, 0, &uv_fw_sz); + uv_base_addr = dt_get_address(uv_fw_node, 0, NULL); + + prlog(PR_INFO, "UV: Copying 0x%llx bytes to protected memory 0x%llx from 0x%llx\n", + uv_fw_sz, uv_base_addr, uv_dt_src); + + memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); +} diff --git a/include/processor.h b/include/processor.h index ddec6c04..cb81aabb 100644 --- a/include/processor.h +++ b/include/processor.h @@ -397,6 +397,13 @@ static inline void st_le32(uint32_t *addr, uint32_t val) asm volatile("stwbrx %0,0,%1" : : "r"(val), "r"(addr), "m"(*addr)); } +static inline bool is_msr_bit_set(uint64_t bit) +{ + if (mfmsr() & bit) + return true; + return false; +} + #endif /* __TEST__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/ultravisor.h b/include/ultravisor.h new file mode 100644 index 00000000..05edb53e --- /dev/null +++ b/include/ultravisor.h @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: Apache-2.0 +/* Copyright 2018-2019 IBM Corp. */ + +#ifndef __ULTRAVISOR_H +#define __ULTRAVISOR_H + +#include +#include +#include + +/* + * enter_uv: Each thread enters ultravisor and exits with S=0 + * @entry: Offset into ultravisor image for threads to jump to + * @fdt: Flattened system device tree + * + * All threads sent here by skiboot from C code + * + * return value: 0 on success, non-zero on failure + */ +extern int enter_uv(uint64_t entry, void *fdt); + +/* + * start_ultravisor: Start the ultravisor on all threads + * @fdt: Flattened system device tree + * + * return value: 0 on success, non-zero on failure + */ +int start_ultravisor(void *fdt); + +/* Set when ultravisor started, so code knows to make a ucall */ +extern bool uv_present; + +void init_uv(void); + +#endif /* __ULTRAVISOR_H */ From patchwork Mon Jul 6 16:14:30 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323713 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rK31Ccwz9sRK for ; Tue, 7 Jul 2020 02:15:51 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rK26TLDzDqdj for ; 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Mon, 6 Jul 2020 16:15:12 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:15:12 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:30 -0400 Message-Id: <20200706161439.12635-4-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 clxscore=1015 adultscore=0 phishscore=0 priorityscore=1501 cotscore=-2147483648 impostorscore=0 bulkscore=0 suspectscore=13 lowpriorityscore=0 mlxlogscore=999 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 03/12] skiboot.tcl: ultravisor support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This tcl code turns on the S bit in MSR and sets up SMFCTRL and SIM_CTRL if MAMBO_ENABLE_SMF is set. Skiboot will run its exit_uv_mode function because there's no ibm,utlravisor device tree node. If ULTRA_IMAGE is set, it loads the image at 0xc0000000 and sets up the ibm,ultravisor device tree node. This can be tested using this (hacked) skiboot as the ultravisor image with: export SKIBOOT=skiboot.lid export ULTRA_IMAGE=$SKIBOOT export ULTRA_ENTRY=$(grep exit_uv_mode skiboot.map|cut -f1 -d " ") export MAMBO_ENABLE_SMF=1 Although you need to hack up exit_uv_mode to ignore the fdt pointer and treat as primary thread. Signed-off-by: Ryan Grimm --- external/mambo/skiboot.tcl | 74 +++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) diff --git a/external/mambo/skiboot.tcl b/external/mambo/skiboot.tcl index 6003fcbe..c823985a 100644 --- a/external/mambo/skiboot.tcl +++ b/external/mambo/skiboot.tcl @@ -56,6 +56,16 @@ if { ![info exists env(SKIBOOT_ZIMAGE)] } { } mconfig payload PAYLOAD $env(SKIBOOT_ZIMAGE) +mconfig enable_smf MAMBO_ENABLE_SMF none + +mconfig ultra_image ULTRA_IMAGE none + +mconfig ultra_src_addr ULTRA_SRC_ADDR 0xc0000000; + +mconfig spr_urmor ULTRA_URMOR 0xe0000000 + +mconfig ultra_entry ULTRA_ENTRY 0; + mconfig linux_cmdline LINUX_CMDLINE "" # Paylod: Memory location for a Linux style ramdisk/initrd @@ -140,6 +150,11 @@ if { $default_config == "P9" } { if { $mconf(numa) } { myconf config memory_region_id_shift 45 } + + if { $mconf(enable_smf) != "none" } { + myconf config processor/initial/SMFCTRL 0x8000000000000002 + myconf config processor/initial/SIM_CTRL1 0x4228100404004000 + } } if { $mconf(numa) } { @@ -507,12 +522,16 @@ for { set c 0 } { $c < $mconf(cpus) } { incr c } { mysim mcm 0 cpu $c thread $t set spr pir $pir lappend irqreg $pir incr pir + if { $mconf(enable_smf) != "none" } { + mysim mcm 0 cpu $c thread $t set spr msr 0x9000000000400000 + } } mysim of addprop $cpu_node array "ibm,ppc-interrupt-server#s" irqreg } #Add In-Memory Collection Counter nodes -if { $default_config == "P9" } { +#if { $default_config == "P9" && $mconf(enable_ultra) == "none" } { +if { $default_config == "P9" && $mconf(ultra_image) == "none" } { #Add the base node "imc-counters" set imc_c [mysim of addchild $root_node "imc-counters" ""] mysim of addprop $imc_c string "compatible" "ibm,opal-in-memory-counters" @@ -669,6 +688,59 @@ if { [info exists env(SKIBOOT_ENABLE_MAMBO_STB)] } { } } +if {$mconf(ultra_image) != "none"} { + set uv_node [ mysim of addchild $root_node "ibm,ultravisor" "" ] + mysim of addprop $uv_node string "compatible" "ibm,ultravisor" + mysim of addprop $uv_node int "#address-cells" 2 + mysim of addprop $uv_node int "#size-cells" 2 + + set uv_fw_node [ mysim of addchild $uv_node "firmware" "" ] + mysim of addprop $uv_fw_node string "compatible" "ibm,uv-firmware" + set uv_entry $mconf(ultra_entry) + set uv_entry_prop [ list [expr $uv_entry >> 32] [expr $uv_entry & 0xffffffff] ] + mysim of addprop $uv_fw_node array "uv-entry" uv_entry_prop + + set range [list] + lappend range $mconf(spr_urmor) + lappend range [expr [mysim display memory_size] - $mconf(spr_urmor)] + mysim of addprop $uv_fw_node array64 "secure-memory-ranges" range + + + set start $mconf(spr_urmor) + + if {[file exists $mconf(ultra_image)]} { + set ultra_file $mconf(ultra_image) + } else { + puts "ERROR: Could not find ultra: $mconf(ultra_image)" + exit + } + + set ultra_size [file size $ultra_file] + set reg [list [expr $start >> 32] [expr $start & 0xffffffff] [expr $ultra_size >> 32] [expr $ultra_size & 0xffffffff]] + mysim of addprop $uv_fw_node array "reg" reg + + #secure-memory node + set start_hex [format %x $start] + set size [expr [mysim display memory_size] - $mconf(spr_urmor)] + set secure_mem_node [mysim of addchild $root_node "secure-memory@$start_hex" ""] + mysim of addprop $secure_mem_node string "compatible" "ibm,secure-memory" + set reg [list [expr $start >> 32] [expr $start & 0xffffffff] [expr $size >> 32] [expr $size & 0xffffffff]] + mysim of addprop $secure_mem_node array "reg" reg + mysim of addprop $secure_mem_node string "device_type" "secure-memory" + set associativity [list 4 0 0 0 0] + mysim of addprop $secure_mem_node "array" "ibm,associativity" associativity + set chip_id [format %x 0] + mysim of addprop $secure_mem_node array "ibm,chip-id" chip_id + + set src_addr $mconf(ultra_src_addr) + mysim memory fread $src_addr $ultra_size $ultra_file + + set uv_firmware [mysim of addchild $reserved_memory "ibm,uv-firmware" ""] + set reg [list $src_addr $ultra_size] + mysim of addprop $uv_firmware array64 "reg" reg + mysim of addprop $uv_firmware empty "name" "ibm,uv-firmware" +} + # Kernel command line args, appended to any from the device tree # e.g.: of::set_bootargs "xmon" # From patchwork Mon Jul 6 16:14:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323714 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rKb2GFsz9sRK for ; Tue, 7 Jul 2020 02:16:19 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rKb0tsqzDqcm for ; Tue, 7 Jul 2020 02:16:19 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; 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Mon, 6 Jul 2020 16:15:24 GMT Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by ppma03dal.us.ibm.com with ESMTP id 322hd8mwk3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:15:23 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GFNb914352678 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:15:23 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EE6C9B2084 for ; Mon, 6 Jul 2020 16:15:22 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D05E3B2085 for ; Mon, 6 Jul 2020 16:15:22 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:15:22 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:31 -0400 Message-Id: <20200706161439.12635-5-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=1 clxscore=1015 cotscore=-2147483648 mlxlogscore=999 impostorscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060119 Subject: [Skiboot] [RFC PATCH v7 04/12] Add memcons support for ultravisor X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan The ultravisor console buffer is provided at offset 0x01100000 from the skiboot base. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj --- hw/ultravisor.c | 13 +++++++++++++ include/console.h | 3 +++ include/debug_descriptor.h | 1 + include/mem-map.h | 16 ++++++++++------ 4 files changed, 27 insertions(+), 6 deletions(-) diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 1be47ec5..467f0ca6 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -8,11 +8,21 @@ #include #include #include +#include +#include static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; bool uv_present; +struct memcons uv_memcons __section(".data.memcons") = { + .magic = MEMCONS_MAGIC, + .obuf_phys = INMEM_UV_CON_START, + .ibuf_phys = INMEM_UV_CON_START + INMEM_UV_CON_OUT_LEN, + .obuf_size = INMEM_UV_CON_OUT_LEN, + .ibuf_size = INMEM_UV_CON_IN_LEN, +}; + static void cpu_start_ultravisor(void *fdt) { uint64_t uv_entry = 0; @@ -90,4 +100,7 @@ void init_uv() uv_fw_sz, uv_base_addr, uv_dt_src); memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); + + dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons); + debug_descriptor.uv_memcons_phys = (u64)&uv_memcons; } diff --git a/include/console.h b/include/console.h index 02fc7a4b..47ffe7fd 100644 --- a/include/console.h +++ b/include/console.h @@ -28,9 +28,12 @@ struct memcons { }; extern struct memcons memcons; +extern struct memcons uv_memcons; #define INMEM_CON_IN_LEN 16 #define INMEM_CON_OUT_LEN (INMEM_CON_LEN - INMEM_CON_IN_LEN) +#define INMEM_UV_CON_IN_LEN 16 +#define INMEM_UV_CON_OUT_LEN (INMEM_UV_CON_LEN - INMEM_UV_CON_IN_LEN) /* Console driver */ struct con_ops { diff --git a/include/debug_descriptor.h b/include/debug_descriptor.h index 3ac487b0..dfcf2686 100644 --- a/include/debug_descriptor.h +++ b/include/debug_descriptor.h @@ -20,6 +20,7 @@ struct debug_descriptor { /* Memory console */ __be64 memcons_phys; + __be64 uv_memcons_phys; __be32 memcons_tce; __be32 memcons_obuf_tce; __be32 memcons_ibuf_tce; diff --git a/include/mem-map.h b/include/mem-map.h index 15ec09ea..2384684b 100644 --- a/include/mem-map.h +++ b/include/mem-map.h @@ -91,16 +91,20 @@ #define INMEM_CON_START (SKIBOOT_BASE + 0x01000000) #define INMEM_CON_LEN 0x100000 -/* This is the location of HBRT console buffer at base + 17M */ -#define HBRT_CON_START (SKIBOOT_BASE + 0x01100000) +/* This is the location of our ultravisor console buffer at base + 17M */ +#define INMEM_UV_CON_START (SKIBOOT_BASE + 0x01100000) +#define INMEM_UV_CON_LEN 0x100000 + +/* This is the location of HBRT console buffer at base + 18M */ +#define HBRT_CON_START (SKIBOOT_BASE + 0x01200000) #define HBRT_CON_LEN 0x100000 -/* Tell FSP to put the init data at base + 20M, allocate 8M */ -#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01200000) +/* Tell FSP to put the init data at base + 19M, allocate 8M */ +#define SPIRA_HEAP_BASE (SKIBOOT_BASE + 0x01300000) #define SPIRA_HEAP_SIZE 0x00800000 /* This is our PSI TCE table. It's 256K entries on P8 */ -#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01a00000) +#define PSI_TCE_TABLE_BASE (SKIBOOT_BASE + 0x01c00000) #define PSI_TCE_TABLE_SIZE 0x00200000UL /* This is our dump result table after MPIPL. Hostboot will write to this @@ -119,7 +123,7 @@ * * (Ensure this has at least a 64k alignment) */ -#define SKIBOOT_SIZE 0x01c10000 +#define SKIBOOT_SIZE 0x01e00000 /* We start laying out the CPU stacks from here, indexed by PIR * each stack is STACK_SIZE in size (naturally aligned power of From patchwork Mon Jul 6 16:14:32 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323717 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rLr1WjTz9sRK for ; Tue, 7 Jul 2020 02:17:24 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rLr0jsYzDqhK for ; Tue, 7 Jul 2020 02:17:24 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4B0rK40bhvzDqfK for ; Tue, 7 Jul 2020 02:15:51 +1000 (AEST) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 066GE77J087245 for ; Mon, 6 Jul 2020 12:15:50 -0400 Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0b-001b2d01.pphosted.com with ESMTP id 322kcxknpc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 12:15:47 -0400 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 066Ft8Kn026365 for ; Mon, 6 Jul 2020 16:15:35 GMT Received: from b03cxnp08026.gho.boulder.ibm.com (b03cxnp08026.gho.boulder.ibm.com [9.17.130.18]) by ppma02wdc.us.ibm.com with ESMTP id 322hd8gqus-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:15:34 +0000 Received: from b03ledav001.gho.boulder.ibm.com (b03ledav001.gho.boulder.ibm.com [9.17.130.232]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GFVCi26739074 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:15:31 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C74706E053 for ; Mon, 6 Jul 2020 16:15:33 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7B1266E052 for ; Mon, 6 Jul 2020 16:15:33 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:15:33 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:32 -0400 Message-Id: <20200706161439.12635-6-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=13 spamscore=0 cotscore=-2147483648 mlxlogscore=999 mlxscore=0 malwarescore=0 clxscore=1015 bulkscore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 05/12] Add ultra call support for skiboot X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan A new type of system call called the ultra call is used to get the services of the ultravisor. This ultracall support is needed in skiboot to access the xscoms which are in the secure memory area. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj [ andmike: ABI change to switch from r0 to r3 ] Signed-off-by: Michael Anderson --- asm/misc.S | 29 +++++++++++++++++++++++++++++ include/ultravisor.h | 11 +++++++++++ 2 files changed, 40 insertions(+) diff --git a/asm/misc.S b/asm/misc.S index 30f67872..5119304a 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -275,6 +275,8 @@ enter_p9_pm_state: * PEF and bring it out of UV mode. All threads will then be running in HV * mode and the only way to re-enable UV mode is with a reboot. * + * Power9 hardware requires [h]srr1 to be set explicitly. + * * r3 = 1 if primary thread * 0 if secondary thread */ @@ -327,3 +329,30 @@ enter_uv: ld %r0,16(%r1) mtlr %r0 blr + +.global ucall +ucall: + mflr %r0 + stdu %r1,-STACK_FRAMESIZE(%r1) + std %r0,STACK_LR(%r1) + mfcr %r0 + stw %r0,STACK_CR(%r1) + std %r4,STACK_GPR4(%r1) /* Save ret buffer */ + mr %r4,%r5 + mr %r5,%r6 + mr %r6,%r7 + mr %r7,%r8 + mr %r8,%r9 + mr %r9,%r10 + sc 2 /* invoke the ultravisor */ + ld %r12,STACK_GPR4(%r1) + std %r4, 0(%r12) + std %r5, 8(%r12) + std %r6, 16(%r12) + std %r7, 24(%r12) + lwz %r0,STACK_CR(%r1) + mtcrf 0xff,%r0 + ld %r0,STACK_LR(%r1) + mtlr %r0 + addi %r1,%r1,STACK_FRAMESIZE + blr /* return r3 = status */ diff --git a/include/ultravisor.h b/include/ultravisor.h index 05edb53e..623b81d4 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -32,4 +32,15 @@ extern bool uv_present; void init_uv(void); +/* + * ucall: Make an ultracall + * @opcode: The ultracall to make + * @retbuf: Buffer to store up to 4 return arguments + * + * This call supports up to 6 arguments and 4 return arguments. Use + * UCALL_BUFSIZE to size the return argument buffer. + */ +#define UCALL_BUFSIZE 4 +extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); + #endif /* __ULTRAVISOR_H */ From patchwork Mon Jul 6 16:14:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323716 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rLS2bkqz9sSt for ; Tue, 7 Jul 2020 02:17:04 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rLR4ph2zDqcW for ; Tue, 7 Jul 2020 02:17:03 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4B0rK04yf4zDqf6 for ; Tue, 7 Jul 2020 02:15:48 +1000 (AEST) Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 066GDiVQ046833 for ; Mon, 6 Jul 2020 12:15:45 -0400 Received: from ppma02wdc.us.ibm.com (aa.5b.37a9.ip4.static.sl-reverse.com [169.55.91.170]) by mx0a-001b2d01.pphosted.com with ESMTP id 322nrtgmaw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 12:15:45 -0400 Received: from pps.filterd (ppma02wdc.us.ibm.com [127.0.0.1]) by ppma02wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 066FtBom026396 for ; Mon, 6 Jul 2020 16:15:44 GMT Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by ppma02wdc.us.ibm.com with ESMTP id 322hd8gqw7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:15:44 +0000 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GFihQ48562476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:15:44 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4B32D12405E for ; Mon, 6 Jul 2020 16:15:44 +0000 (GMT) Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2DBCA124054 for ; Mon, 6 Jul 2020 16:15:44 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:15:44 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:33 -0400 Message-Id: <20200706161439.12635-7-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 priorityscore=1501 suspectscore=1 mlxlogscore=783 impostorscore=0 cotscore=-2147483648 clxscore=1015 adultscore=0 spamscore=0 malwarescore=0 mlxscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 06/12] xscoms: read/write xscoms using ucall X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan xscom registers are in the secure memory area when secure mode is enabled. These registers cannot be accessed directly and need to use ultravisor services using ultracall. Signed-off-by: Madhavan Srinivasan Signed-off-by: Santosh Sivaraj [ linuxram: Set uv_present just after starting UV ] Signed-off-by: Ram Pai [ grimm: Don't check MSR in xscom read/write ] Signed-off-by: Ryan Grimm --- include/ultravisor.h | 21 +++++++++++++++++++++ include/xscom.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/include/ultravisor.h b/include/ultravisor.h index 623b81d4..84217d66 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * enter_uv: Each thread enters ultravisor and exits with S=0 @@ -43,4 +44,24 @@ void init_uv(void); #define UCALL_BUFSIZE 4 extern long ucall(unsigned long opcode, unsigned long *retbuf, ...); +#define UV_READ_SCOM 0xF114 +#define UV_WRITE_SCOM 0xF118 + +static inline int uv_xscom_read(u64 partid, u64 pcb_addr, u64 *val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + long rc; + + rc = ucall(UV_READ_SCOM, retbuf, partid, pcb_addr); + *val = retbuf[0]; + return rc; +} + +static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) +{ + unsigned long retbuf[UCALL_BUFSIZE]; + + return ucall(UV_WRITE_SCOM, retbuf, partid, pcb_addr, val); +} + #endif /* __ULTRAVISOR_H */ diff --git a/include/xscom.h b/include/xscom.h index bd8bb89a..67a845fd 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -7,6 +7,7 @@ #include #include #include +#include /* * SCOM "partID" definitions: @@ -174,9 +175,13 @@ extern void _xscom_unlock(void); /* Targeted SCOM access */ static inline int xscom_read(uint32_t partid, uint64_t pcb_addr, uint64_t *val) { + if (uv_present) + return uv_xscom_read(partid, pcb_addr, val); return _xscom_read(partid, pcb_addr, val, true); } static inline int xscom_write(uint32_t partid, uint64_t pcb_addr, uint64_t val) { + if (uv_present) + return uv_xscom_write(partid, pcb_addr, val); return _xscom_write(partid, pcb_addr, val, true); } extern int xscom_write_mask(uint32_t partid, uint64_t pcb_addr, uint64_t val, uint64_t mask); From patchwork Mon Jul 6 16:14:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323718 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rM64nrLz9sRK for ; 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Mon, 6 Jul 2020 12:15:56 -0400 Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com with ESMTP id 322nx5safd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 12:15:56 -0400 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 066Fss1w029588 for ; Mon, 6 Jul 2020 16:15:55 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma04wdc.us.ibm.com with ESMTP id 322hd8rq23-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:15:55 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GFs0931785382 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:15:54 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C374DAC067 for ; Mon, 6 Jul 2020 16:15:54 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9B2D3AC062 for ; Mon, 6 Jul 2020 16:15:54 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:15:54 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:34 -0400 Message-Id: <20200706161439.12635-8-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 priorityscore=1501 phishscore=0 impostorscore=0 bulkscore=0 spamscore=0 malwarescore=0 suspectscore=1 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 07/12] hdata/memory.c: Parse HDAT for secure memory X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The secure memory ranges are provided by the hostboot through HDAT. Skiboot parses HDAT and creates secure-memory@ device tree nodes. The secure-memory nodes set dev_type to "secure-memory" so the kernel doesn't try to use them. In the HDIF_ms_area_address_range structure, HDAT spec version 10.5, the mirror attribute at offset 0x14 is renamed to memory attribute. The memory attribute now defines byte 3 as secure memory whereas previously it was reserved. The rest of the attribute is unchanged: 1st byte -> Range is Mirrorable 0x00 = false 0x01 = true 2nd byte -> Hardware Mirroring Algorithm 0x0A – Memory Mirroring algorithm for P9 systems 0xFF – Memory Mirroring Not Supported 3rd byte -> SMF Memory 0x00 = false 0x01 = true 4th byte -> Reserved Signed-off-by: Ryan Grimm --- hdata/memory.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hdata/memory.c b/hdata/memory.c index bd47fee4..9443f297 100755 --- a/hdata/memory.c +++ b/hdata/memory.c @@ -32,7 +32,7 @@ struct HDIF_ms_area_address_range { __be64 start; __be64 end; __be32 chip; - __be32 mirror_attr; + __be32 memory_attr; __be64 mirror_start; __be32 controller_id; __be32 phys_attr; @@ -66,6 +66,9 @@ struct HDIF_ms_area_address_range { #define MS_CONTROLLER_MCC_ID(id) GETFIELD(PPC_BITMASK32(8, 15), id) #define MS_CONTROLLER_OMI_ID(id) GETFIELD(PPC_BITMASK32(16, 31), id) +#define MS_ATTR_PEF PPC_BIT32(23) +#define UV_SECURE_MEM_BIT PPC_BIT(15) + struct HDIF_ms_area_id { __be16 id; #define MS_PTYPE_RISER_CARD 0x8000 @@ -150,10 +153,10 @@ static bool add_address_range(struct dt_node *root, chip_id = pcid_to_chip_id(be32_to_cpu(arange->chip)); prlog(PR_DEBUG, " Range: 0x%016llx..0x%016llx " - "on Chip 0x%x mattr: 0x%x pattr: 0x%x status:0x%x\n", + "on Chip 0x%x memattr: 0x%08x pattr: 0x%x status:0x%x\n", (long long)be64_to_cpu(arange->start), (long long)be64_to_cpu(arange->end), - chip_id, be32_to_cpu(arange->mirror_attr), + chip_id, be32_to_cpu(arange->memory_attr), mem_type, mem_status); /* reg contains start and length */ @@ -182,6 +185,13 @@ static bool add_address_range(struct dt_node *root, return false; } + if (be32_to_cpu(arange->memory_attr) & MS_ATTR_PEF) { + prlog(PR_DEBUG, "HDAT: Found secure memory\n"); + name = "secure-memory"; + dev_type = "secure-memory"; + compat = "ibm,secure-memory"; + } + if (be16_to_cpu(id->flags) & MS_AREA_SHARED) { mem = dt_find_by_name_addr(dt_root, name, reg[0]); if (mem) { From patchwork Mon Jul 6 16:14:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323719 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rMN1TYPz9sRK for ; Tue, 7 Jul 2020 02:17:52 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rMN12rmzDqgk for ; Tue, 7 Jul 2020 02:17:52 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; 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Mon, 6 Jul 2020 16:16:05 GMT Received: from b01cxnp22033.gho.pok.ibm.com (b01cxnp22033.gho.pok.ibm.com [9.57.198.23]) by ppma05wdc.us.ibm.com with ESMTP id 322hd8rrfy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:16:05 +0000 Received: from b01ledav003.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp22033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GG5Tu52101596 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:16:05 GMT Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3A505B2066 for ; Mon, 6 Jul 2020 16:16:05 +0000 (GMT) Received: from b01ledav003.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11965B206B for ; Mon, 6 Jul 2020 16:16:05 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b01ledav003.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:16:04 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:35 -0400 Message-Id: <20200706161439.12635-9-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=1 clxscore=1015 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 08/12] hdata/spira.c: Create ibm, ultravisor dt node X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Create ibm,ultravisor node if secure memory exists. See doc/opal-uv-abi.rst for details. Signed-off-by: Ryan Grimm --- hdata/spira.c | 30 ++++++++++++++++++++++++++++++ include/ultravisor.h | 2 ++ 2 files changed, 32 insertions(+) diff --git a/hdata/spira.c b/hdata/spira.c index 35d6109d..9d0ea6d6 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -17,6 +17,7 @@ #include "hostservices.h" #include "naca.h" #include "spira.h" +#include /* Processor Initialization structure, contains * the initial NIA and MSR values for the entry @@ -1650,6 +1651,32 @@ static void add_npus(void) } } +static void add_uv(void) +{ + struct dt_node *uv_node, *secure_mem_node, *uv_fw_node; + uint64_t uv_fw_start; + char fw_name[64]; + + secure_mem_node = dt_find_compatible_node_on_chip(dt_root, NULL, + "ibm,secure-memory", 0); + if (!secure_mem_node) { + prlog(PR_DEBUG, "HDAT: No ibm,secure-memory found\n"); + return; + } + + uv_node = dt_new_check(dt_root, "ibm,ultravisor"); + dt_add_property_string(uv_node, "compatible", "ibm,ultravisor"); + dt_add_property_cells(uv_node, "#address-cells", 2); + dt_add_property_cells(uv_node, "#size-cells", 2); + + uv_fw_start = dt_get_address(secure_mem_node, 0, NULL); + + snprintf(fw_name, 64, "firmware@%llx", (unsigned long long)uv_fw_start); + uv_fw_node = dt_new_check(uv_node, fw_name); + dt_add_property_string(uv_fw_node, "compatible", "ibm,uv-firmware"); + dt_add_property_u64s(uv_fw_node, "reg", uv_fw_start, UV_LOAD_MAX_SIZE); +} + /* * Legacy SPIRA is being deprecated and we have new SPIRA-H/S structures. * But on older system (p7?) we will continue to get legacy SPIRA. @@ -1754,6 +1781,9 @@ int parse_hdat(bool is_opal) /* Parse MS VPD */ memory_parse(); + /* Add UV node if secure memory exists */ + add_uv(); + /* Add any FSPs */ fsp_parse(); diff --git a/include/ultravisor.h b/include/ultravisor.h index 84217d66..d2fbb2f9 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -64,4 +64,6 @@ static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) return ucall(UV_WRITE_SCOM, retbuf, partid, pcb_addr, val); } +#define UV_LOAD_MAX_SIZE 0x200000 + #endif /* __ULTRAVISOR_H */ From patchwork Mon Jul 6 16:14:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323720 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rMg35xBz9sSd for ; Tue, 7 Jul 2020 02:18:07 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rMg288WzDqtR for ; Tue, 7 Jul 2020 02:18:07 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; 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Mon, 6 Jul 2020 16:16:16 GMT Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by ppma02dal.us.ibm.com with ESMTP id 322hd8vuye-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:16:16 +0000 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GGFQe14025460 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:16:15 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A25E4112069 for ; Mon, 6 Jul 2020 16:16:15 +0000 (GMT) Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7B855112062 for ; Mon, 6 Jul 2020 16:16:15 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:16:15 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:36 -0400 Message-Id: <20200706161439.12635-10-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=3 clxscore=1015 impostorscore=0 mlxscore=0 malwarescore=0 mlxlogscore=915 priorityscore=1501 lowpriorityscore=0 spamscore=0 bulkscore=0 phishscore=0 adultscore=0 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 09/12] core/mem_region.c: Implement local free X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Signed-off-by: Ryan Grimm --- core/mem_region.c | 32 ++++++++++++++++++++++++++++++++ include/mem_region-malloc.h | 3 +++ 2 files changed, 35 insertions(+) diff --git a/core/mem_region.c b/core/mem_region.c index 36de2d09..aefea8d2 100644 --- a/core/mem_region.c +++ b/core/mem_region.c @@ -920,6 +920,38 @@ restart: return p; } +void __local_free(void *p, const char *location) +{ + struct mem_region *region; + struct alloc_hdr *hdr; + + if (!p) + return; + + lock(&mem_region_lock); + + list_for_each(®ions, region, list) { + /* local_alloc doesn't use heap */ + if (region == &skiboot_heap) + continue; + + if (p >= region_start(region) && + (p < (region_start(region) + region->len))) { + hdr = p - sizeof(*hdr); + + if (hdr->free) + bad_header(region, hdr, "re-freed", location); + + lock(®ion->free_list_lock); + make_free(region, (struct free_hdr *)hdr, location, false); + unlock(®ion->free_list_lock); + } + + } + + unlock(&mem_region_lock); +} + struct mem_region *find_mem_region(const char *name) { struct mem_region *region; diff --git a/include/mem_region-malloc.h b/include/mem_region-malloc.h index 271311b2..cf64eb25 100644 --- a/include/mem_region-malloc.h +++ b/include/mem_region-malloc.h @@ -28,4 +28,7 @@ void *__local_alloc(unsigned int chip, size_t size, size_t align, #define local_alloc(chip_id, size, align) \ __local_alloc((chip_id), (size), (align), __location__) +void __local_free(void *ptr, const char *location); +#define local_free(ptr) __local_free(ptr, __location__); + #endif /* __MEM_REGION_MALLOC_H */ From patchwork Mon Jul 6 16:14:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323721 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rN03glBz9sSd for ; Tue, 7 Jul 2020 02:18:24 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rN02pkHzDqwH for ; Tue, 7 Jul 2020 02:18:24 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; 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Mon, 6 Jul 2020 16:16:26 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:37 -0400 Message-Id: <20200706161439.12635-11-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 mlxlogscore=999 suspectscore=3 clxscore=1015 cotscore=-2147483648 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 10/12] Load the ultravisor from flash and decompress X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The ultravisor, labeled UVISOR is preloaded from the PNOR in main_cpu_entry after the kernel is preloaded. This also works on FSP-based systems with an ultra.lid on the FSP. Skiboot decompresses it later in init_uv. Signed-off-by: Santosh Sivaraj Signed-off-by: Ryan Grimm --- core/flash.c | 1 + core/init.c | 1 + hw/fsp/fsp.c | 2 + hw/ultravisor.c | 95 +++++++++++++++++++++++++++++++++++++++----- include/platform.h | 1 + include/ultravisor.h | 3 ++ 6 files changed, 93 insertions(+), 10 deletions(-) diff --git a/core/flash.c b/core/flash.c index de748641..bc44a4e5 100644 --- a/core/flash.c +++ b/core/flash.c @@ -45,6 +45,7 @@ static struct { { RESOURCE_ID_INITRAMFS,RESOURCE_SUBID_NONE, "ROOTFS" }, { RESOURCE_ID_CAPP, RESOURCE_SUBID_SUPPORTED, "CAPP" }, { RESOURCE_ID_IMA_CATALOG, RESOURCE_SUBID_SUPPORTED, "IMA_CATALOG" }, + { RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, "UVISOR" }, { RESOURCE_ID_VERSION, RESOURCE_SUBID_NONE, "VERSION" }, { RESOURCE_ID_KERNEL_FW, RESOURCE_SUBID_NONE, "BOOTKERNFW" }, }; diff --git a/core/init.c b/core/init.c index e0166098..d9a181a7 100644 --- a/core/init.c +++ b/core/init.c @@ -1315,6 +1315,7 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) preload_capp_ucode(); start_preload_kernel(); + uv_preload_image(); /* Catalog decompression routine */ imc_decompress_catalog(); diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index 70452cf9..7b564f93 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -114,6 +114,7 @@ static u64 fsp_hir_timeout; #define KERNEL_LID_PHYP 0x80a00701 #define KERNEL_LID_OPAL 0x80f00101 #define INITRAMFS_LID_OPAL 0x80f00102 +#define ULTRA_LID_OPAL 0x80f00105 /* * We keep track on last logged values for some things to print only on @@ -2381,6 +2382,7 @@ static struct { } fsp_lid_map[] = { { RESOURCE_ID_KERNEL, RESOURCE_SUBID_NONE, KERNEL_LID_OPAL }, { RESOURCE_ID_INITRAMFS,RESOURCE_SUBID_NONE, INITRAMFS_LID_OPAL }, + { RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, ULTRA_LID_OPAL }, { RESOURCE_ID_IMA_CATALOG,IMA_CATALOG_NIMBUS, 0x80f00103 }, { RESOURCE_ID_CAPP, CAPP_IDX_MURANO_DD20, 0x80a02002 }, { RESOURCE_ID_CAPP, CAPP_IDX_MURANO_DD21, 0x80a02001 }, diff --git a/hw/ultravisor.c b/hw/ultravisor.c index 467f0ca6..34c16404 100644 --- a/hw/ultravisor.c +++ b/hw/ultravisor.c @@ -10,11 +10,16 @@ #include #include #include +#include +#include static struct dt_node *uv_fw_node; static uint64_t uv_base_addr; bool uv_present; +static char *uv_image = NULL; +static size_t uv_image_size; + struct memcons uv_memcons __section(".data.memcons") = { .magic = MEMCONS_MAGIC, .obuf_phys = INMEM_UV_CON_START, @@ -70,10 +75,44 @@ int start_ultravisor(void *fdt) return OPAL_SUCCESS; } +static int uv_decompress_image(void) +{ + struct xz_decompress uv_xz; + uint64_t uv_fw_size; + + if (!uv_image) { + prerror("UV: Preload hasn't started yet! Aborting.\n"); + return OPAL_INTERNAL_ERROR; + } + + if (wait_for_resource_loaded(RESOURCE_ID_UV_IMAGE, + RESOURCE_SUBID_NONE) != OPAL_SUCCESS) { + prerror("UV: Ultravisor image load failed\n"); + return OPAL_INTERNAL_ERROR; + } + + uv_xz.dst = (void *)dt_get_address(uv_fw_node, 0, &uv_fw_size); + uv_xz.dst_size = uv_fw_size; + uv_xz.src_size = uv_image_size; + uv_xz.src = uv_image; + + if (stb_is_container((void*)uv_xz.src, uv_xz.src_size)) + uv_xz.src = uv_xz.src + SECURE_BOOT_HEADERS_SIZE; + + xz_start_decompress(&uv_xz); + if ((uv_xz.status != OPAL_PARTIAL) && (uv_xz.status != OPAL_SUCCESS)) { + prerror("UV: XZ decompression failed status 0x%x\n", uv_xz.status); + return OPAL_INTERNAL_ERROR; + } + + return OPAL_SUCCESS; +} + void init_uv() { uint64_t uv_dt_src, uv_fw_sz; struct dt_node *reserved_mem; + int ret; if (!is_msr_bit_set(MSR_S)) { prlog(PR_DEBUG, "UV: S bit not set\n"); @@ -84,23 +123,59 @@ void init_uv() if (!uv_fw_node) { prlog(PR_DEBUG, "UV: No ibm,uv-firmware node found, disabling pef\n"); cpu_disable_pef(); - return; + goto err; } - reserved_mem = dt_find_by_path(dt_root, "/reserved-memory/ibm,uv-firmware"); - if (!reserved_mem) { - prerror("UV: No reserved memory for ibm,uv-firmware found\n"); - return; - } + /* If decompress fails, look for reserved memory by Mambo tcl or cronus BML */ + ret = uv_decompress_image(); + if (ret) { + reserved_mem = dt_find_by_path(dt_root, "/reserved-memory/ibm,uv-firmware"); + if (!reserved_mem) { + prerror("UV: No reserved memory for ibm,uv-firmware found\n"); + return; + } - uv_dt_src = dt_get_address(reserved_mem, 0, &uv_fw_sz); - uv_base_addr = dt_get_address(uv_fw_node, 0, NULL); + uv_dt_src = dt_get_address(reserved_mem, 0, &uv_fw_sz); + uv_base_addr = dt_get_address(uv_fw_node, 0, NULL); - prlog(PR_INFO, "UV: Copying 0x%llx bytes to protected memory 0x%llx from 0x%llx\n", + prlog(PR_INFO, "UV: Copying 0x%llx bytes to protected memory 0x%llx from 0x%llx\n", uv_fw_sz, uv_base_addr, uv_dt_src); - memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); + memcpy((void *)uv_base_addr, (void *)uv_dt_src, uv_fw_sz); + } dt_add_property_u64(uv_fw_node, "memcons", (u64)&uv_memcons); debug_descriptor.uv_memcons_phys = (u64)&uv_memcons; +err: + local_free(uv_image); +} + +/* + * Preload the UV image from PNOR partition + * + * uv_image is allocated locally to the chip and freed here if preload fails + * or free in init_uv + */ +void uv_preload_image(void) +{ + struct proc_chip *chip = next_chip(NULL); + int ret; + + prlog(PR_DEBUG, "UV: Preload starting\n"); + + uv_image_size = MAX_COMPRESSED_UV_IMAGE_SIZE; + uv_image = local_alloc(chip->id, uv_image_size, uv_image_size); + if (!uv_image) { + prerror("UV: Memory allocation failed\n"); + return; + } + memset(uv_image, 0, uv_image_size); + + ret = start_preload_resource(RESOURCE_ID_UV_IMAGE, RESOURCE_SUBID_NONE, + uv_image, &uv_image_size); + + if (ret != OPAL_SUCCESS) { + local_free(uv_image); + prerror("UV: platform load failed: %d\n", ret); + } } diff --git a/include/platform.h b/include/platform.h index ef93278b..57b2eeef 100644 --- a/include/platform.h +++ b/include/platform.h @@ -17,6 +17,7 @@ enum resource_id { RESOURCE_ID_INITRAMFS, RESOURCE_ID_CAPP, RESOURCE_ID_IMA_CATALOG, + RESOURCE_ID_UV_IMAGE, RESOURCE_ID_VERSION, RESOURCE_ID_KERNEL_FW, }; diff --git a/include/ultravisor.h b/include/ultravisor.h index d2fbb2f9..23e14b2c 100644 --- a/include/ultravisor.h +++ b/include/ultravisor.h @@ -66,4 +66,7 @@ static inline int uv_xscom_write(u64 partid, u64 pcb_addr, u64 val) #define UV_LOAD_MAX_SIZE 0x200000 +#define MAX_COMPRESSED_UV_IMAGE_SIZE 0x40000 /* 256 Kilobytes */ +void uv_preload_image(void); + #endif /* __ULTRAVISOR_H */ From patchwork Mon Jul 6 16:14:38 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323722 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rNK0Kjfz9sRK for ; Tue, 7 Jul 2020 02:18:41 +1000 (AEST) Authentication-Results: ozlabs.org; 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Mon, 6 Jul 2020 16:16:37 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2817ABE053 for ; Mon, 6 Jul 2020 16:16:37 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:16:37 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:38 -0400 Message-Id: <20200706161439.12635-12-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=13 clxscore=1015 cotscore=-2147483648 mlxlogscore=999 impostorscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 priorityscore=1501 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060119 Subject: [Skiboot] [RFC PATCH v7 11/12] skiboot/imc: Disable IMC node when UV enabled X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Madhavan Srinivasan Don't create the IMC nodes when the ultravisor is enabled. Hypervisor IMC initialization requires access to HOMER and IMC scoms which are protected and only accessable via ultra calls. So, don't create them until the kernel supports the ultra calls. Signed-off-by: Madhavan Srinivasan [ grimm: move S bit check to beginning of function ] [ grimm: comments and commit message ] Signed-off-by: Ryan Grimm --- hw/imc.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/imc.c b/hw/imc.c index 927fba0b..f6351225 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -527,6 +527,16 @@ void imc_init(void) struct dt_node *dev; int err_flag = -1; + /* + * If MSR(S) bit is set, HOMER and IMC scoms are only accessible via + * ultra call. The kernels lacks support, so don't create them. + * + * At this point uv_present can't be used since uv_init() + * is called much later, so check the MSR bit. + */ + if (is_msr_bit_set(MSR_S)) + return; + if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { dev = dt_find_compatible_node(dt_root, NULL, "ibm,opal-in-memory-counters"); From patchwork Mon Jul 6 16:14:39 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan Grimm X-Patchwork-Id: 1323723 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4B0rNb6k2Cz9sRK for ; Tue, 7 Jul 2020 02:18:55 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4B0rNb5t2pzDr34 for ; Tue, 7 Jul 2020 02:18:55 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=grimm@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4B0rLD0lBLzDqcq for ; Tue, 7 Jul 2020 02:16:51 +1000 (AEST) Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 066GDed4083704 for ; Mon, 6 Jul 2020 12:16:49 -0400 Received: from ppma04dal.us.ibm.com (7a.29.35a9.ip4.static.sl-reverse.com [169.53.41.122]) by mx0b-001b2d01.pphosted.com with ESMTP id 322kx970ax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 12:16:49 -0400 Received: from pps.filterd (ppma04dal.us.ibm.com [127.0.0.1]) by ppma04dal.us.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 066FuHPK030643 for ; Mon, 6 Jul 2020 16:16:48 GMT Received: from b01cxnp22034.gho.pok.ibm.com (b01cxnp22034.gho.pok.ibm.com [9.57.198.24]) by ppma04dal.us.ibm.com with ESMTP id 322hd8mw4d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jul 2020 16:16:48 +0000 Received: from b01ledav006.gho.pok.ibm.com (b01ledav006.gho.pok.ibm.com [9.57.199.111]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 066GGmZg54329702 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Mon, 6 Jul 2020 16:16:48 GMT Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 05C44AC059 for ; Mon, 6 Jul 2020 16:16:48 +0000 (GMT) Received: from b01ledav006.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D32E7AC05B for ; Mon, 6 Jul 2020 16:16:47 +0000 (GMT) Received: from alain.ibm.com (unknown [9.85.164.109]) by b01ledav006.gho.pok.ibm.com (Postfix) with ESMTP for ; Mon, 6 Jul 2020 16:16:47 +0000 (GMT) From: Ryan Grimm To: skiboot@lists.ozlabs.org Date: Mon, 6 Jul 2020 12:14:39 -0400 Message-Id: <20200706161439.12635-13-grimm@linux.ibm.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20200706161439.12635-1-grimm@linux.ibm.com> References: <20200706161439.12635-1-grimm@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-06_12:2020-07-06, 2020-07-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 adultscore=0 mlxscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 spamscore=0 cotscore=-2147483648 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=3 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2004280000 definitions=main-2007060118 Subject: [Skiboot] [RFC PATCH v7 12/12] Add obsolete secure-memory-ranges property X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Upstream kernel code looks for this so keep compatibility till it's safe to remove. Signed-off-by: Ryan Grimm --- hdata/spira.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/hdata/spira.c b/hdata/spira.c index 9d0ea6d6..5ba1ff13 100644 --- a/hdata/spira.c +++ b/hdata/spira.c @@ -1651,6 +1651,34 @@ static void add_npus(void) } } +static void add_obsolete_uv_prop(struct dt_node *uv_node) +{ + uint64_t secure_start, secure_size; + struct dt_node *np; + int num_ranges = 0; + uint64_t *ranges; + int i = 0; + + dt_for_each_compatible(dt_root, np, "ibm,secure-memory") + num_ranges++; + + ranges = malloc(num_ranges * sizeof(ranges) * 2); + if (!ranges) { + prerror("UV: Malloc failed"); + return; + } + + dt_for_each_compatible(dt_root, np, "ibm,secure-memory") { + secure_start = dt_get_address(np, 0, &secure_size); + ranges[i] = secure_start; + ranges[i++] = secure_size; + } + + dt_add_property(uv_node, "secure-memory-ranges", + ranges, sizeof(ranges)); + free(ranges); +} + static void add_uv(void) { struct dt_node *uv_node, *secure_mem_node, *uv_fw_node; @@ -1675,6 +1703,8 @@ static void add_uv(void) uv_fw_node = dt_new_check(uv_node, fw_name); dt_add_property_string(uv_fw_node, "compatible", "ibm,uv-firmware"); dt_add_property_u64s(uv_fw_node, "reg", uv_fw_start, UV_LOAD_MAX_SIZE); + + add_obsolete_uv_prop(uv_fw_node); } /*