From patchwork Wed Sep 6 16:59:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suneel Garapati X-Patchwork-Id: 810731 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="gHDpPWFE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xnVF02Lymz9t2d for ; Thu, 7 Sep 2017 02:59:48 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 08932C21EFD; Wed, 6 Sep 2017 16:59:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CC15DC21E3B; Wed, 6 Sep 2017 16:59:43 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5F8FAC21E3B; Wed, 6 Sep 2017 16:59:43 +0000 (UTC) Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by lists.denx.de (Postfix) with ESMTPS id C8CE1C21E11 for ; Wed, 6 Sep 2017 16:59:42 +0000 (UTC) Received: by mail-pf0-f195.google.com with SMTP id m1so3313503pfk.0 for ; Wed, 06 Sep 2017 09:59:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=PifiLok7libgwTrLIjATtIM5d4JpKuq/4U0m9t2C8DQ=; b=gHDpPWFEMNgvcnt4U6JZ1ZMAfxXcX9wOAL5+gVwDDLFqVbe7IEGBI7njcJuA/eQx2U 8Klso+N99wVGHlJTyf2eCaSZgtxBR/eBpvZhCjMp7hV4CzhVAZRF7tPdhcWee/K2T5vD nsvLaA4ikWqlDvcmgnZwX1Coy+OwAeBT9ShSfEyU+SiKn89fTuZd0RS1cgeyJuzlqdnv rbus1Kf3UQEJ2XK12I99oT1xc+huEX1Sz1P3xCCd9UeRyP2HbonQYNlIsErodTQ9rMEP +SMeENiFRRGQXOFZOSdpVUBK3c5q9PPsVK4eucBZH9oqNuohGh4PL1SSZTVKAU+Y64Sm F80g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=PifiLok7libgwTrLIjATtIM5d4JpKuq/4U0m9t2C8DQ=; b=dwg/QZyLIOGg5tYV2b63qB6ggx1suVGxofh+mCj4ux6LuRNEvqlVbNliQ5qIl+zccZ 5RPqWOdQNKkYhPlxwyKBu6CpIRMVnmUg6jVr4LXvUxaiYeAP6232X7L2MEfnYfIz9sMS pfDAxx2s97OAcUvdw0FCx4T5xGWerJ7fklUtw6/Wpms+OAABRo2z+DD9h3KuM/+Q8xdC rSQ0MDVEuaXCZkC9GZgwEaQhmTD8H5bhzUWu0oi/9NWOIWwL2GO2z0Es6JrUsK3v2CdB btzEGXzOcLifx+NzeSCol8tVeaevdp0AWNTIwVdIHrdUnKAWi6Mwo4wc3xc4eDu86/tF VKLg== X-Gm-Message-State: AHPjjUgF5b+cgj7nRI8zIVsKb82qwcupaDDCazZhCzGs0mw6ePJTYuMF owZkKawzz9sHIj2Y X-Google-Smtp-Source: ADKCNb5DSEKQSEXv10TuPZAQd/RvuiRJUPvHwMBOjCqP30C9rnY9HE4G+u9iDAj7TbphxFHcUpS/Zg== X-Received: by 10.98.33.134 with SMTP id o6mr7931207pfj.103.1504717181155; Wed, 06 Sep 2017 09:59:41 -0700 (PDT) Received: from suneel.hsd1.ca.comcast.net ([2601:646:8e00:e521:a8ab:948d:75cf:79c4]) by smtp.gmail.com with ESMTPSA id j10sm365556pfj.116.2017.09.06.09.59.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 06 Sep 2017 09:59:40 -0700 (PDT) From: Suneel Garapati To: Bin Meng Date: Wed, 6 Sep 2017 09:59:35 -0700 Message-Id: <1504717175-11844-1-git-send-email-suneelglinux@gmail.com> X-Mailer: git-send-email 2.7.4 Cc: u-boot@lists.denx.de, Michal Simek Subject: [U-Boot] [PATCH v1] drivers: ahci: write upper 32 bits for clb and fis registers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If 64-bit capability is supported, commandlistbase and fis base should be split as lower32 and upper32. upper32 should be written to PORT_(LST/FIS)_ADDR_HI. Signed-off-by: Suneel Garapati Reviewed-by: Simon Glass --- Changes v1: - add macro definitions for LOWER32, UPPER32 drivers/ata/ahci.c | 14 ++++++++++++-- include/ahci.h | 1 + 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 5e4df19..178d9a7 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -27,6 +27,9 @@ #include #include +#define LOWER32(val) (u32)((u64)(val) & 0xFFFFFFFF) +#define UPPER32(val) (u32)(((u64)(val) & 0xFFFFFFFF00000000ULL) >> 32) + static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); #ifndef CONFIG_DM_SCSI @@ -607,10 +610,17 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port) pp->cmd_tbl_sg = (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); - writel_with_flush((unsigned long)pp->cmd_slot, + if (uc_priv->cap & HOST_CAP_64) + writel_with_flush(cpu_to_le32(UPPER32(pp->cmd_slot)), + port_mmio + PORT_LST_ADDR_HI); + writel_with_flush(cpu_to_le32(LOWER32(pp->cmd_slot)), port_mmio + PORT_LST_ADDR); - writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); + if (uc_priv->cap & HOST_CAP_64) + writel_with_flush(cpu_to_le32(UPPER32(pp->rx_fis)), + port_mmio + PORT_FIS_ADDR_HI); + writel_with_flush(cpu_to_le32(LOWER32(pp->rx_fis)), + port_mmio + PORT_FIS_ADDR); #ifdef CONFIG_SUNXI_AHCI sunxi_dma_init(port_mmio); diff --git a/include/ahci.h b/include/ahci.h index 33171b7..80e7f13 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -40,6 +40,7 @@ #define HOST_RESET (1 << 0) /* reset controller; self-clear */ #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ +#define HOST_CAP_64 (1 << 31) /* 64bit addressing capability */ /* Registers for each SATA port */ #define PORT_LST_ADDR 0x00 /* command list DMA addr */