From patchwork Thu Dec 14 13:45:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 848556 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="KzTlmowQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yyFGd4zLSz9t2f for ; Fri, 15 Dec 2017 00:46:49 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752718AbdLNNqq (ORCPT ); Thu, 14 Dec 2017 08:46:46 -0500 Received: from mail-qk0-f195.google.com ([209.85.220.195]:46704 "EHLO mail-qk0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752888AbdLNNpw (ORCPT ); Thu, 14 Dec 2017 08:45:52 -0500 Received: by mail-qk0-f195.google.com with SMTP id b184so6256417qkc.13; Thu, 14 Dec 2017 05:45:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jwtAZI/OXUgPcvCQ5VmN26UT+1uEyHPR34Tu/5g0/4Y=; b=KzTlmowQ+SbMIcMJQK8oi5gn6Zdkhz27WXwFEU/pu0bccfRVOWfv/jnJmZuWBheC+C oNsLPvV9lUS0j9IfWqknXTBrDc0mJnl5iFtOpm+1ZfqiqSF3SQa0++2wSFdClqAUoFEz 3sHcAJ3Qoyk/uyMpMb+F2kMmKp9/v+sUS/kUBrZX5Bi1GyFLuBr/lxaqt92mr/UKnGxs VKbDLH2HsWKskqO4X2HVm9LgtIWTUtz/a6ZIsibnk53TgXGwEc1VJpWqcfT0Dvh6/k69 QT5ou+MH80w1U+DTxqx8Alq6Q6Lq7WiZRMaOtY376YOTuv8iGyGqyTuidxjt6TxR05JD C7sQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jwtAZI/OXUgPcvCQ5VmN26UT+1uEyHPR34Tu/5g0/4Y=; b=W05SD7ARtjJ2H+N7giLmlUXCndU30Z8TTXdPNzXka3PypBdOjGv+52cXa4SIt5VOSs wCWGk7j1nx7FR2M0ZWXbOkxnn3rRDjjr1faWvRpBIKpYDBFCyk6C41p19PZxNSU5h7sU X92zog9beMmR1vRzjnvD0IzcYO97sxaBMX5M9isgMSHIAYdzMbwXrD6mS+pyFaoB0rlB g0f6g3hjpvHUF3bX2rIFelMrNVvGJDbJ9h5y6b7CpMjbC38jIP+1IxiqPLKxB0vRlL/a X1JMo9NebB0sfENz2OgrwIPZFl7gyqM4I/fEVdqVYDr1/6oF8RMrYcgd9f1EgEv6v8iX IXnQ== X-Gm-Message-State: AKGB3mIC2ve0SIqoooenEwC/8f0RlxtLKYXuU+hSJhZ9qKIiYc1A3FJV 0vK8j3eOChYpI/D4fRkM13jLZQ== X-Google-Smtp-Source: ACJfBovmkVJOt3v52BvB3eZfvbtGqR7Y/9qEBeScWNoQ+oyv9bOezpFfbDwBL5PVkjgwFdZTkGjgNA== X-Received: by 10.55.191.135 with SMTP id p129mr16254917qkf.211.1513259151384; Thu, 14 Dec 2017 05:45:51 -0800 (PST) Received: from localhost (p200300E41F200F003F65F430A8AE2E44.dip0.t-ipconnect.de. [2003:e4:1f20:f00:3f65:f430:a8ae:2e44]) by smtp.gmail.com with ESMTPSA id y135sm2664594qka.48.2017.12.14.05.45.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Dec 2017 05:45:50 -0800 (PST) From: Thierry Reding To: Lorenzo Pieralisi , Bjorn Helgaas Cc: Jonathan Hunter , Vidya Saga , Manikanta Maddireddy , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 1/4] PCI: tegra: Clarify configuration space address computations Date: Thu, 14 Dec 2017 14:45:42 +0100 Message-Id: <20171214134545.11143-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171214134545.11143-1-thierry.reding@gmail.com> References: <20171214134545.11143-1-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thierry Reding Tegra uses a non-compatible variant of ECAM where the extended register field is separate from the register field. Clarify that the register offset also factors into the computation of the configuration space addresses. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index f6d0430e6704..8a07c6f9e1b0 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -364,11 +364,13 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) * * Mapping the whole extended configuration space would require 256 MiB of * virtual address space, only a small part of which will actually be used. - * To work around this, a 4K of region is used to generate required - * configuration transaction with relevant B:D:F values. This is achieved by - * dynamically programming base address and size of AFI_AXI_BAR used for - * end point config space mapping to make sure that the address (access to - * which generates correct config transaction) falls in this 4K region + * + * To work around this, a 4 KiB region is used to generate the required + * configuration transaction with relevant B:D:F and register offset values. + * This is achieved by dynamically programming base address and size of + * AFI_AXI_BAR used for end point config space mapping to make sure that the + * address (access to which generates correct config transaction) falls in + * this 4 KiB region. */ static unsigned long tegra_pcie_conf_offset(unsigned char b, unsigned int devfn, int where) From patchwork Thu Dec 14 13:45:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 848548 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="L+g+gs/w"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yyFFl1RVDz9t2f for ; Fri, 15 Dec 2017 00:46:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753168AbdLNNp5 (ORCPT ); Thu, 14 Dec 2017 08:45:57 -0500 Received: from mail-qk0-f196.google.com ([209.85.220.196]:41464 "EHLO mail-qk0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753129AbdLNNpz (ORCPT ); Thu, 14 Dec 2017 08:45:55 -0500 Received: by mail-qk0-f196.google.com with SMTP id 84so6254591qks.8; Thu, 14 Dec 2017 05:45:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RdZ1uFShzY+JuTwN6tgcRkGXXuykHcWSr3kpHuIQqQM=; b=L+g+gs/wTvUaT+jgfJpi0eUxraRI7Xsu/ff2ZfPxn2lTrSO0zrYWnaYvueA1mMGl9F HM/ILKe/3vbV8DHs+ePAAew1mcIS7UgZl2oXvZ7SinwLxfyfJp4l9LiWn72sqtuAhIS7 anuv1uUtp2DtnJTFGxQg8RdCIUm3o7srBpF1I+FrgFTg1mcq9mQ7OyTWalPQcsLXVAcz Urgc9C1JT5qM4yUqlbsIXv6nf7auMG4xpiXUYaau15bn6JF0Np1NLXCrvMnQlIsDnD6t pIvBLALJO82jCdg189bZ/pQNpHQcFomoqqvRoSGkIqXyrN/dxU5DtTdI/ZC5Pao9KYeh nM5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RdZ1uFShzY+JuTwN6tgcRkGXXuykHcWSr3kpHuIQqQM=; b=mz62awptdoeLd9CzHXTNHyRspu7FmMoC6CPz/0Md42Vt0c0N2/XvdjCVy/E8nal2e1 0GhjHfp6y4UlG5Kts9JYqm0L1rlQ4LM1qXchCulUNSu+MuA6roAAfcDDHNjZ2j4vMK0q bXfdhy2IAOJp/awwbKBmVP2CZQBCi4IXTVNX87t69XnEO9kFxvSpjY33MK6dZxdz96FU TRjQLlZXJ/9b2tevKAfaDEykGHMia0307sgffPvXJ4OC8NWhVUuzsXkkTREy4x3PSiFF NIWV/yQHEibPk/No7VLP0IDnLJwW9/rvkODPtS8ZcpPnAmQMQwXv3Jvtrm47Mb24ycFu k6jg== X-Gm-Message-State: AKGB3mJSUqbj+WsI6mmrCmgVFWHwfC5/vPn50wbX/VIV5AW6tYZLzY28 L3MYZ0P8yhTBwESfAFqQmWg= X-Google-Smtp-Source: ACJfBosN0/hRMJrl+S40QRlfha/iTo3y87tt0MVpqxfbcMXQz+IJ9QFqMPDdlyrr0aTd0LtCt6Phzg== X-Received: by 10.55.156.17 with SMTP id f17mr15946508qke.217.1513259154434; Thu, 14 Dec 2017 05:45:54 -0800 (PST) Received: from localhost (p200300E41F200F003F65F430A8AE2E44.dip0.t-ipconnect.de. [2003:e4:1f20:f00:3f65:f430:a8ae:2e44]) by smtp.gmail.com with ESMTPSA id w41sm2509581qtc.19.2017.12.14.05.45.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Dec 2017 05:45:53 -0800 (PST) From: Thierry Reding To: Lorenzo Pieralisi , Bjorn Helgaas Cc: Jonathan Hunter , Vidya Saga , Manikanta Maddireddy , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 2/4] PCI: tegra: Reorder parameters in offset computations Date: Thu, 14 Dec 2017 14:45:43 +0100 Message-Id: <20171214134545.11143-3-thierry.reding@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171214134545.11143-1-thierry.reding@gmail.com> References: <20171214134545.11143-1-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thierry Reding The current computation of the configuration space offset is slightly difficult to read because the fields aren't naturally ordered. This is no doubt done to put extended register and register fields together, but that's confusing because they are separate in the address mapping given in the comment above the computations. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 8a07c6f9e1b0..26b734c84850 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -372,11 +372,11 @@ static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) * address (access to which generates correct config transaction) falls in * this 4 KiB region. */ -static unsigned long tegra_pcie_conf_offset(unsigned char b, unsigned int devfn, - int where) +static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn, + unsigned int where) { - return (b << 16) | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | - (((where & 0xf00) >> 8) << 24) | (where & 0xff); + return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) | + (PCI_FUNC(devfn) << 8) | (where & 0xff); } static int tegra_pcie_add_bus(struct pci_bus *bus) From patchwork Thu Dec 14 13:45:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 848550 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mZf13lc5"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yyFFn3bRKz9t3m for ; Fri, 15 Dec 2017 00:46:05 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753054AbdLNNqB (ORCPT ); Thu, 14 Dec 2017 08:46:01 -0500 Received: from mail-qk0-f194.google.com ([209.85.220.194]:46714 "EHLO mail-qk0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753158AbdLNNp5 (ORCPT ); Thu, 14 Dec 2017 08:45:57 -0500 Received: by mail-qk0-f194.google.com with SMTP id b184so6256799qkc.13; Thu, 14 Dec 2017 05:45:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=99cvBtqFT2ZlND0OlqouDeiafNg4tPZbO5SG/j/+BCk=; b=mZf13lc59erLJ3nXHgiEopDGJnpr7W4O/YvFR74aba8WCtOEyTgYKpOoLVhKHY6pzH gPMhI7Uu2ECFUXoLTM3IRe3lirDVmwMwhxPU7orDONu29/v9qfkCXOSbZcLyQJp0euHH s3FAhxGEyzFhoz5ZrxcOxcazZp2H8Fqth3YmMKiJvleo6QNohuhn/fdX3b4xpPxYGCSs djoB+bj884nQhBKvPr16hCOZjFxgzq6VG6Rr5gunxAx3aAvaHCfkGg8Jo578/H42Ll7X o5BH7tf0xC1ndbYSYgcRvJw+C+RmlaCyGSJRHrDJyYl4bmonNjgjh74m+I+bCBoT/I4C 00pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=99cvBtqFT2ZlND0OlqouDeiafNg4tPZbO5SG/j/+BCk=; b=iTYOdE1MKF+K7AkcJfIu9XTwP74evP94sAZd4tbtXbBmupumUs/lcCJFvoVjrFnuSo i12qlIlVaqqVvQP1uu+Of/jxyh7MCXh5KdFaFvzbf9H1WganH0zvCrxMfGLD7eI/NgJV 7OZTTIQzpuaI54LuOZb0l9r8MdoL075aX219YROBQdxgfjGEjp3WyGsvxSlXp6JBGBWo X8IFlibDaL7NQU9K7R544WfJdT08FFspn8qaRzkX/n+RblM0KaL4rTpNyvOrT6H6zqYT 8D0dV/VRF/4z91MemljRd2xizWJwX/7GqQCsNSbOVpzgkyUupWQONfx2TtvPP4WrkW6I 5O8g== X-Gm-Message-State: AKGB3mKMktbS9BPECh+K2i81L25aGcHl9HSaJkMb35noUTHp20myKK0G qSuEBgJTS+BKuS468SvZC48= X-Google-Smtp-Source: ACJfBoviAC1kk0QOaXcQZm7F1hQsnFrWjFHBHIGYyZ6zKSDrWyQFXv2uWBOao0DeqQiMkOshJD5q3g== X-Received: by 10.55.212.91 with SMTP id l88mr9757196qki.66.1513259157001; Thu, 14 Dec 2017 05:45:57 -0800 (PST) Received: from localhost (p200300E41F200F003F65F430A8AE2E44.dip0.t-ipconnect.de. [2003:e4:1f20:f00:3f65:f430:a8ae:2e44]) by smtp.gmail.com with ESMTPSA id m30sm2644314qtb.29.2017.12.14.05.45.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Dec 2017 05:45:56 -0800 (PST) From: Thierry Reding To: Lorenzo Pieralisi , Bjorn Helgaas Cc: Jonathan Hunter , Vidya Saga , Manikanta Maddireddy , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 3/4] PCI: tegra: Consolidate I/O register variables Date: Thu, 14 Dec 2017 14:45:44 +0100 Message-Id: <20171214134545.11143-4-thierry.reding@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171214134545.11143-1-thierry.reding@gmail.com> References: <20171214134545.11143-1-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thierry Reding Move variables that store I/O register region mappings together for slightly better readability. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 26b734c84850..7f8a81e17db6 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -270,13 +270,12 @@ struct tegra_pcie { void __iomem *pads; void __iomem *afi; + void __iomem *cfg; int irq; struct list_head buses; struct resource *cs; - void __iomem *cfg_va_base; - struct resource io; struct resource pio; struct resource mem; @@ -434,7 +433,7 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, } } else { offset = tegra_pcie_conf_offset(bus->number, devfn, where); - addr = pcie->cfg_va_base + (offset & (SZ_4K - 1)); + addr = pcie->cfg + (offset & (SZ_4K - 1)); val = offset & ~(SZ_4K - 1); afi_writel(pcie, pcie->cs->start - val, AFI_AXI_BAR0_START); afi_writel(pcie, (val + SZ_4K) >> 12, AFI_AXI_BAR0_SZ); @@ -1305,8 +1304,8 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) goto poweroff; } - pcie->cfg_va_base = devm_ioremap(dev, pcie->cs->start, SZ_4K); - if (!pcie->cfg_va_base) { + pcie->cfg = devm_ioremap(dev, pcie->cs.start, SZ_4K); + if (!pcie->cfg) { dev_err(pcie->dev, "failed to ioremap config space\n"); err = -EADDRNOTAVAIL; goto poweroff; From patchwork Thu Dec 14 13:45:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 848552 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cPu18bmf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yyFGT5LPRz9t2f for ; Fri, 15 Dec 2017 00:46:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753018AbdLNNqF (ORCPT ); Thu, 14 Dec 2017 08:46:05 -0500 Received: from mail-qt0-f195.google.com ([209.85.216.195]:44706 "EHLO mail-qt0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752909AbdLNNqA (ORCPT ); Thu, 14 Dec 2017 08:46:00 -0500 Received: by mail-qt0-f195.google.com with SMTP id m59so7916327qte.11; Thu, 14 Dec 2017 05:46:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jRusb0P9/fhmE0pdN4K1+Rm0IJFiKHhJcqPwzSLb1z8=; b=cPu18bmfbUq53U0CBoKhR/ucCfp4w45a0/5vdtM0Ucr0Us8O8BCj1ZXxKCbxhR8TsC LN/+DhPiVvAUWQNrOOEsGj7FU19OC/KlKzQwfefDYjDZXEy9vg8kndCFLZbkdt4hJjqE qSLgwsib7uHIjriH3lavPDYMX9F6czKUD3kReVPCwiwE2noP6j2NbBATnaKoVw9dJlHq CNu/yAlxrjKmBWNfwh3RyqJPUuelTmkoia29faTt2Nq35Qd72dz0X8pz8yG8iG1Mr3ar t2HSp/xXB3q3hSRYUoUwOZOU4yNMEGZqmNm/RxbnpUQfSLvOjnC2ghuH/eYScCqzHViY aeIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jRusb0P9/fhmE0pdN4K1+Rm0IJFiKHhJcqPwzSLb1z8=; b=PmQRQBltg/uf2sCD/hN8d8YPtQGDtf8zgd1Y+r8QgvJXgBNkl9vEbrbICL1X3ih3hI a8emdDhz6kNruh1lsF8fI1/xVvvKC6mgNnggxsligm5603DGi+Cuq5bWPtaHuPlecV94 KUWo4isL9XaWcoHil84xDKazNy4v4AiegJP+dtyIelUj78AjjShiP+Nowbr0cFS6A8Pt +jP2jPphYXOVzRMDw2TW+JKu67En8FwfuzGeyTPnoTusK7xwDc/iS0Wfmgq4W7nJ63Pm WoeWbv76S1JnIg3gtC8Z1lEF98FJjZrAA4u4ujgn7IymA6vEKIsFp+2xuiBE+wQ/Tdii YLcA== X-Gm-Message-State: AKGB3mJ4yLgEElCkUaTobT+8Z6bM1gwqYX96khJVew523xlTuWwrZUpu WaYIZl1rCUOZ0qFJ8src/8c= X-Google-Smtp-Source: ACJfBoug1om0BF6kw2WqwSs9sWRKr/87515beBSxCmz0k3wgYVSF2OS/XRXol02XLwF8xBK/L9buCw== X-Received: by 10.237.54.4 with SMTP id e4mr16496255qtb.67.1513259159750; Thu, 14 Dec 2017 05:45:59 -0800 (PST) Received: from localhost (p200300E41F200F003F65F430A8AE2E44.dip0.t-ipconnect.de. [2003:e4:1f20:f00:3f65:f430:a8ae:2e44]) by smtp.gmail.com with ESMTPSA id b140sm2556885qkc.0.2017.12.14.05.45.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Dec 2017 05:45:59 -0800 (PST) From: Thierry Reding To: Lorenzo Pieralisi , Bjorn Helgaas Cc: Jonathan Hunter , Vidya Saga , Manikanta Maddireddy , linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 4/4] PCI: tegra: Remove artificial mapping restriction Date: Thu, 14 Dec 2017 14:45:45 +0100 Message-Id: <20171214134545.11143-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171214134545.11143-1-thierry.reding@gmail.com> References: <20171214134545.11143-1-thierry.reding@gmail.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Thierry Reding The current code restricts the location of the 4 KiB configuration space mapping region. This is unnecessary if the AFI_FPCI_BAR0 register is used to move the 4 KiB window into the FPCI address map. Doing this will allow all generations of Tegra to be handled in a unified way. Signed-off-by: Thierry Reding --- drivers/pci/host/pci-tegra.c | 46 +++++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 26 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 7f8a81e17db6..2e7bea127120 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -257,7 +257,6 @@ struct tegra_pcie_soc { bool has_gen2; bool force_pca_enable; bool program_uphy; - bool use_4k_conf_space; }; static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip) @@ -274,7 +273,7 @@ struct tegra_pcie { int irq; struct list_head buses; - struct resource *cs; + struct resource cs; struct resource io; struct resource pio; @@ -418,8 +417,6 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, struct pci_host_bridge *host = pci_find_host_bridge(bus); struct tegra_pcie *pcie = pci_host_bridge_priv(host); void __iomem *addr = NULL; - u32 val = 0; - u32 offset = 0; if (bus->number == 0) { unsigned int slot = PCI_SLOT(devfn); @@ -432,11 +429,17 @@ static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus, } } } else { + unsigned int offset; + u32 base; + offset = tegra_pcie_conf_offset(bus->number, devfn, where); + + /* move 4 KiB window to offset within the FPCI region */ + base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8); + afi_writel(pcie, base, AFI_FPCI_BAR0); + + /* move to correct offset within the 4 KiB page */ addr = pcie->cfg + (offset & (SZ_4K - 1)); - val = offset & ~(SZ_4K - 1); - afi_writel(pcie, pcie->cs->start - val, AFI_AXI_BAR0_START); - afi_writel(pcie, (val + SZ_4K) >> 12, AFI_AXI_BAR0_SZ); } return addr; @@ -689,8 +692,9 @@ static void tegra_pcie_setup_translations(struct tegra_pcie *pcie) u32 fpci_bar, size, axi_address; /* Bar 0: type 1 extended configuration space */ - fpci_bar = 0xfe100000; - afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0); + size = resource_size(&pcie->cs); + afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START); + afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ); /* Bar 1: downstream IO bar */ fpci_bar = 0xfdfc0000; @@ -1246,7 +1250,6 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) struct platform_device *pdev = to_platform_device(dev); struct resource *pads, *afi, *res; const struct tegra_pcie_soc *soc = pcie->soc; - u32 axi_addr = 0; int err; err = tegra_pcie_clocks_get(pcie); @@ -1296,18 +1299,14 @@ static int tegra_pcie_get_resources(struct tegra_pcie *pcie) goto poweroff; } - axi_addr = pcie->soc->use_4k_conf_space ? - res->start : res->end - SZ_4K + 1; - pcie->cs = devm_request_mem_region(dev, axi_addr, SZ_4K, res->name); - if (!pcie->cs) { - err = -EADDRNOTAVAIL; - goto poweroff; - } + pcie->cs = *res; - pcie->cfg = devm_ioremap(dev, pcie->cs.start, SZ_4K); - if (!pcie->cfg) { - dev_err(pcie->dev, "failed to ioremap config space\n"); - err = -EADDRNOTAVAIL; + /* constrain configuration space to 4 KiB */ + pcie->cs.end = pcie->cs.start + SZ_4K - 1; + + pcie->cfg = devm_ioremap_resource(dev, &pcie->cs); + if (IS_ERR(pcie->cfg)) { + err = PTR_ERR(pcie->cfg); goto poweroff; } @@ -2120,7 +2119,6 @@ static const struct tegra_pcie_soc tegra20_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, - .use_4k_conf_space = true, }; static const struct tegra_pcie_soc tegra30_pcie = { @@ -2138,7 +2136,6 @@ static const struct tegra_pcie_soc tegra30_pcie = { .has_gen2 = false, .force_pca_enable = false, .program_uphy = true, - .use_4k_conf_space = false, }; static const struct tegra_pcie_soc tegra124_pcie = { @@ -2155,7 +2152,6 @@ static const struct tegra_pcie_soc tegra124_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = true, - .use_4k_conf_space = false, }; static const struct tegra_pcie_soc tegra210_pcie = { @@ -2172,7 +2168,6 @@ static const struct tegra_pcie_soc tegra210_pcie = { .has_gen2 = true, .force_pca_enable = true, .program_uphy = true, - .use_4k_conf_space = false, }; static const struct tegra_pcie_soc tegra186_pcie = { @@ -2190,7 +2185,6 @@ static const struct tegra_pcie_soc tegra186_pcie = { .has_gen2 = true, .force_pca_enable = false, .program_uphy = false, - .use_4k_conf_space = true, }; static const struct of_device_id tegra_pcie_of_match[] = {